SSM9971GM Dual N-channel Enhancement-mode Power MOSFETs PRODUCT SUMMARY BVDSS 60V R DS(ON) 50mΩ ID 5A DESCRIPTION The SSM9971GM acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM2310GM is supplied in an RoHS-compliant SO-8 package, which is widely used for medium power commercial and industrial surface mount applications. Pb-free; RoHS-compliant SO-8 D2 D2 D1 D1 G2 S2 SO-8 S1 G1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDS Drain-source voltage VGS Gate-source voltage ID IDM PD Continuous drain current Pulsed drain current 3 , Value Units 60 V ± 25 V T A = 25°C 5 A TA = 100°C 3.2 A 30 A 2 W 0.016 W/°C 1,2 3 Total power dissipation , TA = 25°C Linear derating factor TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol RΘJA Parameter Maximum thermal resistance, junction-ambient 3 Value Units 62.5 °C/W Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 135°C/W when mounted on the minimum pad area required for soldering. 10/16/2005 Rev.3.1 www.SiliconStandard.com 1 of 5 SSM9971GM ELECTRICAL CHARACTERISTICS Symbol (at Tj = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. Max. Units 60 - - V BVDSS Drain-source breakdown voltage VGS=0V, ID=250uA ∆ BV DSS/∆ Tj Breakdown voltage temperature coefficient Reference to 25°C, ID=1mA - 0.06 - V/°C RDS(ON) Static drain-source on-resistance2 VGS=10V, ID=5A - - 50 mΩ VGS=4.5V, ID=2.5A - - 60 mΩ VDS=VGS, ID=250uA 1 - 3 V VGS(th) Gate threshold voltage gfs Forward transconductance VDS=10V, ID=5A - 7 - S IDSS Drain-source leakage current VDS=60V, VGS=0V - - 1 uA VDS=48V ,VGS=0V, Tj = 70°C - - 25 uA VGS=±25V - - ±100 nA ID=5A - 32.5 - nC IGSS Gate-source leakage current 2 Qg Total gate charge Qgs Gate-source charge VDS=48V - 4.9 - nC Qgd Gate-drain ("Miller") charge VGS=10V - 8.8 - nC VDS=30V - 9.6 - ns 2 td(on) Turn-on delay time tr Rise time ID=5A - 10 - ns td(off) Turn-off delay time RG=3.3Ω , VGS=10V - 30 - ns tf Fall time RD=6Ω - 5.5 - ns Ciss Input capacitance VGS=0V - 1658 - pF Coss Output capacitance VDS=25V - 156 - pF Crss Reverse transfer capacitance f=1.0MHz - 109 - pF Min. Typ. IS=1.6A, VGS=0V - - 1.2 V Source-Drain Diode Symbol Parameter 2 Test Conditions Max. Units VSD Forward voltage trr Reverse-recovery time IS=5A, VGS=0V, - 29.2 - ns Qrr Reverse-recovery charge dI/dt=100A/µs - 48 - nC Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 10/16/2005 Rev.3.1 www.SiliconStandard.com 2 of 5 SSM9971GM 35 35 o o T A =25 C 25 20 15 10 V G =3.0V 25 20 15 V G =3.0V 10 5 5 0 0 0 1 2 3 4 5 0 1 V DS , Drain-to-Source Voltage (V) 2 3 4 5 V DS , Drain-to-Source Voltage (V) Fig 1. Typical output characteristics Fig 2. Typical output characteristics 52 3.0 I D =5A I D =5A V G =10V 2.5 o T A =25 C Normalized R DS(ON) 48 RDS(ON) (mΩ ) 10V 6.0V 4.5V 30 ID , Drain Current (A) ID , Drain Current (A) T A =150 C 10V 6.0V 4.5V 30 44 40 2.0 1.5 1.0 36 0.5 0.0 32 3 5 7 9 -50 11 0 50 100 150 T j , Junction Temperature ( o C) V GS , Gate-to-Source Voltage (V) Fig 3. On-resistance vs. gate voltage Fig 4. Normalized on-resistance vs. junction temperature 100 3 2.5 10 T j =25 o C VGS(th) (V) IS (A) 2 T j =150 o C 1 1.5 1 0.1 0.5 0 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 V SD , Source-to-Drain Voltage (V) Fig 5. Forward characteristic of the reverse diode 10/16/2005 Rev.3.1 1.5 -50 0 50 100 150 o T j ,Junction Temperature ( C) Fig 6. Gate threshold voltage vs. junction temperature www.SiliconStandard.com 3 of 5 SSM9971GM f=1.0MHz 14 10000 I D =5A VGS , Gate to Source Voltage (V) 12 V DS =48V V DS =38V V DS =30V 10 Ciss 1000 8 6 Coss Crss 100 4 2 0 0 5 10 15 20 25 30 35 40 10 1 Q G , Total Gate Charge (nC) Fig 7. Gate charge characteristics 5 9 13 17 21 V DS , Drain-to-Source Voltage (V) 25 29 Fig 8. Typical capacitance characteristics 1 100 Normalized Thermal Response (R θja) Duty foctor=0.5 10 ID (A) 1ms 10ms 1 100ms o T A =25 C Single Pulse 0.1 1s DC 0.01 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t Single Pulse T Duty factor = t/T Peak T j = PDM x Rthja + Ta R θja=135°C/W 0.001 0.1 1 10 100 1000 0.0001 0.001 0.01 V DS , Drain-to-Source Voltage (V) Fig 9. Maximum safe operating area 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective transient thermal impedance VG VDS 90% QG 10V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching time waveforms 10/16/2005 Rev.3.1 Charge Q Fig 12. Gate charge diagram www.SiliconStandard.com 4 of 5 SSM9971GM PHYSICAL DIMENSIONS D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e e A A1 C B L 1.27(TYP) H 5.80 6.50 L 0.38 1.27 All dimensions in millimeters. Dimensions do not include mold protrusions. PART MARKING PART NUMBER: 9971GM XXXXXX YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a 13 inch (330mm) reel, packed in a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/16/2005 Rev.3.1 www.SiliconStandard.com 5 of 5