ZARLINK PLUTO

Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
PLUTO
Dual Mode CDMA/AMPS Baseband Interface
Advance Information
DS4722 - 1.8 July 1998
The PLUTO baseband interface circuit is designed for use
in dual mode CDMA/AMPS digital cellular telephones. In the
telephone, Pluto provides the interface between the radio (RF
& IF) components and the baseband digital signal processor.
Pluto is part of a complete chipset solution for CDMA phones
entitled the Planet chipset.
The receive (RX) section converts the analog in-phase and
quadrature (I & Q) signals into equivalent digital signals whilst
the transmit (TX) circuits perform the complementary function
of translating digital baseband information into the analog
equivalent signals required for the modulator in the radio
circuits. VHF PLLS are also included for second RXLO and
TXIF generation.
PLUTO also contains a 4 channel general purpose ADC
which is included for such purposes as environmental and
signal strength monitoring.
PIN 1 IDENT
PIN 80
FEATURES
GP80
MP28
PIN 1
Figure 1 Pin connections - top view
■ Dual mode AMPS/CDMA compatible
■ Low Power/Low Voltage operation
ABSOLUTE MAXIMUM RATINGS
■ Standard baseband I and Q interface
APPLICATIONS
Supply voltage
Voltage applied to any other pin
Operating junction temperature
Storage temperature
ESD (human body model)
■ Dual Mode CDMA/AMPs digital cellular
telephones
ORDERING INFORMATION
PLUTO/KG/GP1R
■ 4 Input Auxiliary ADC
■ Synthesisers
TXQ,TXQTXI,TXI-
FM_MOD
TXIF PD_RX
PD_TX
RXIF
TX
SYNTH
TCXO/4
/4
-0.3 to 3.9V
-0.3 to Vcc+0.3V
150°C
-55°C to 150°C
2kV
ADC<3> ADC<1>
FC_I
I+,I-
BAL
Q+,Q-
FC_Q
ADC<2> ADC<0>
ANALOG
MULTIPLEXER
RX
SYNTH
8-BIT
DAC
8-BIT
DAC
S<0>
S<1>
8-BIT
DAC
VDD
GND
8-BIT
DAC
1025
8-BIT
DAC
8-BIT 6-BIT
ADC ADC
6-BIT 8-BIT
ADC ADC
8-BIT
ADC
SUB
FM/
CHIPx8
512
SLEEP/
IDLE/
RESET/
19.68MHz
BUFFER
rx calibration and control
tx calibration and control
SDATA
SCLOCK
SLATCH
TCXO
TXCLK
TXD<7:0>
RXIFMDATA
RXID<3:0>
ADCENA
ADCDATA
ADCCLK
RXQFMDATA
RXQD<3:0>
Figure 2 Block diagram
PLUTO
PIN DESCRIPTION
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
2
Pin Name
VDD
RSET
GND
TX_IF
IDLEB
PD TX
FMB
PD_RX
SLEEPB
RX_IF
TX_LOCK
RX_LOCK
TCXO/4
TXD<0>
TXD<1>
TXD<2>
TXD<3>
TXD<4>
TXD<5>
TXD<6>
TXD<7>
TXCLK
TXCLKB
CHIPx8
VDD
TCXO
GND
SUB
RESET
SDATA
SCLK
SLATCH
S<0>
n/c
RXID<0>
RXID<1>
RXID<2>
RXID<3>
S<1>
n/c
RXQD<0>
RXQD<1>
RXQD<2>
RXQD<3>
GND
VDD
RXFMSTB
FMCLK
RXQFMDATA
RXIFMDATA
ADCLK
ADCDATA
ADCENA
SUB
Type
Power
Input
Ground
Input
Digital
Output
Input
Output
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Input
Ground
Ground
Input
Input
Input
Input
Input
A/D
Digital
Digital
Digital
Digital
Digital
Description
Power Supply
Bias current setting resistor - 40kΩ to ground
Ground
TX VCO output
Idle mode control signal - active low - pulled low if left unconnected
TX synthesiser charge pump output
FM mode control signal - active low - pulled low if left unconnected
RX synthesiser charge pump output
Sleep mode control signal - active low - pulled low if left unconnected
RX VCO output
TX synthesiser lock detect open drain output - pulled high by ext. resistor
RX synthesiser lock detect open drain output - pulled high by ext. resistor
TCXO divided by 4 output
Transmit data bit 0 (lsb)
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
Transmit data bit 4
Transmit data bit 5
Transmit data bit 6
Transmit data bit 7 (MSB)
Complimentary Transmit Clock (+ve)
Complementary Transmit Clock (-ve)
9.8304MHz synthesiser output
Power Supply
TCXO 19.68MHz a.c. coupled sinewave input
Ground
Substrate-Ground
Chip master reset - pulled high if not connected
Serial Interface Data Input
Serial Interface Clock Input
Serial Interfce Latch Input
Aux ADC mux channel select LSB
Output
Output
Output
Output
Input
Digital
Digital
Digital
Digital
Digital
I-Channel RX CDMA output LSB - low when inactive
I-Channel RX CDMA output bit 1 - low when inactive
I-Channel RX CDMA output bit 2 - low when inactive
I-Channel RX CDMA output bit 3 - low when inactive
Aux ADC mux channel select MSB
Output
Output
Output
Output
Ground
Power
input
Input
Output
Output
Output
Output
Input
Ground
Digital
Digital
Digital
Digital
Q_Channel RX CDMA output LSB - low when inactive
Q_Channel RX CDMA output bit 1 - low when inactive
Q_Channel RX CDMA output bit 2 - low when inactive
Q_Channel RX CDMA output bit 3 - low when inactive
Ground
Power Supply
Receive data FM strobe - pulled low if not connected
Receive data FM clock - pulled low if not connected
Q-Channel RX FM data serial output - low when inactive
I-Channel RX FM data serial output -low when inactive
Auxiliary ADC serial data clock. Low when inactive
Auxiliary ADC serial data output. Low when inactive
Auxiliary ADC enable - pull down if not used
Substrate - Ground
Analog
Analog
Digital
Analog
Digital
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
PLUTO
PIN DESCRIPTION (continued)
No
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
RXQP
RXQM
SUB
RXIP
RXIM
VDD
GND
VREF<0>
AD<0>
AD<1>
AD<2>
AD<3>
Vtest
EnTest
FC_Q
FC_I
BAL
VDD
GND
TXIP
TXIM
SUB
TXQP
TXQM
FMTX
VREF<1>
Type
Input
Input
Ground
Input
Input
Power
Ground
Input/Output
Input
Input
Input
Input
Output
Output
Output
Output
Output
Power
Ground
Output
Output
Ground
Output
Output
Output
Input/Output
A/D
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Digital
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Description
Receive Q Channel Input (+ve)
Receive Q Channel Input (-ve)
Substrate - Ground
Receive Q channel input (+ve)
Receive Q channel Input (-ve)
Power Supply
Ground
CDMA Receive Circuit Voltage Reference De-Coupling
AUX ADC Input
AUX ADC Input
AUX ADC Input
AUX ADC Input
RX Filter tuning tone output - pulled low when inactive
RX Filter tuning mode control output - pulled low when inactive
RX Filter Q channel FC control
RX Filter channel FC control
RX Filter Gain Balance Control
Power Supply
Ground
Transmit Circuit channel Complementary Output (+ve)
Transmit Circuit I channel Complementary Output (-ve)
Substrate - Ground
Transmit Circuit Q channel Complementary Output (+ve)
Transmit Circuit Q channel Complementary Output (-ve)
Transmit Circuit FM output
Transmit Circuit Voltage Reference De-coupling
FUNCTIONAL DESCRIPTION
Baseband TX interface circuit
The Pluto baseband transmit circuit acts as an interface
between the baseband signal processor and the RF/IF sections
in a CDMA/AMPS compatible mobile telephone.
The TX circuit has two modes of operation :
CDMA mode, transmit data that has previously been encoded
by the baseband digital signal processor is converted to
equivalent analog signals by matched digital-to-analog
converters, these signals are then filtered to remove the image
of the sample clock that would otherwise be present at the
output before being output to the I and Q modulator as
differential signals.
FM mode, transmit data is treated in much the same way as
in CDMA mode except that only one DAC is used and (because
of the much lower bandwidth of AMPS signals) a different
reconstruction filter is used before the analog fm signal is output
to the mixer as a single ended signal.
CDMA Transmit Signal Path
CDMA TX DACs
In CDMA mode two matched 8-bit DACs are used to
generate the in-phase and quadrature signals, the input
data for the DACs is obtained by multiplexing over an 8-bit
parallel input port (TXD<7:0>). The transmit data rate is
twice as fast as the differential transmit clock (TXCLK).
Incoming data that is valid during the rising edge of the
transmit clock is loaded into in In-Phase DAC & incoming
data that is valid on the falling edge of the transmit clock is
loaded into the Quadrature DAC - I and Q values must be
modified in the digital baseband chip to account for the halfcycle delay between them.
CDMA Analog Reconstruction Filters
The frequency spectrum at the output of the transmit
DACs contains unwanted frequency components.
Reconstruction filters are used to smooth the DAC output
signals, providing continuous time output signals at the I and
Q output pins thereby removing these undesirable signals.
The low pass filters used are 5th order Butterworth,
continuous time filters with a nominal cut-off frequency of 1.2
MHz. These filters are designed to have a linear phase
response in the pass band. On-chip reconstruction filters
minimise the phase and amplitude mismatch between I and
Q channels.
3
PLUTO
CDMA TX Section Analog Interface
The ITx and QTx outputs can be d.c. or a.c. coupled to the
external circuits and will differentially drive a minimum
resistive load of 5 kΩ and a maximum capacitive load of 20 pF.
When the CDMA transmit path is in power-down mode the
positive outputs goes high and the negative output goes low.
FM Transmit Signal Path
FM TX DAC
In FM mode, the Q-Channel DAC is used to generate an
analog FM modulation signal from the data transmitted from
the digital baseband processor. In this mode, all other CDMA
TX circuits are powered down.
FM Mode Analog Reconstruction Filters
The frequency spectrum at the output of the transmit DAC
contains unwanted frequency components. A reconstruction
filter is used to smooth the DAC output signals.
Low-pass filters are used with a cut-off frequency of
approximately 13 kHz. These filters are 3rd order Butterworth
filters.
FM TX Section Analog Interface
The FMTX output can be d.c. or a.c. coupled to the radio
circuits and will drive a minimum resistive load of 5 kΩ and a
maximum capacitive load of 20 pF.
When the FM mode is in power-down the output is in high
impedance state.
CDMA Receive Signal Path
CDMA Receive ADC
In CDMA mode two high speed 4-bit ADCs are used to
digitise the incoming signals before subsequent transmission
to the baseband digital signal processor as two parallel 4 bit
words (RXI<3:0> and RXQ<3:0>). The sample rate of
9.8304MHz is generated via an on chip synthesiser that
requires no setting up or external components. On each falling
edge of the synthesised clock (CHIPx8) a new digital sample
is output on the digital bus.
4
CDMA Receive Calibration Circuit
On entering into CDMA mode from power down or from FM
mode the calibration circuits are activated. These circuits
measure the differences between the receive path gain in the
pass band and in the transition band of both I and Q filters. Via
a successive approximation process they tune the receive
filters cut-off frequency and amplitude matching using the 8 bit
DACs provided for this purpose (I_FC, Q_FC and BAL). Once
both filters (I and Q) have been calibrated in this way the DAC
outputs will not change until the chip is powered down or the
calibration circuit is re-activated in some other way.
FM Receive Signal Path
In FM mode two low speed 8-bit ADCs are used to digitise
the incoming signals before subsequent transmission to the
baseband digital signal processor as two serial 8-bit words
(FMRXI & FMRXQ). The sample rate is entirely determined by
the digital baseband processor (up-to the maximum allowed)
via the FMCLK input.
In FM mode the receive filters are assumed to track the
filters used in CDMA mode i.e. there is no separate tuning
mechanism.
SYNTHESISERS
The Synthesiser block comprises the input buffers, main
dividers, phase comparator, charge pump and lock detect
circuit for a TX and RX synthesiser. The loop filter components
and the VCOs are external to the device. A common reference
divider chain is also included together with bias and control
circuitry. All blocks apart from reference divider, bias and
control logic are duplicated exactly for RX and TX
synthesisers.
The receive intermediate frequency (RX_IF) is
programmable and the transmit intermediate frequency
(TX_IF) is fixed at 130.38MHz.
AUX ADC
The auxiliary converter section contains a single 8-bit
successive approximation analog to digital converter, with
serial output. In order to maximise the flexibility of Pluto, a 4
way analog multiplexer is provided, which enables the
converter to encode any one of four selectable channels. The
converter is intended for such applications as power supply
and temperature monitoring. When not in use, the converter is
powered down, and its outputs are held low.
PLUTO
TIMING INFORMATION
Parameter
Value
Min
Typ
Units
Conditions
Max
t1
TXCLOCK PERIOD (CDMA TX)
203.2
ns
CDMA TX Figure 3
t2
t3
TXCLOCK HIGH TIME (CDMA TX)
TXCLOCK LOW TIME (CDMA TX)
101.6
101.6
ns
ns
CDMA TX Figure 3
CDMA TX Figure 3
t4
t5
TXCLOCK PHASE Delay (CDMA TX)
TXCLOCK RISE TIME (CDMA TX)
1.2
12
ns
ns
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
t6
t7
TXCLOCK FALL TIME (CDMA TX)
TXD-TXCLOCK SETUP TIME
12
20
ns
ns
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
t8
TXCLOCK-TXD HOLD TIME
3
ns
CDMA TX Figure 3, FM TX Figure 4
t11 TXCLOCK PERIOD (FM TX)
t12 TXCLOCK HIGH TIME (FM TX)
2.78
1.39
µs
µs
FM TX Figure 4
FM TX Figure 4
t13 TXCLOCK LOW TIME (FM TX)
t14 CHIPx8 PERIOD
1.39
101.6
µs
ns
FM TX Figure 4
Figure 5
t15 CHIPx8 HIGH TIME
t16 CHIPx8LOW TIME
50.8
50.8
152.4
ns
ns
Figure 5
Figure 5
12
12
ns
ns
Figure 5
Figure 5
20
ns
ns
Figure 5
Figure 5
µs
µs
FM RX Figure 6
FM RX Figure 6
µs
ns
FM RX Figure 6
FM RX Figure 6
t17 CHIPx8 RISE TIME
t18 CHIPx8 FALL TIME
3
3
t19 RXD Hold Time After CHIPx8↓
t20 RXD DELAY After CHIPx8↓
10
t21 FMCLK PERIOD
t22 FMCLK HIGH TIME
2.78
1.39
t23 FMCLK LOW TIME
t24 FMCLK RISE TIME
1.39
12
t25 FMCLK FALL TIME
t26 RXFMSTB HIGH TIME
1
12
ns
µs
FM RX Figure 6
FM RX Figure 6
t27 RXFMSTB -FMCLK↓ SETUP TIME
t28 FMCLK↓ − RXFMSTB HOLD TIME
50
50
ns
ns
FM RX Figure 6
FM RX Figure 6
ns
µs
FM RX Figure 6
General purpose ADC Figure 7
ns
ns
General purpose ADC Figure 7
General purpose ADC Figure 7
t29 FMCLK↓ − OUTPUT DATA DELAY
t30 ADCENA HIGH _ CONVERSION
t31 ADCENA HIGH TIME
t32 ADCENA LOW TIME
50
40
100
100
t33 ADCCLK PERIOD
t34 ADCCLK HIGH TIME
2.44
0.81
µs
µs
General purpose ADC Figure 7
General purpose ADC Figure 7
t35 ADCCLK LOW TIME
t36 ADCCLK RISE TIME
1.62
µs
ns
General purpose ADC Figure 7
General purpose ADC Figure 7
ns
µs
General purpose ADC Figure 7
General purpose ADC Figure 7
12
t37 ADCCLK FALL TIME
t38 ADCDATA VALID BEFORE ADCCLK↑
12
1
t39 ADC DATA HOLD TIME
t40 SCLK-SDATA setup time
5
20
ns
ns
General purpose ADC Figure 7
Serial Interface Figure 8
t41 SCLK-SDATA hold time
t42 SCLK pulse width
20
50
ns
ns
Serial Interface Figure 8
Serial Interface Figure 8
t43 SLATCH-SCLK setup time
t44 SLATCH pulse width
20
50
ns
ns
Serial Interfsce Figure 8
Serial Interface Figure 8
t45 SCLK period
100
ns
Serial Interface Figure 8
5
PLUTO
t1
t2
t3
t4
t4
TXCLK
t6
t5
//
//
TXCLKbar
//
TXD<7:0>
//
t7
t8
t9
t10
Figure 3 CDMA TX Mode
t11
t12
t13
t4
t4
t6
t5
TXCLK
TXCLKbar
TXD<7:0>
t9
t10
Figure 4. FM TX MODE
t14
t15
t16
t17
t18
CHIPx8
RXQD<3:0>
RXID<3:0>
t19
t20
Figure 5. CDMA RX MODE
6
PLUTO
t21
t22
t25
t24
t23
FMCLK
t26
RXFMSTB
t27
t28
RXIFMDATA
LSB-1
LSB
MSB
RXQFMDATA
t29
Figure 6. FM RX MODE
t30
t32
t31
t37
t33
ADCENA
ADCCLK
t34
t36
t35
MSB
LSB
ADCDATA
t38
t39
Figure 7. General purpose ADC
t40
t45
t43
t42
SLATCH
t44
SCLK
LSB
MSB
SDATA
t41
Figure 8. Serial interface
7
PLUTO
PROGRAMMING and CONTROL
The control modes for Pluto can be set via external pins or via a 3 wire serial interface. On initialising Pluto control is from
external pins but can then be set for programming from the serial interface by setting the appropriate bit in a serial input word.
The Rx second LO synthesiser is programmed via the serial interface: the Tx IF synthesiser is fixed and requires no programming.
Mode Control - External
The control modes are set by the pins SLEEPB, FMB and IDLEB as shown in the table below:
SLEEPB
FMB
IDLEB
Mode
(Pin 9)
(Pin 7)
(Pin 5)
0
X
X
Sleep Mode
1
0
0
FM Receive only
1
0
1
FM Receive and Transmit
1
1
0
CDMA Receive only
1
1
1
CDMA Receive and Transmit
Aux ADC Selection - External
The auxiliary analog to digital converters can be selected via pins S0 and S1 as shown in the table below:
S1
S0
ADC
(Pin 39)
(Pin 33)
selected
0
0
ADC<0>
0
0
ADC<1>
1
0
ADC<2>
1
1
ADC<3>
ADC selection can also be programmed to be via serial interface if required
Serial Interface
The 3 wire serial interface (SDATA, SCLK and SLATCH) is programmed using 24 bit words as shown below. Timing
details are shown in Figure 8.
MSB
WORD1
WORD2
LSB
23
22
21
20
19
18
17
16
0
0
0
0
0
X
X
RXC
0
0
0
0
SOP FMB IDB SLB
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RXDIV<13:0>
0
0
AD1 AD0 TST
0
0
0
0
0
MXS CTB
0
0
1
0
0
0
0
1
unused
RXC
RX Synth comparison frequency :0 = 30kHz, 1 = 5kHZ
RXDIV<13:0>
RX Synth divider ratio
SOP
External/ Serial mode selection: 0 = Ext, 1 = Serial
SLB, IDB, FMB
Sleep, Idle and FM mode control bits (serial mode)
TST
Test Mode Control - This is for test purposes only and should be set to 0
AD1, AD0
Aux ADC select bits (serial mode)
MXS
External / Serial Aux ADC select: 0 = Ext
CTB
Enable Rx Calibration: 0 = calibration mode
If SOP is high mode control is via serial bits FMB, IDB and SLB, instead of external pins FMB, IDLEB and SLEEPB.
If MXS is high then ADC selection is via AD1, AD0 instead of S<1>, S<0>
8
PLUTO
INITIALISATION
Transmit
On power-up or reset (RESETB) the Tx reconstruction
filters are tuned to give the specified cut-off frequency. This
calibration is internal and requires no external input. The
calibration time is 1ms.
Receive
On power-up or reset (RESETB) an autocalibration algorithm is started which can be used to tune the programmable
filters in Jupiter. (Jupiter is a programmable active filter designed for use in dual mode CDMA/AMPS system -further
details of which can be found in the Jupiter Datasheet). The
autocalibration is also initiated when Pluto is switched into
CDMA mode via FMB control.
0
-0.8
-4
CDMA TX FILTER RESPONSE
When Pluto enters calibration mode the En Test (pin 68)
goes high. A test signal at 364kHz is then generated at the
Vtest output (pin 67). This signal is input to Jupiter which
provides a response which is digitised by the I and Q Rx ADCs.
An output DAC - BAL - (Pin 71) then tunes the Q channel to
match the I and Q channel amplitude via a successive approximation routine. The test signal is then switched to 728kHz
which is above the required cut off of the filter. DAC outputs,
FC_I and FC_Q are then adjusted to tune the I and Q filters to
the correct amplitude with reference to the in band test signal.
The filter cut off is tuned to 690kHz. Oversampling in the Rx
ADC's ensures sufficient accuracy for the calibration. This
calibration routine takes 26ms and after completion En Test
goes low and the test signal Vtest is disabled. Only the CDMA
filter is tuned, the matching within Jupiter ensures that the FM
(AMPS) filter performance meets specification.
0
-0.6
Relative
Amplitude
(dB)
Relative
Amplitude
(dB)
-5.8
-3.0
1k
630k
1.25M
FM TX FILTER RESPONSE
10M
Frequency (Hz)
10k
29k
100k
Frequency (Hz)
Figure 9 Baseband RX interface circuit
9
PLUTO
RECOMMENDED OPERATING CONDITIONS
Characteristic
Value
Min
Operating voltage range
Operating temperature range
Input high voltage, VIH
Input low voltage, VIL
Master clock amplitude
Units
Typ
Conditions
Max
2.7
3.6
V
-40
VDD-0.8
+85
°C
V
0.8
V
mV pk-pk
800
AC coupled 19.68MHz sinusoidal
signal
Input current, IIH
Input capacitance, CIN
Output high voltage, VOH
0.1
µA
5
pF
V
0.4
10
V
µA
VDD-0.4
Output low voltage, VOL
Tri-state leakage current
IOUT = 100µA
IOUT = 100µA
ELECTRICAL CHARACTERISTICS
TAMB = -30°C to +70°C, VCC = +2.7 to +3.6V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Value
Min
Typ
Units
Conditions
Max
CDMA TX Interface
Resolution
8
Bits
Integral non-linearity
0.5
LSB
Differential non-linearity
0.5
LSB
V
Full scale output Voltage
Output common mode Voltage
+Ve output Voltage in Power-down mode
-Ve output Voltage in Power-down mode
1.6
2.05
2.4
1.1
1.2
1.3
Vdd-0.16 Vdd-0.1 Vdd-0.04
0.04
0.1
I,Q gain mismatch
I,Q phase imbalance
Differential offset
PSRR
0.16
V
V
V
0.15
dB
1
degrees
TBD
mV
50
Vpp differential
dB
VDD to differential I & Q outputs,
100mV pk-pk at 100kHz
Load resistance
5
kΩ
Load capacitance
20
Filter type
Filter order
pF
Butterwoth low pass
5th
Filter cut off
See Figure 9
Filter Pass Band ripple
See Figure 9
Filter stop band attenuation
Sample rate
10
See Figure 9
6
Msample/s
PLUTO
ELECTRICAL CHARACTERISTICS (continued)
TAMB = -30°C to +70°C, VCC = +2.7 to +3.6V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Value
Min
Typ
Units
Conditions
Max
FM TX Interface
Resolution
Integral non linearity
8
0.5
0.5
Bits
LSB
Differential non linearity
Output Voltage range
550
LSB
mVpp
Output Voltage mid scale
PSRR
0
50
V
dB
Differential
Vdd to output, 100mV
pk-pk at 100kHz
Load resistance
5
kΩ
Load capacitance
Filter type
20
pF
Butterworth low pass
Filter order
Filter Pass Band ripple
3rd
See Figure 9
Filter stop band attenuation
Filter cut-off
CDMA RX Interface
Resolution
See Figure 9
See Figure 9
4
Full scale input voltage
Input common mode range
Input sample rate
Input resistance (dc)
Input capacitance
Integral non linearity
Differential non linearity
IRX and QRX gain matching
Bits
1
Vdd -1.4
V pk-pk
V
9.8304
Ms/s
kΩ
20
10
20
0.15
pF
LSB
0.175
0.25
LSB
dB
Measured differentially
11
PLUTO
ELECTRICAL CHARACTERISTICS (CDMA BASEBAND RX INTERFACE CIRCUIT) continued
TAMB = -30°C to +70°C, VCC = +2.7 to +3.6V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Value
Min
Typ
Units
Conditions
Max
FM RX Interface
Resolution
Full scale input voltage
8
Input dc level
Input sample rate
Input resistance (dc)
Input capacitance
Vdd-1.4
30
ADC full scale range
ADC zero scale range
10
12
V
ks/s
20
kΩ
pF
±1.5
±0.75
LSB
LSB
8
Bits
2.5
0.5
V
V
±1.25
±0.75
Integral non linearity
Differential non linearity
Conversion time
ADCCLK
50
100
Integral non linearity
Differential non linearity
AUXILIARY CONVERTER SECTION
Resolution
Bits
V pk-pk
1
20
410
LSB
LSB
ks/s
kHz
Measured differentially
PLUTO
ELECTRICAL CHARACTERISTICS (Continued)
TAMB = -30°C to +70°C, VCC = +2.7 to +3.6V. These characteristics are guaranteed by either production test or design. They
apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Characteristic
Value
Min
TRANSMIT SYNTHESISER
Input Frequency
Lock mode output current current
Acquisition mode output current
PD output compliance
RECEIVER SYNTHESISER
Input frequency
Lock mode output current
Acquisition mode output current
PD output compliance
Typ
Units
Max
65.19
MHz
16
176
µA
µA
0.5
42.69
Vdd-0.5
V
52.595
MHz
µA
16
176
0.5
POWER SUPPLY CURRENTS
Sleep
Conditions
Vdd-0.5
V
V
1
mA
CDMA_IDLE
FM_ILDE
11
5
15
7
mA
mA
CDMA_RTTX
FM_RXTX
18
11
32
15
mA
mA
Rset = 40kΩ
Rset = 40kΩ
Rset = 40kΩ
Rset = 40kΩ
13
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE