STMICROELECTRONICS TDA8204B

TDA8204B
NICAM DECODER
HIGHLY INTEGRATED TWO-CHIP SOLUTION FOR NICAM DEMODULATION (using
TDA8205 QSPK)
DATA AND SOUND RECOVERY ACCORDING
TO EBU SPB 424 SPECIFICATIONS
I2S INTERFACE FOR DIGITAL AUDIO PURPOSES (14-bit samples, 32kHz word select
clock, 896kHz serial clock)
4 TIMES UP SAMPLING DIGITAL FILTER
AND NOISE SHAPER
I2C INTERFACE FOR MICROCONTROLLER
SOFTWARE DRIVE
PAY TV APPLICATION CAPABILITIES
AUTOMATIC ERROR MONITORING
(programmable error rate limit)
DESCRIPTION
The TDA8204B performs two main functions, first
one is NICAM decoding, second one is audio signal
recovery (DAC) combined with audio signal switching (Matrix). An I2S output is provided for digital
audio when required and all functions of both the
TDA8204B and the TDA8205 are accessed via an
on-chip I2C bus interface. The I2S interface can be
used as an input for converting to analog some I2S
digital sound.
November 1994
SHRINK 42
(Plastic Package)
ORDER CODE : TDA8204B
PIN CONNECTIONS
GND
1
42
CK11648
DACDR
2
41
TEST2
DACDL
3
40
CK728
SERI
4
39
NDI
VDD
5
38
GND
RSW
6
37
TEST
HA0
7
36
TEST1
TEST0
8
35
SEL0
US2
9
34
SEL1
US1
10
33
DV
US0
11
32
VDD
SCL
12
31
ADV
SDA
13
30
PDV
SD
14
29
FID
SCK
15
28
DDO
WS
16
27
DDI
VDD
17
26
GND
C4
18
25
MUTE
C3
19
24
RESET
C2
20
23
ER
C1
21
22
GND
8204B-01.EPS
.
.
.
.
.
..
1/12
TDA8204B
Pin No
1
2
3
4
5
6
PIn Name
GND
DACDR
DACDL
SERI
VDD
RSW
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
HA0
TEST0
US2
US1
US0
SCL
SDA
SD
SCK
WS
VDD
C4
C3
C2
C1
Function
Ground
PWM Data Output Right
PWM Data Output Left
Inter Chip Serial Bus Output
+5V Supply
Reserve Sound Switch
Status/Control
Hardware Address Selection
To be connected to VDD or GND
User bit 2 (input)
User bit 1 (output)
User bit 0 (output)
I2C Bus Clock
2
I C Bus Data
I2S Bus Data
2
I S Bus Clock
I2S Bus Word Select
+5V Supply
Application Control Bit 4 Flag
Application Control Bit 3 Flag
Application Control Bit 2 Flag
Application Control Bit 1 Flag
Pin No
22
23
24
25
26
27
Pin Name
GND
ER
RESET
MUTE
GND
DDI
Function
Ground
Error Monitor Flag Output
Reset
NICAM Mute
Ground
Descrambled Data Input
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DDO
FID
PDV
ADV
VDD
DV
SEL1
SEL0
TEST1
TEST
GND
NDI
CK728
TEST2
CK11648
Descrambled Data Output
Frame Identification Flag Output
Parity Data Valid Flag Output
Additional Data Valid Flag Output
+5V Supply
Data Valid Flag Output
Language Selection 1 Input
Language Selection 0 Input
Not to be connected
To be connected to GND
Ground
NICAM Data Input
728kHz bit Clock Output
Not to be connected
11.648MHz bit Clock Input
8204B-01.TBL
PIN ASSIGMENT
SCK
WS
SD
V DD
V DD
V DD
33
29
23
35
34
15
16
14
5
17
32
DIGITAL
FILTER
I2 S
CK11648 42
SERIAL
BUS
C1
C2
C3
C4
10
9
7
8
1 22
26 38
GND
PDV
11
GND
MUTE
4
SERI
TEST0
18
HA0
19
13 SDA
US2
20
12 SCL
I 2 C INTERFACE
US1
21
2 DACDR
US0
30
TEST
25
TEST2
41 36 37
TEST1
RESET 24
3 DACDL
NOISE
FILTER
8204B-02.EPS
NICAM DECODER
GND
CK728 40
GND
31
SEL1
ADV
6
SEL0
RSW
27
ER
DDI
28
DV
DDO
39
FID
NDI
BLOCK DIAGRAM
Parameter
Supply Voltage
Total Power Dissipation
Operating Temperature Range
Storage Temperature Range
Value
7
1.2
0, + 70
- 20, + 150
Unit
V
W
o
C
o
C
8204B-02.TBL
Symbol
VDD
Ptot
Toper
Tstg
Unit
C/W
8204B-03.TBL
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
Symbol
Rth (j-a)
2/12
Parameter
Thermal Resistance Juntion-ambient
Max.
Value
67
o
TDA8204B
ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VDD = 5V, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.75
30
5
45
5.25
90
V
mA
0.4
V
V
SUPPLY
VDD
IDD
Supply Voltage Range
Supply Current
OUTPUTS
DACDR, DACDL, SERI, US1, SCK, WS, C4, ER, DDO, FID, PDV, ADV, DV, CK728
VOL
VOH
Low Output Voltage (IOL = -4mA)
High Output Voltage (IOH = 4mA)
0.7 VDD
US0 (open drain)
VOL
Low Output Voltage (IOL = -4mA)
ILK
High Output Current (leakage)
CONSTANT CURRENT LED DRIVERS C1, C2, C3
Low Output Current (VOL = 0.4V)
IOL
0.4
V
±2
µA
- 10
mA
INPUTS
HA0, US2, RESET, DDI, SEL1, SEL0, TEST, NDI, CK11
VIL
Low Input Voltage
VIH
ILK
High Input Voltage
Input Leakage Current
0.8
V
V
±2
µA
0.4
V
V
0.8
V
0.6 VDD
BI-DIRECTIONAL
VOL
VOH
RSW, MUTE
Low Output Voltage (IOL = -4mA)
High OUtput Voltage (IOH = 100µA)
VOL
Low Input Voltage
SD
Low Output Voltage (IOL = -4mA)
VOH
VIL
VIH
High Output Voltage (IOH = 4mA)
Low Input Voltage
High Input Voltage
ILK
Input Leakage Current
VIL
0.7 VDD
0.4
V
0.8
V
V
V
±2
µA
1.5
VDD
100
2
V
V
kHz
µA
pF
0.7 VDD
0.6 VDD
I2C INTERFACE
fSCL
tr, tf
SCL
Low Input Voltage
High Input Voltage
SCL Clock Frequency
Input Rise and Fall Times
0
3
IIL
Input Leakage Current (VI = 5.5V)
10
CI
Input Capacitance
SDA
7
VIL
VIH
tr, tf
IIL
CI
VOL
tf
CI
Input Low Voltage
Input High Voltage
Input Rise / Fall Times
0
3
1.5
VDD
2
Input Leakage Current (VI = 5.5V with output off)
10
Input Capacitance
Low Output Voltage (IOL = 3mA)
Output Fall Time between 3.0V and 1.0V
Load Capacitance
7
0.5
200
400
0
µs
V
V
µs
µA
pF
V
ns
pF
3/12
8204B-04.TBL
VIL
VIH
TDA8204B
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
I2C BUS TIMING
4
4
µs
µs
ns
ns
tSU, dAT
tHD, dAT
tSU, STO
Data Set-up Time
Data Hold Time
Stop Set-up Time from Clock High
250
170
4
µs
tBUF
Start Set-up Time following a Stop
4
µs
tHD, STA
Start Hold Time
4
µs
tSU, STA
Start Set-up Time following Clock Low to High Transition
4
µs
8204B-05.TBL
SERIAL BUS (referred to VIH = 3V, VIL = 1.5V)
Low Period Clock
High Period Clock
tLOW
tHIGH
2
Figure 1 : I C Serial Bus Timing
SDA
t BUF
tF
t LOW
SCL
t HD, STA
tr
t HD, DAT
t HIGH
t SU, DAT
t SU, STA
V IH = 3V, VIL = 1.5V
t SU, STO
8204B-03.EPS
SDA
Figure 2 : I2S Bus Timing Diagram
CLOCK
f = 896kHz
WS
f = 32 kHz
SD OUT
LSB
word n - 1
right channel
SD IN
4/12
MSB
MSB
LSB
word n
left channel
14 bits
MSB
word n + 1
right channel
14 bits
LSB
MSB
8204B-04.EPS
I 2S
TDA8204B
FUNCTION DESCRIPTION
The TDA8204B is partitioned into 6 major parts
shown in the block diagram.
The NICAM Decoder performs data and sound
re co ve ry f ro m t h e si g na l s sp e ci f ie d in
EBU SPB 424. The expanded digital audio signals
(14-bit) are made available at the digital audio
interface (I2S) in a serial multiplex of left and right
channels. They are also processed by a 4 times
upsampling digital filter and noise shaper which
results in a high speed digital data stream at the
output pins DACDL/DACDR. This data stream can
be applied to the 1-bit D-A convertors contained in
the TDA8205.
The TDA8204B is I2C bus controlled and provides
control over the functions of the TDA8205 by
means of a serial inter-chip bus.
The 10-bit input audio samples are expanded to
14-bit using scale factor bits according to NICAM
decoding rules. Samples in error by the parity
check are replaced by interpolated one or repeated.
Mute is set according to an error counter when the
error rate exceeds error rate limit (ERL) and reset
when the error rate is below ERL/4.
Application control information (bit C1, C2, C3, C4)
is recovered by majority decision logic over 16
frames. the C1, C2, C3 , C4 bits can be read in SR0
register and are set on the C1, C2, C3, C4 pins
according to the state of bit 0 (BEA) of the CR2
register.
2 - Digital Filter and Noise Shaper
A digital filter performs 4X upsampling in two
stages. The main FIR 2x upsampler is followed by
a smaller 2x FIR upsampler. Digital upsampling
means a much simpler post-DAC reconstruction
filter can be used thus saving on external component count and cost.
A noise shaper converts the samples from the
digital filter into two high speed serial bitstreams
which can be applied to the DACs in the TDA8205.
1 - NICAM Decoder
1.1 - BLOCK DIAGRAM (see Figure 3)
1.2 - DESCRIPTION
NICAM frame alignment requires searching out a
frame alignment word (FAW) and a 16 frame sequence conveyed by C0 bit. Because of noise,
interferences, errors in the incoming NICAM Data,
aliases of the FAW, a robust scheme is implemented. It ensures the decoder will align, and stay
aligned, to signals beyond the limit of maximum
useable error rate. Thanks to a 511 bit PRBS synchronized by the recovered clock and a modulo 2
adder, original data are recovered. This data
stream can be processed externaly for de-encryption in Pay TV applications using descrambled data
Pins DDO, DDI.
To allow simultaneous reading and writing of
mono/stereo samples, de-interleaved data frames
are stored in a 3 page RAM.
3 - I2S Bus
A standard three-wire interface, conforming to the
I2S bus protocol, is provided, allowing connection
of an external DAC or DAT interface. Audio samples
contain 14-bit, so 16-bit DACs will pad the two LSBs
with 0. The word select clock operates at 32kHz
and the serial clock at 896kHz.
By setting SDI bit of CR2 to 1, the I2S interface can
receive the digital I2S sound. This prevents duplicating the dual D/A converter.
RSW
ER
MUTE
21 20 19 18 6
23
25
C4
C1
27
C3
DDI
28
C2
DDO
Figure 3 : NICAM Decoder Block Diagram
MAJORITY
LOGIC
DESCRAMBLER
COUNTER
RAM
EXPANDER
CONCEAL
AND MUTE
ADDRESS
FRAME
CONTROL
GENERATOR
TO FILTER
8204B-05.EPS
PDV 30
FID 29
ERROR
RECOVERY
3 PAGE
NDI 39
DV 33
SCALE FACTOR
ADV 31
5/12
TDA8204B
4 - Interchip Bus
A one-line serial bus provides interchip communications allowing control of all functions through the
single I2C bus interface.
5 - I2C Bus
An I2C bus interface provides access to control and
status registers within the two chips to allow control
of their functions and monitoring of status. A digital
filter is included to improve noise immunity.
5.1 - DATA FLAGS (see Figure 4)
These indicate the status of the descrambled data
on the DDO pin. They are inhibited if the decoder
is out of alignement.
- FID : Frame alignment word (scrambled)
- PDV : Parity Data Valid. CIB0 and CIB1 overwrite
the first 2 bits of FAW
- ADV : 11 additional data bits
- DV : Data valid (mode dependant)
5.2 - DECRYPTION (see Figure 5)
The PRBS generator (used for descrambling) is
normally preset to all ones at the start of each
frame. However, it is possible to preset it to any
value on each frame by means of a code word clock
(CWC) and serial code word data (CWD) interface
on pins SEL0 and SEL1.
CWD, which is clocked in on the negative going
edges of the CWC clock, can be sent anywhere
during the frame except when FID = 1. The CWC
is asynchronous with respect to the Nicam clock
and the CWD will be used on the following frame.
During the time FID = 1, the levels on the SEL0,
SEL1 pins are read for language selection. Code
words for descrambler presetting may be sent in
either an 8-bit or 9-bit formats. There are four
possibilities :
- if 7 or less clock cycles are counted on CW-clock
during a frame, the PRBS generator is preset to
all ones ;
- if 8 clock cycles are counted, 8 bits of CW-data
are clocked into the shift register, the first bit of the
previous transfer now moving to bit 9 position in
the shift register. The resulting value is used to
preset the PRBS generator on the next frame.
- if 9 clock cycles are counted, the CW-data (which
has been clocked into a 9-bit shift register) is used
to preset the PRBS generator on the next frame.
- if 10 or more clock cycles are counted, only the
first 9 bits of the CW-data are used and loaded
into the PRBS generator on the next frame.
Figure 4 : Data Flags
1 FRAME
NEXT FRAME
CK728
FA W
DDO
CB0 CB1
C0 C1 C2 C3 C4 AD0
AD10
NICAM DATA 704 BITS
24 CONTROL
704 DATA
FID
PDV
ADV
DV Stereo
DV Data
ODD FRAME
8204B-06.EPS
EVEN FRAME
DV Mono
Figure 5 : PRBS Presetter
FID
SEL1
(CWD)
6/12
8204B-07.EPS
SEL0
(CWC)
TDA8204B
5.3 - SOFTWARE SPECIFICATION
Software control of IC’s is given by programming
four registers, one read only status register (SR0)
and three read and write control registers (CR1,
CR2, CR3).
Transmit format : S = Start, A = Acknowledge
P = stop
REG SUB
ADDRESS
0 A
A DATA A
P
34
36 35
P
Note : All registers are read sequentially; device status and the
contents of all registers may be read. The sequence may be
terminated by not acknowledging (NOACK) the slave.
32 31
EAIL
CR1 A
DATA
EAIR
A
AMOL
SR0
DATA
1 A
SAIL
CHIP
ADDRESS
AMOR
Figure 6
Receive format :
S
Output select (see tables)
Input select (see tables)
Auxiliary output gain, 0 = 0dB, 1 = 6dB
Auxiliary output mute, 0 = no-mute,
1 = muted
FRE : Free run clock VCXO for set up,
0 = normal, 1 = free run
To set crystal series capacitor
Switches and Matrix Description
SAIR
CHIP
ADDRESS
:
:
:
:
MAI
S
Qn
In
G0
AUM
38 37
27 AOL
28 AOR
LFIL1
Chip address
0
1
1
0
1
HAO
R/W
LSB
RFIL1
INTL
INTR
HAO : Hardware address selection pin
Reserve sound switch
Register addresses
Reg.
Name
SR0
CR1
CR2
CR3
Sub Adress
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
0
0
1
1
0
1
0
1
NICAM status
Matrix and mutes
NICAM control
Switches
Register contents
SR0 : NICAM status (read only)
US2
US2
MSB
L/S :
LA2 :
MUT :
C4 :
C3 :
C2 :
C1 :
US2 :
C1
0
C2
0
C3
0
C4
1
MUT
1
LA2
1
L/S
1
LSB
If FN1 bit of CR2 is 0, LS bit is loss of
frame alignment status
LS =1, FAW is lost
LS = 0 FAW is identified
• If FN1 bit of CR2 is 1, LS bit is selected
system status
LS = 1, B/G standard
LS = 0, I standard
Loss of sub-frame alignment
(1 = loss of alignment)
NICAM mute (1 = DAC outputs muted)
Reserve sound flag (1 = FM backup)
Application control bit 3
Application control bit 2
Application control bit 1
User bit 2 (input)
US2 bit indicates the state of US2 input Pin
•
CR1 : Matrix and mutes (read and write register)
Q1
0
MSB
Q0
0
I2
0
I1
0
I0
0
G0
0
8204B-08.EPS
1
MSB
AUM
0
FRE
0
LSB
Audio matrix
Output selection
Q1
0
0
Q0
0
1
Output
AOL
AOR
Mute and gain selection
Q0
0
0
1
1
I2
0
1
0
1
Mute
OFF*
ON*
-
Gain
0dB**
+6dB**
* Mute is activated by left channel selection
** Gain is activated by right channel selection
Input selection
I1
0
0
1
1
I0
0
1
0
1
Input
INTL
INTR
EAIL
EAIR
Example of programming
First
: 00100X X X
step
INTL connected to AOL, mute ON on
AOL/AOR
Sec: 01011X X X
ond
EAIR connected to AOR, gain 0dB on
step
AOL/AOR
Thrird : 0 0 0 0 0 X X X
step
INTL connected to AOL, mute OFF on
AOL/AOR
The power up default configuration is 0dB and
unmute for both channels AOL/R, and INTL connected to AOL, and INTR connected to AOR.
7/12
TDA8204B
CR2 : NICAM control (read and write register)
SDI
0
MSB
SDI
ECT
MAE
FN1
UMT
LA1
LA0
BEA
ECT
0
MAE
0
FN1
0
UMT
0
LA1
0
LA0
0
BEA
1
LSB
: I2S direction
0 = Output, 1 = Input
: Bit error rate counting time
0 = 128ms, 1 = 64ms
: Max allowed errors
0 = 511, 1 = 255
: Set function of bit 0 in SR0, 0 = loss of
alignment (status), 1 = system status (I or
B/G)
: Un-mute NICAM, 1 = un-mute, 0 = mute
: Language select 1 (LA1 ⊕ SEL1)
: Language select 0 (LA0 ⊕ SEL0)
: Set C1-C3 function
ECT
0
0
1
1
MAE
0
1
0
1
BER MUTE
8.9 x 10-3 (1 in 112)
4.4 x 10-3 (1 in 225)
1.8 x 10-2 (1 in 56)
8.9 x 10-3 (1 in 112)
C1 (21)
C2 (20)
C3 (19)
1
Single mono mode
Dual mono mode
Stereo mode
* Application control bit of NICAM signal
Note : C4 pin remains unchanged. The function of C1-C4 in SR0
remains unchanged.
CR3 : Switches (read and write register)
US1
0
MSB
US1
US0
AUT
IBG
FSn
SYN
US0
0
:
:
:
:
:
:
FS1
0
0
1
1
AUT
1
IBG
0
FS1
0
FS0
0
X
0
Selection
Auto NICAM
FM-Mono
FM-Stereo
NICAM
NICAM STAND-ALONE APPLICATION
The NICAM kit has been designed to be monitored
by the I2C bus; nevertheless stand-alone working
capability is offered to the designer for low cost
8/12
US2
C1
C2
C3
C4
MUT
C1
0
:
:
:
:
:
:
C2
0
C3
0
C4
1
MUT
1
LA2
1
L/S
1
LSB
Not used in stand-alone
Application control bit status for
NICAM signal
Reserve Sound Flag
DAC outputs muted (demuted as soon
as NICAM appears)
: the subframe alignment is been lost
: FAW status (FN1 of CR2 = 0)
Q1
0
MSB
Q1
Q0
I2
I1
G0
AUM
FRE
Q0
0
:
:
:
:
:
:
:
I2
0
I1
0
I0
0
G0
0
AUM
0
FRE
0
LSB
NICAM sound is sent on all matrix
outputs and on AMOx pins
Gain = 0dB on AMOx
AMOx pins un-muted
VCXO in normal mode
CR2 (R/W)
SYN
1
LSB
User bit 1 (output)
User bit 0 (output)
Automatic selection, 1 = enable
Select system I or B/G, 1 = B/G
Force switch (see table)
1 = synthesiser, 0 = dual VCXO
(carrier loop)
FS0
0
1
0
1
US2
US2
MSB
CR1 (R/W)
BEA
0
C1*
C2*
C3*
1 - Power-ON Configuration
SR0 (status)
LA2
L/S
Un-mute at BER/4.
TDA8204B
Output (Pin)
applications.
In order to know the status of the kit in stand-alone
mode, consider the contents of the four I2C registers at power-ON (4 registers : SR0 - CR1 - CR2 CR3). Hardware configurable pins will be described
later.
SDA
0
MSB
SDA
ECT &
MAE
FN1
ECT
0
MAE
0
FN1
0
UMT
0
LA1
0
LA0
0
BEA
1
LSB
: Normal mode
: BER = 1/112
: Bit L/S of SR0 set to alignment loss
status
UMT
: TDA8204B mute pin 25 to 0
LA1
: Result depending of SEL1
LA0
: Result depending of SEL0
BEA
: Beacon decoding mode but all diodes
are OFF until a NICAM signal has been
found
CR3 (R/W)
US1
0
MSB
US1
US0
AUT
US0
0
AUT
1
IBG
0
FS1
0
FS0
0
: Not used in stand-by mode
: Not used in stand-by mode
: Automatic standard
X
0
SYN
1
LSB
TDA8204B
IBG
FSn
FN2
SYN
: Standard I (don’t care)
: Set to Auto NICAM (if NICAM fails, FM
mono is selected)
: Not used
: Synthesizer selected
2 - Hardware Configurable Pins
2.1 - TDA8204B - PIN 6 - (RSW)
- as an output :
status of the RSW switch
- 0 = FM mono
- 1 = NICAM
- as an input :
- 0 = FM mono (forced)
2.2 - TDA8204B - PINS 34/35 - (SEL0/SEL1)
(see Figure 7)
- to select the language in case of bilingual operation
- selected value is related to LA0 and LA1
As the I2C bus is not used LA0 and LA1 = 0
(power-ON condition) / SEL0 = Q0, SEL1 = Q1
The 4 choices are summarized in the table below.
SEL0
0
0
1
1
SEL1
0
1
0
1
DACDL
M1
M1
M2
M2
DACDR
M2
M1
M2
M1
M1 = Mono 1
M2 = Mono 2
VII - 2.3. TDA8204B - PIN 25 - (MUTE)
- as an output :
status of the DAC
- 0 = unmuted
- 1 = muted
- as an input :
- 0 = unmute DAC (forced)
Figure 7
LA1
Q1 = SEL1
LA1
Q0 = SEL0
LA0
Q1
SEL1 34
Q0
SEL0 35
S
W
I
T
C
H
8204B-09.EPS
LA0
9/12
10nF
C1
R3
1.2kΩ
R2 470Ω
R4
470Ω
T1
6.0MHz
Q1
R9 8.2MΩ
TRAP
8204B-10.EPS
NICAM
SYS. I
IN
R1
8.2kΩ
C7
100nF
R10 39kΩ
R5
100Ω
C2 10nF
C3 10nF
R6
33Ω
BFP
1
42
C22
10µF
F1
6.552MHz
C7 680pF
R8
150Ω
C8
220nF
C10 6.8nF
C11 150pF
X1
2
3
4
C5
220pF
R7
470Ω
C4 1nF
6
C24 1µF
C25 1µF
MON1
MON2
7
8
L1
10µH
TDA8205
V
DD
Q2
C23
10µF
L2 10µH
C14
6.8nF
R12
5.6kΩ
R13
43kΩ
10 11 12 13 14 15
C13
100nF
9
IC1
36 35 34 33 32 31 30 29 28
C6
220pF
VCC
5
41 40 39 38 37
R18 10kW
11.648MHz
C9 120pF
C12 18pF*
C19
100nF
R11 5.6kΩ
* C12 value depends on X1
C21
10µF
C26
220µF
R14
43kΩ
C18
100nF
R15
5.6kΩ
C16
10µF
R20 22kΩ
C15
6.8nF
21
22
R17 330Ω
C17 100nF
16 17 18 19 20
27 26 25 24 23
C20
10µF
R19 270Ω
R16
1MΩ
1
2
3
5
LK2
6
7
8
9
C28
100nF
10 11 12 13 14
TDA8204B
AUDIO
OUTPUT
15 16 17 18 19
Unmute
DAC
(forced)
stereo
dual
mono
single
mono
20 21
23 22
ERROR
MONITOR
28 27 26 25 24
Q1, Q2 : BC109 or BC550C
F1 : TOKO TH316BQM2110QDAF (5VFP)
T1 : Matsushita EFCS6R0MWS
X1 : 11.648MHz Crystal NDK
IC2
37 36 35 34 33 32 31 30 29
FM mono
(forced)
4
42 41 40 39 38
mute
LED1
LK1
Language
Selection
L
R
LED2
LED3
10/12
LED4
FM MONO IN
TDA8204B
APPLICATION DIAGRAMS
Figure 8 : Stand Alone Application (I standard)
T1
R11
470Ω
5.5MHz
R14
1.2kΩ
R13 470Ω
R12
8.2kΩ
R8
1.2kΩ
R7 470Ω
6.0MHz
T2
TRAP
8204B-11.EPS
10nF
C34
10nF
C31
Q2
Q1
C25
220nF
R5
470Ω
TRAP
NICAM
SYS. I
IN
NICAM
SYS. BG
IN
R6
8.2kΩ
R27 8.2MΩ
VCC
R1 39kΩ
R15
100Ω
C36 10nF
C35 10nF
R9
100Ω
C33 10nF
C32 10nF
R16
33Ω
BFP
F2
6.552MHz
R10
33Ω
BFP
1
3
C30
220pF
R18
470Ω
C38 1nF
R17
470Ω
C37 1nF
R31 10kΩ
2
4
5
7
MON1
MON2
C29
220pF
6
8
TDA8205
Q3
VDD
C44
220µF
C40
6.8nF
R19
5.6kΩ
+5V
+12V
R20
43k Ω
C5
10µF
C1
10µF
R21
43kΩ
C20
10µF
C42 100nF
C6
100nF
C2
100nF
C7
100nF
C3
100nF
R33 22kΩ
C41
6.8nF
R22
5.6k Ω
C43
100nF
10 11 12 13 14 15 16 17 18 19 20 21
C39
100nF
9
IC1
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
11.648MHz
X1
F1
5.85MHz
C45 680pF
R2
150Ω
C26
120pF
C21 6.8nF
C22 150pF
C23 18pF *
C17
1µF
C18
10µF
C16
1µF
C19
10µF
VCC
C8
100nF
VDD
VDD
SEL1
SEL0
ERROR
MONITOR
1
2
3
4
5
6
7
9
10 11 12 13 14 15 16 17 18 19 20 21
TDA8204B
USER
BITS
I 2 S BUS
Q1, Q2, Q3 : BC109 or BC550C
F1 : TOKO TH316 BQM 2080 QDAF (5VFP)
F2 : TOKO TH316 BQM 2110 QDAF (5VFP)
T1 : Matsushita EFCS5R5MWS
T2 : Matsushita EFCS6R0MWS
X1 / 11.648MHz Crys tal NDK
8
IC2
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
R25
330Ω
LED1
mute
R24
1MΩ
VDD
C4
100nF
R32 270Ω
C15
10µF
C14
10µF
RSW
C13
100nF
CK728
US1
C12
100nF
TEST
US0
C11
100nF
DV
GND
C10
100nF
ADV
SD
C9
100nF
PDV
SCK
AUDIO
OUTPUT
Right
Left
MUTE
C4
AUDIO
MUTABLE OUT
Left
Right
R23 5.6kΩ
FID
WS
FM
MONO
IN
CONTROL
BITS
C3
STEREO
AUDIO IN
Right
Left
C2
EXTERNAL
AUDIO IN
Left
Right
C1
* C23 value depends on X1
LED3
dual
mono
LED2
single
mono
SCL
SDA
LED4
stereo
V DD
I 2 C BUS
TDA8204B
Figure 9 : I2C Bus Controlled Application (I and B/G standard)
11/12
TDA8204B
PACKAGE MECHANICAL DATA
42 PINS - PLASTIC SHRINK
e4
A
I
b1
L
a1
F
b2
e
b
E
Stand-off
e
A
a1
b
b1
b2
b3
D
E
e
e3
e4
F
i
L
22
1
21
Min.
3.30
Millimeters
Typ.
0.51
0.35
0.20
0.75
0.75
15.57
Max.
Min.
0.130
0.020
0.014
0.008
0.030
0.030
0.59
0.36
1.42
39.12
17.35
1.778
35.56
15.24
Inches
Typ.
0.613
Max.
0.023
0.014
0.056
1.540
0.683
0.070
1.400
0.600
14.48
5.08
2.54
0.570
0.200
0.100
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and
replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
SDIP42.TBL
Dimensions
42
PMSDIP42.EPS
D