ASAHI KASEI [AK93C45C/55C/65C] AK93C45C/55C/65C 1K/2K/4Kbit Serial CMOS EEPROM Features ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.5V to 5.5V(READ) VCC = 1.6V to 5.5V(WRITE/WRAL/PAGE WRITE) AK93C45C ・・1024 bits, 64 x 16 organization AK93C55C ・・2048 bits, 128 x 16 organization AK93C65C ・・4096 bits, 256 x 16 organization SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors -1.0MHz(1.5V≤VCC<2.5V), 4.0MHz(2.5V≤VCC≤5.5V) LOW POWER CONSUMPTION - 0.8µA Max. Standby High Reliability - Endurance : 1000K E/W cycles / Address - Data Retention : 10 years Automatic address increment (READ) Automatic write cycle time-out with auto-ERASE Busy/Ready status signal Software and Hardware controlled write protection IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (TMSOP, SON, USON) DO DATA REGISTER DI INSTRUCTION REGISTER INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION 16 ADD. BUFFERS R/W AMPS AND AUTO ERASE DECODER 16 EEPROM 93C45C=1024bit 93C55C=2048bit 93C65C=4096bit CS VPP SW SK PE VREF VPP GENERATOR Block Diagram DAM06E-01 2005/10 - 1 - ASAHI KASEI [AK93C45C/55C/65C] General Description The AK93C45C/55C/65C is a 1024/2048/4096-bit serial CMOS EEPROM divided into 64/128/256 registers of 16 bits each. The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS and WRAL. Those instructions control the AK93C45C/55C/65C. The AK93C45C/55C/65C can operate full function under wide operating voltage range. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C45C/55C/65C, consisting of chip select (CS), serial clock (SK), data-in (DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C45C/55C/65C takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C45C/55C/65C takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output. x Software controlled write protection When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction is disabled. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE, PAGE WRITE, WRAL, EWEN and EWDS instructions. x Busy/Ready status signal After a WRITE, PAGE WRITE, WRAL instruction, the DO output serves as a Busy/Ready status indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. DAM06E-01 2005/10 - 2 - ASAHI KASEI [AK93C45C/55C/65C] Type of Products Model AK93C45CT AK93C45CL AK93C45CU AK93C55CT AK93C55CL AK93C55CU AK93C65CT AK93C65CL AK93C65CU Memory size 1K bits 2K bits 4K bits Temp. Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C VCC 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V 1.5V to 5.5V Package 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON 8pin Plastic TMSOP 8pin Plastic SON 8pin Plastic USON Pin Arrangement AK93C45CT/55CT/65CT CS SK DI DO 1 2 3 4 8 7 6 5 AK93C45CL/55CL/65CL VCC NC PE GND VCC NC PE GND 1 2 3 4 8pin TMSOP 8 7 6 5 CS SK DI DO 8pin SON AK93C45CU/55CU/65CU VCC NC PE GND 1 2 3 4 8 7 6 5 CS SK DI DO 8pin USON Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output PE Program Enable VCC Power Supply GND Ground NC Not Connected *1 (note) The PE is internally pulled up to VCC ( R = typ.2.5MΩ, VCC=5V ). *1: Please Open NC pin. DAM06E-01 2005/10 - 3 - ASAHI KASEI [AK93C45C/55C/65C] Functional Description The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS and WRAL. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory Address location. The CS pin must be brought low for a minimum of ‘tCS’ between each instruction when the instruction is continuously executed. Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00 Instruction Address Data Comments A5-A0 A5-A0 A5-A0 11XXXX 00XXXX 010000 D15-D0 D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Page Write register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table1. Instruction Set for the AK93C45C Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00 Instruction Address Data Comments XA6-A0 XA6-A0 XA6-A0 11XXXXXX 00XXXXXX 010000000 D15-D0 D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Page Write register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table2. Instruction Set for the AK93C55C Start Op Bit Code READ 1 10 WRITE 1 01 PAGE WRITE 1 11 EWEN 1 00 EWDS 1 00 WRAL 1 00 Instruction Address Data Comments A7-A0 A7-A0 A7-A0 11XXXXXX 00XXXXXX 010000000 D15-D0 D15-D0 D15-D0 Reads data stored in memory, at specified address. Writes register. Page Write register. Write enable must precede all programming modes. Disables all programming instructions. D15-D0 Writes all registers. X: Don't care table3. Instruction Set for the AK93C65C (Note) x The AK93C45C/55C/65C perceives the start bit in the logic"1" and also "01". DAM06E-01 2005/10 - 4 - ASAHI KASEI [AK93C45C/55C/65C] WRITE The write instruction is followed by 16 bits of data to be written into the specified address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. PE CS SK DI 0 0 1 1 2 0 Start Bit 3 1 4 A5 5 A4 8 A1 9 A0 10 D15 11 D14 23 D2 24 D1 25 tCS D0 Op code Busy Hi-Z DO Ready AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. tE/W WRITE (AK93C45C) PE CS SK DI 0 0 1 1 2 0 Start Bit 3 4 X 1 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 tCS D0 Op code Busy Hi-Z DO Ready AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. tE/W X: Don't care WRITE (AK93C55C) PE CS SK DI 0 0 1 1 Start Bit DO 2 0 3 1 4 A7 5 A6 10 A1 11 A0 12 D15 13 D14 25 D2 26 D1 27 tCS D0 Op code Busy Hi-Z Ready AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. tE/W WRITE (AK93C65C) DAM06E-01 2005/10 - 5 - ASAHI KASEI [AK93C45C/55C/65C] PAGE WRITE AK93C45C/55C/65C has Page Write mode, which can write the data within 4 words with one programming cycle. The input data sent to the shift register within 4 words. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. After the receipt of each word, the two lower order address pointer bits internally incremented by one. The higher order six bits of the word address remains constant. When the highest address is reached ”XXXX XX11”, the address counter rolls over to address ”XXXX XX00” allowing the page write cycle to be continued indefinitely. If AK93C45C/55C/65C is transmitted more than 4 words, the address counter will ”roll over” and the previously written data will be overwritten. When AK93C45C/55C/65C is transmitted 6 words, fifth word will be overwritten to first word, and sixth word will be overwritten to second word. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. PE CS 0 SK 1 2 3 4 5 6 7 8 A5 A4 A3 A2 A1 9 10 11 12 23 24 25 Data(n) DI 0 1 1 1 A0 D15 D14 D13 D2 D1 D0 Hi-Z DO AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. PE CS SK 26 27 39 40 tCS 41 Data(n+1) DI DO D15 D14 D2 Data(n+3) D1 D0 D15 D0 D15 D14 D2 Hi-Z D1 D0 Busy tE/W Ready PAGE WRITE (AK93C45C) DAM06E-01 2005/10 - 6 - ASAHI KASEI [AK93C45C/55C/65C] PE CS 0 SK 1 2 3 4 5 6 7 8 A6 A5 A4 A3 9 10 11 12 25 26 27 Data(n) DI 0 1 1 1 X A2 A1 A0 D15 D2 D1 D0 Hi-Z DO AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. PE CS SK 28 29 41 42 tCS 43 Data(n+1) DI D15 D14 D2 Data(n+3) D1 D0 D15 D0 D15 D14 D2 D1 D0 Hi-Z DO Busy Ready tE/W X: Don't care PAGE WRITE (AK93C55C) PE CS 0 SK 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 9 10 11 12 25 26 27 Data(n) DI 0 1 1 1 A2 A1 A0 D15 D2 D1 D0 Hi-Z DO AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. PE CS SK 28 29 41 42 tCS 43 Data(n+1) DI DO D15 D14 D2 Data(n+3) D1 D0 D15 D0 D15 D14 D2 Hi-Z D1 D0 Busy tE/W Ready PAGE WRITE (AK93C65C) DAM06E-01 2005/10 - 7 - ASAHI KASEI [AK93C45C/55C/65C] WRAL The write instruction is followed by 16 bits of data to be written into all address. After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. PE CS SK DI 0 0 1 1 2 0 3 0 4 0 5 6 0 1 7 0 8 0 10 9 0 D15 11 D14 12 D13 13 D12 25 tCS D0 Start Bit Busy Hi-Z DO R eady AK93C45C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL. tE/W WRAL (AK93C45C) PE CS SK DI 0 0 1 1 2 0 3 0 4 0 5 1 6 0 7 0 8 0 10 9 0 0 11 0 12 D15 13 D14 27 tCS D0 Start Bit Busy Hi-Z DO R eady AK93C55C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL. tE/W WRAL (AK93C55C) PE CS SK DI 0 0 1 1 2 0 3 0 4 0 5 1 6 0 7 0 8 0 10 9 0 0 11 0 12 D15 13 D14 27 tCS D0 Start Bit Busy Hi-Z DO R eady AK93C65C output a logic "1" (R eady status), if previous instruction is W RITE, PAGE W RITE, W RAL. tE/W WRAL (AK93C65C) DAM06E-01 2005/10 - 8 - ASAHI KASEI [AK93C45C/55C/65C] READ The read instruction is the only instruction which outputs serial data on the DO pin. Following the Start bit, first Op code and address are decoded, then the data from the selected memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from the selected memory location. The output data changes are synchronized with the rising edges of the serial clock (SK). The data in the next address can be read sequentially by continuing to provide clock. The address automatically cycles to the next higher address after the 16bit data shifted out. When the highest address is reached, the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. CS SK DI 0 0 1 1 2 1 Start bit 3 4 A5 0 5 A4 8 A1 9 10 11 25 26 40 41 A0 Op code Hi-Z DO AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. D15 D14 D0 0 Dummy address[A5–A0] Bit D15 D1 D0 address[A5–A0]+1 READ (AK93C45C) CS SK DI 0 0 1 1 2 1 Start bit 3 4 X 0 5 A6 10 A1 11 12 13 27 28 42 43 A0 Op code Hi-Z DO AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. D15 D14 D0 0 Dummy address[A6–A0] Bit D15 D1 D0 address[A6–A0]+1 X: Don't care READ (AK93C55C) CS SK DI 0 0 1 1 Start bit 2 1 3 0 4 A7 5 A6 10 A1 12 13 27 28 42 43 A0 Op code Hi-Z DO 11 AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. D15 D14 D0 0 Dummy address[A7–A0] Bit D15 D1 D0 address[A7–A0]+1 READ (AK93C65C) DAM06E-01 2005/10 - 9 - ASAHI KASEI [AK93C45C/55C/65C] EWEN / EWDS When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction is disable. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or VCC is removed from the part. Execution of a read instruction is independent of both EWEN and EWDS instructions. PE CS SK 0 DI 0 1 1 2 0 3 4 5 0 6 X 7 X 8 X 9 X EWEN=11 EWDS=00 Start bit Hi-Z DO AK93C45C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL. X: Don't care EWEN / EWDS (AK93C45C) PE CS SK DI 0 0 1 1 2 0 3 4 5 6 X 0 7 X 8 X 9 10 X X 11 X EWEN=11 EWDS=00 Start bit Hi-Z DO AK93C55C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL. X: Don't care EWEN / EWDS (AK93C55C) PE CS SK DI 0 0 1 1 Start bit DO 2 0 3 4 5 6 X 0 7 X 8 X 9 X 10 X 11 X EWEN=11 EWDS=00 Hi-Z AK93C65C output a logic "1" (Ready status), if previous instruction is WRITE PAGE WRITE, WRAL. X: Don't care EWEN / EWDS (AK93C65C) DAM06E-01 2005/10 - 10 - ASAHI KASEI [AK93C45C/55C/65C] Absolute Maximum Ratings Parameter Power Supply All Input Voltages with Respect to Ground Ambient storage temperature Symbol VCC VIO Min -0.6 -0.6 Max +6.5 VCC+0.6 Unit V V Tst -65 +150 °C Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Condition Parameter Power Supply 1(Except READ) Power Supply 2(READ) Ambient Operating Temperature Symbol VCC1 VCC2 Ta DAM06E-01 Min 1.6 1.5 -40 Max 5.5 5.5 +85 Unit V V °C 2005/10 - 11 - ASAHI KASEI [AK93C45C/55C/65C] Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS ( 1.5V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Parameter Symbol ICC1 Condition VCC=5.5V, tSKP=250ns, *1 Max. 2.5 Unit mA ICC2 VCC=1.8V, tSKP=1.0µs, *1 1.5 mA Current Dissipation (WRAL) ICC3 VCC=5.5V, tSKP=250ns, *1 2.5 mA ICC4 VCC=1.8V, tSKP=1.0µs, *1 1.5 mA Current Dissipation (READ) ICC5 VCC=5.5V, tSKP=250ns, *1 1.5 mA ICC6 VCC=1.5V, tSKP=1.0µs, *1 0.1 mA Current Dissipation (Standby) ICCSB VCC=5.5V 0.8 µA Input High Voltage VIH1 VCC=5.0V±10% 2.0 VCC + 0.5 V VIH2 2.5V ≤ VCC ≤ 5.5V 0.8 x VCC VCC + 0.5 V VIH3 1.5V ≤ VCC < 2.5V 0.8 x VCC VCC + 0.5 V VIL1 VCC=5.0V±10% -0.1 0.8 V VIL2 1.8V ≤ VCC ≤ 5.5V -0.1 0.15 x VCC V VIL3 1.5V ≤ VCC < 1.8V -0.1 0.1 x VCC V VOH1 VCC=5.0V±10% IOH=-0.4mA VOH2 Current Dissipation (WRITE) Input Low Voltage Min. *2 2.2 V 2.5V ≤ VCC ≤ 5.5V IOH=-0.1mA 0.8 x VCC V VOH3 1.5V ≤ VCC < 2.5V IOH=-0.1mA 0.8 x VCC V VOL1 VCC=5.0V±10% IOL=1.5mA 0.4 V VOL2 2.5V ≤ VCC ≤ 5.5V IOL=1.0mA 0.4 V VOL3 1.5V ≤ VCC < 2.5V IOL=0.1mA 0.4 V Input Leakage ILI VCC=5.5V, VIN=5.5V ±1.0 µA Output Leakage ILO VCC=5.5V, VOUT=5.5V, CS=GND ±1.0 µA Output High Voltage Output Low Voltage *3 *1 : VIN=VIH/VIL, DO=Open *2 : VIN=VCC/GND, CS=GND, DO=Open, PE=VCC/Open *3 : CS, SK, DI pin DAM06E-01 2005/10 - 12 - ASAHI KASEI [AK93C45C/55C/65C] (2) A.C. ELECTRICAL CHARACTERISTICS ( 1.5V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified ) Parameter SK Cycle Time SK Pulse Width CS Setup Time CS Hold Time Data Hold Time *4 Selftimed Programming Time Min CS Low Time SK HOLD Time CS to Status Valid CS to Output High-Z Endurance Condition 2.5V ≤ VCC ≤ 5.5V Min. 250 tSKP2 1.5V ≤ VCC < 2.5V 1.0 µs tSKW1 2.5V ≤ VCC ≤ 5.5V 100 ns tSKW2 1.5V ≤ VCC < 2.5V 400 ns tCSS1 2.5V ≤ VCC ≤ 5.5V 80 ns tCSS2 1.5V ≤ VCC < 2.5V 200 ns 0 ns tCSH Data Setup Time Output delay Symbol tSKP1 *5 Max. Unit ns tDIS1 2.5V ≤ VCC ≤ 5.5V 50 ns tDIS2 1.5V ≤ VCC < 2.5V 100 ns tDIH1 2.5V ≤ VCC ≤ 5.5V 50 ns tDIH2 1.5V ≤ VCC < 2.5V 100 ns tPD1 2.5V ≤ VCC ≤ 5.5V 60 ns tPD2 1.5V ≤ VCC < 2.5V 300 ns tE/W 1.6V ≤ VCC ≤ 5.5V 5 ms tCS1 2.5V ≤ VCC ≤ 5.5V 60 ns tCS2 1.5V ≤ VCC < 2.5V 200 ns tCCH1 2.5V ≤ VCC ≤ 5.5V 60 ns tCCH2 1.5V ≤ VCC < 2.5V 200 ns tSV1 2.5V ≤ VCC ≤ 5.5V 125 ns tSV2 1.6V ≤ VCC < 2.5V 300 ns tOZ1 2.5V ≤ VCC ≤ 5.5V 75 ns tOZ2 1.5V ≤ VCC < 2.5V 100 ns 5.5V, 25°C, PAGE WRITE 1,000,000 E/W cycles/ Address *4 : CL=100pF *5 : This parameter is not tested to all samples. DAM06E-01 2005/10 - 13 - ASAHI KASEI [AK93C45C/55C/65C] Synchronous Data timing CS tCSS tSKW tSKW tSKP SK tDIS DI 0 tDIH 1 tSV Hi-Z DO AK93C45C/55C/65C output a logical "1" (Ready status), if previous instruction is WRITE, PAGE WRITE, WRAL. The Start of Instruction CS tCSH SK DI tPD DO D3 tPD D2 tPD D1 tOZ D0 Hi-Z The End of Instruction DAM06E-01 2005/10 - 14 - ASAHI KASEI [AK93C45C/55C/65C] tCS CS tCSH tCCH SK tDIS DI tDIH D1 D0 tSV DO Hi-Z Busy Ready tE/W Busy/Ready Signal Output DAM06E-01 2005/10 - 15 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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