ASAHI KASEI [AKD4633-A] AKD4633-A AK4633 Evaluation board Rev.3 GENERAL DESCRIPTION AKD4633-A is an evaluation board for the AK4633VN, 16bit mono CODEC with MIC/SPK amplifier. The AKD4633-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). AKD4633-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4633-A --- Evaluation board for AK4633VN (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • BNC connector for an external clock input • 10pin Header for serial control mode 5V AVDD DVDD SVDD 3.3V Regulator GND MIC-Jack Control Data MIC 10pin Header BEEP/MIN/MOUT AOUT DSP AK4633VN 10pin Header SPK-Jack AK4114 Opt In Opt Out Clock Gen Figure 1. AKD4633-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM079406> 2007/04 -1- ASAHI KASEI [AKD4633-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD, SVDD, and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, and VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default> [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red ) (orange) (orange) (blue) (orenge) (black) (black) (black) = 5V = open = open = open = open = 0V = 0V = 0V : 3.3V is supplied to AVDD of AK4633VN from regulator. : 3.3V is supplied to DVDD of AK4633VN from regulator. : 3.3V is supplied to SVDD of AK4633VN from regulator. : 3.3V is supplied to logic block from regulator. : for analog ground : for analog ground : for logic ground 1-2) When AVDD, DVDD, SVDD, and VCC are not supplied from the regulator. (AVDD, DVDD, SVDD, and VCC jack should be junction.) See “Other jumper pins set up (page 10)”. [REG] [AVDD] [DVDD] [SVDD] [VCC] [AVSS] [AGND] [DGND] (red) (orange) (orange) (blue) (orenge) (black) (black) (black) = “REG” jack should be open. = 2.6 ∼ 3.6V : for AVDD of AK4633VN (typ. 3.3V) = 2.6 ∼ 3.6V : for DVDD of AK4633VN (typ. 3.3V) = 2.6 ∼ 5.25V : for SVDD of AK4633VN (typ. 3.3V, 5.0V) = 2.6 ∼ 3.6V : for logic (typ. 3.3V) = 0V : for analog ground = 0V : for analog ground = 0V : for logic ground Each supply line should be distributed from the power supply unit. AVDD and DVDD must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4633VN and AK4114 should be reset once bringing SW1, 2 “L” upon power-up. Evaluation mode In case of AK4633VN evaluation using AK4114, it is necessary to correspond to audio interface format for AK4633VN and AK4114. About AK4633VN’s audio interface format, refer to datasheet of AK4633VN. About AK4114’s audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) (4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode (5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode <KM079406> 2007/04 -2- ASAHI KASEI [AKD4633-A] (1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode a) Set up jumper pins of MCKI clock X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X’tal of 12.288MHz (Default) is set on the AKD4633VN. Set “No.8 of SW3” to “H”. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock generator. JP6 JP17 XTE MCKI JP18 MKFS JP21 MCLK_SEL XTL DIR EXT 256fs 512fs 1024fs MCKO b) Set up jumper pins of BICK clock Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4633VN. There is no necessity for set up JP19. JP20 BICK INV JP29 BICK_INV JP27 BICK DIR ADC THR INV THR JP19 BICK_SEL 64fs 32fs 16fs EXT c) Set up jumper pins of FCK clock JP28 FCK JP22 FCK_SEL DIR ADC 2fs 1fs EXT d) Set up jumper pins of DATA When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following. JP30 JP26 4631_SDTI SDTI DIR ADC DAC/LOOP ADC <KM079406> 2007/04 -3- ASAHI KASEI [AKD4633-A] (2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) a) Set up jumper pins of MCKI clock X’tal of 12.288MHz (Default) is set on the AKD4633-A. In this case, the AK4633VN corresponds to PLL reference clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4633VN is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit” in the AK4633VN should be set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the output impedance of the clock generator. JP17 XTE JP6 MCKI JP18 MKFS JP21 MCLK_SEL XTL DIR EXT 256fs 512fs 1024fs MCKO b) Set up jumper pins of BICK clock JP20 BICK INV JP27 BICK DIR ADC THR JP29 BICK_INV INV THR JP19 BICK_SEL 64fs 32fs 16fs EXT c) Set up jumper pins of FCK clock JP22 FCK_SEL JP28 FCK DIR ADC 2fs 1fs EXT d) Set up jumper pins of DATA When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following. JP30 JP26 4631_SDTI SDTI DIR ADC DAC/LOOP ADC <KM079406> 2007/04 -4- ASAHI KASEI [AKD4633-A] (3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK pin) a) Set up jumper pins of BICK clock When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the output impedance of the clock generator. JP17 XTE JP20 BICK JP21 MCLK_SEL XTL DIR EXT INV THR JP29 BICK_INV JP27 BICK DIR ADC INV THR In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”, “512fs”, “1024fs” from left. JP18 MKFS JP18 MKFS JP18 MKFS 256fs 512fs 1024fs MCKO 256fs 512fs 1024fs MCKO 256fs 512fs 1024fs MCKO And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left. JP19 BICK_SEL JP19 BICK_SEL JP19 BICK_SEL 64fs 32fs 16fs EXT 64fs 32fs 16fs EXT 64fs 32fs 16fs EXT <KM079406> 2007/04 -5- ASAHI KASEI [AKD4633-A] b) Set up jumper pins of FCK clock When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator. JP22 FCK_SEL JP28 FCK DIR ADC 2fs 1fs EXT c) Set up jumper pins of DATA When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following. JP30 JP26 4633_SDTI SDTI DIR ADC <KM079406> DAC/LOOP ADC 2007/04 -6- ASAHI KASEI [AKD4633-A] (4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock JP6 MCKI JP21 MCLK_SEL JP18 MKFS XTL DIR EXT 256fs 512fs 1024fs JP17 XTE b) Set up jumper pins of BICK clock JP20 BICK INV THR JP29 BICK_INV JP27 BICK DIR ADC INV JP19 BICK_SEL THR 64fs 32fs 16fs EXT c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator. JP28 FCK DIR JP22 FCK_SEL ADC 2fs 1fs EXT d) Set up jumper pins of DATA When D/A converter of the AK4633VN is evaluated by using DIR of AK4114, the jumper pins should be set to the following. JP30 JP26 4633_SDTI SDTI DIR ADC DAC/LOOP ADC <KM079406> 2007/04 -7- ASAHI KASEI [AKD4633-A] (5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode a) Set up jumper pins of MCKI clock JP6 MCKI JP21 MCLK_SEL JP18 MKFS XTL DIR EXT 256fs 512fs 1024fs JP17 XTE b) Set up jumper pins of BICK clock JP20 BICK INV THR JP27 BICK DIR ADC JP29 BICK_INV INV JP19 BICK_SEL THR 64fs 32fs 16fs EXT c) Set up jumper pins of FCK clock JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator. JP28 FCK DIR JP22 FCK_SEL ADC 2fs 1fs EXT d) Set up jumper pins of DATA When A/D converter of the AK4633VN is evaluated by using DIR of AK4114, the jumper pins should be set to the following. JP30 JP26 4633_SDTI SDTI DIR ADC DAC/LOOP ADC <KM079406> 2007/04 -8- ASAHI KASEI [AKD4633-A] DIP Switch set up [SW3] (MODE) : Mode Setting of AK4633-VN and AK4114 ON is “H”, OFF is “L”. No. Name ON (“H”) OFF (“L”) 1 DIF0 AK4114 Audio Format Setting 2 DIF1 See Table 2 3 DIF2 Clock Operation Mode select 4 CM0 See Table 3 5 CM1 6 OCKS0 Master Clock Frequency Select See Table 4 7 OCKS1 8 M/S Master mode Slave mode Note. When the AK4633VN is evaluated Master mode, “No.8 of SW3” is set to “H”. Table 1. Mode Setting for AK4633VN and AK4114 Resistor setting for AK4633VN Audio Interface Format Setting for AK4114 Audio Interface Format DIF1 bit DIF0 bit DIF0 DIF1 DIF2 0 1 L L L 24bit, Left justified 16bit, Right justified 1 0 L L H 24bit, Left justified 24bit, Left justified 1 1 H L H DAUX SDTO 2 Default 2 24bit, I S 24bit, I S Note. When the AK4633VN is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”. Table 2. Setting for AK4114 Audio Interface Format Mode 0 1 CM1 0 0 CM0 0 1 UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 Default 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Default setting is recommended. Table 3. Clock Operation Mode select No. 0 2 OCKS1 0 1 MCKO1 256fs 512fs MCKO2 256fs 256fs X’tal 256fs 512fs Default Table 4. Master Clock Frequency Select (Stereo mode) <KM079406> 2007/04 -9- ASAHI KASEI [AKD4633-A] Other jumper pins set up 1. JP1 (GND) OPEN SHORT : Analog ground and Digital ground : Separated. : Common. (The connector “DGND” can be open.) <Default> 2. JP2 (MICP) MICP BEEP : Connection between MICP pin and BEEP pin of the AK4633VN. : MIC Differential input. : BEEP input. <Default> 3. JP3 (AVDD_SEL) : AVDD of the AK4633VN REG : AVDD is supplied from the regulator (“AVDD” jack should be open). < Default > AVDD : AVDD is supplied from “AVDD ” jack. 4. JP9 (DVDD_SEL) : DVDD of the AK4633VN AVDD : DVDD is supplied from “AVDD”. < Default > DVDD : DVDD is supplied from “DVDD ” jack. 5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line. DVDD : Logic block of LVC is supplied from “DVDD”. < Default > VCC : Logic block of LVC is supplied from “VCC ” jack. 6. JP11 (VCC_SEL) : Logic block is selected supply line. LVC : Logic is supplied from supply line of LVC. < Default > VCC : Logic block of LVC is supplied from “VCC ” jack. 7. JP4 (SVDD_SEL) : SVDD of the AK4633VN REG : SVDD is supplied from the regulator (“SVDD” jack should be open). < Default > SVDD : SVDD is supplied from “SVDD ” jack. 8. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114. MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4633VN. < Default > MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4633VN. <KM079406> 2007/04 - 10 - ASAHI KASEI [AKD4633-A] The function of the toggle SW [SW1] (DIR) : Power control of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. [SW2] (PDN) : Power control of AK4633VN. Keep “H” during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK4633VN can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4633-A Connect PC 10 wire flat cable 10pin Connector CSN CCLK AKD4633-A CDTI 10pin Header Figure 2. Connect of 10 wire flat cable <KM079406> 2007/04 - 11 - ASAHI KASEI [AKD4633-A] Analog Input / Output Circuits (1) Input Circuits a) MIC Input Circuit J1 MIC-JACK 6 4 3 AVSS JP12 MIC_SEL JACK INT J3 MIC RCA 2 3 1 MR-552LS AVSS Figure 3. MIC Input Circuit (a-1) Analog signal is input to MIC pin via J1 connector. JP12 MIC_SEL RCA JACK (a-2) Analog signal is input to MIC pin via J3 connector. JP12 MIC_SEL RCA JACK b) BEEP Input Circuit J4 BEEP 2 C26 1u R18 47k MR-552LS AVSS R19 1 + 2 3 1 BEEP 20k AVSS Figure 4. BEEP Input Circuit <KM079406> 2007/04 - 12 - ASAHI KASEI [AKD4633-A] (2) Output Circuits a) AOUT Output Circuit 1 AOUT + C28 R20 220 2 1u J5 AOUT 2 3 1 R21 20k MR-552LS AVSS AVSS Figure 5. AOUT Output Circuit b) SPK Output Circuit Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14 (SPN_SEL) should be open, or “PMSPK bit” in the AK4633VN should be set to “0”. JP31 Dynamic R15 10 3 4 SVSS SPN J2 SPK-JACK 6 JP13 D1 A SVSS K DIODE ZENER SVSS K DIODE ZENER SPK1 SPN_SEL JP14 D2 A Dynamic(EXT) Piezo(EXT) Dynamic CN5 Dynamic(EXT) Piezo(EXT) Dynamic 020S16 R 2 SPP_SEL 1 L R17 10 SPP Figure 6. SPK Output Circuit (b-1) An external dynamic speaker is evaluated by using J2 (SPK-JACK) connector. JP13 SPN_SEL Dynamic Dynamic(EXT) Piezo(EXT) JP14 SPP_SEL JP31 Dynamic Dynamic Dynamic(EXT) Piezo(EXT) (b-2) An external Piezo speaker is evaluated by using J2 (SPK-JACK) connector. <KM079406> 2007/04 - 13 - ASAHI KASEI [AKD4633-A] JP13 SPN_SEL Dynamic Dynamic(EXT) Piezo(EXT) JP14 SPP_SEL JP31 Dynamic Dynamic Dynamic(EXT) Piezo(EXT) (b-3) Analog signal of SPP/SPN pins are output from “Dynamic Speaker” on the evaluation (SPK1). JP13 SPN_SEL Dynamic Dynamic(EXT) Piezo(EXT) JP14 SPP_SEL JP31 Dynamic Dynamic Dynamic(EXT) Piezo(EXT) ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM079406> 2007/04 - 14 - ASAHI KASEI [AKD4633-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4633-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4633-A by 10-line type flat cable (packed with AKD4633-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4633VN Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4633.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4633VN. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM079406> 2007/04 - 15 - ASAHI KASEI [AKD4633-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4633VN by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button. <KM079406> 2007/04 - 16 - ASAHI KASEI [AKD4633-A] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4633VN. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM079406> 2007/04 - 17 - ASAHI KASEI [AKD4633-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM079406> 2007/04 - 18 - ASAHI KASEI [AKD4633-A] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM079406> 2007/04 - 19 - ASAHI KASEI [AKD4633-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3. Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 3-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 3-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM079406> 2007/04 - 20 - ASAHI KASEI [AKD4633-A] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (2) Click [WRITE] button, then the register setting is executed. <KM079406> 2007/04 - 21 - ASAHI KASEI [AKD4633-A] Figure 5. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM079406> 2007/04 - 22 - ASAHI KASEI [AKD4633-A] 8. [Filter Dialog] It is possible to calculate the coefficients of HPF and EQ filters, write these coefficients to registers and confirm the frequency response of these filters. Click [Filter] button, then the window as shown in Figure 6 opens. Figure 6. [Filter] Window (1) Setup the Parameters Set up the parameters of HPF and EQ filters. Parameter Contents Sampling Rate Sampling Frequency (fs) HPF Cut Off Frequency High Pass Filter Cut Off Frequency EQ1 Center Frequency EQ1 Center Frequency EQ1 Band Width EQ1 Band Width (Note 1) EQ1 Gain EQ1 Gain (Note 2) EQ2 Center Frequency EQ2 Center Frequency EQ2 Band Width EQ2 Band Width (Note 1) EQ2 Gain EQ2 Gain (Note 2) Note 1. Band width of 3dB gain difference from center frequency Note 2. This filter is notch filter when this gain is -1. Setup range 48000Hz ≥ fs ≥ 7350Hz (fs/2 – 1) ≥ fc > fs/10000 fs/2 ≥ EQ1 > 0Hz fs/2 ≥ EQ1 >1Hz 3 > EQ1 ≥- 1 fs/2 ≥ EQ2 > 0Hz fs/2 ≥ EQ2 >1Hz 3 > EQ2 ≥- 1 (2) Filter ON/OFF Set up the ON or OFF of filters by the check button of "HPFAD", "HPF", "EQ1" and "EQ2". The filter is ON when the button is checked. Figure 7. Filter ON/OFF check button <KM079406> 2007/04 - 23 - ASAHI KASEI [AKD4633-A] (3) Calculation of Register Setting When [Register Setting] is clicked, the register setting of filters are displayed in "Register Setting" area. At the same this, these setting are written to HPFAD bit, HPF bit, EQ1 bit, EQ2 bit and 10H-1FH registers. If the parameter is out of range, then the error message is displayed and these writing to register aren't executed. Figure 8. Calculation result to register parameters (4) Frequency Response When [Register Setting] is clicked, the frequency response is displayed. At the same this, these setting are written to HPFAD bit, HPF bit, EQ1 bit, EQ2 bit and 10H-1FH registers. If [UpDate] button is clicked after setting the frequency range, the display of frequency response is updated. Figure 9. Frequency characteristic indicates result <KM079406> 2007/04 - 24 - ASAHI KASEI [AKD4633-A] Revision History Date 05/07/14 05/08/23 05/09/16 05/10/21 06/04/14 Manual Revision KM079400 KM079401 KM079402 KM079403 KM079404 Board Revision 0 1 1 2 2 Reason First Edition Update Error Correct Update Update 07/02/15 KM079405 3 Error Correct 07/04/02 KM079406 3 Error Correct Contents Change of a figure & circuit Port Numbers are corrected in circuit. Device revision of AK4633 is changed to “Rev.B”. Part change in LOGIC circuit diagram. U9: 74LVC541Æ74HC541 Port number was corrected in both silkscreen printing and circuit diagram. JP1(MICP) Æ JP2 (MICP) Port number was corrected in both silkscreen printing and circuit diagram. Silkscreen printing: JP2 (MCKI) Æ JP6 (MCKI) Circuit diagram: JP5 (MCKI) Æ JP6 (MCKI) IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM079406> 2007/04 - 25 - D AVSS SVSS VCC3.3V REG AVDD DVDD AVSS SVDD SVSS DGND T45_O T45_R T45_O T45_O T45_BK T45_BU T45_BK T45_BK REG_IN AVDD DVDD AVSS SVDD 1 1 1 1 1 1 1 1 25 26 27 28 VCC3.3V AVSS SVSS JP2 MICP R1 2.2k + C1 1u E E CN1 32pin_4 29 AVSS 30 C3 + 47u 31 1 2 C2 0.1u 32 GND REG OUT C1 0.1u E INT JP1 GND REG_IN T1 TA48033F IN C AOUT B BEEP A BEEP MICP TP4 BEEP C2 0.22u TP2 AOUT 1 1 1 C3 10u D AVSS C5 0.1u REG 10k TP14 VCOC VCOM 2 AVSS 3 AVDD R4 (open) SPN JP4 REG SVDD_SEL DVSS 14 C10 0.1u 13 BICK FCK SDTO CDTI SPN 20 SPP 19 4633_MCKO 18 4633_MCKI 2 (short) TP10 MCKO 1 MCKI PDN DVDD 21 C16 + 47u TP12 MCKI VCOC CSN SVDD L2 SVSS JP6 MCKI C11 10u 17 C 32pin_3 AVSS 32pin_1 12 51 11 R7 9 7 8 10 1 PDN 17 16 5 TP15 PDN AVSS SPP MCKO 15 CCLK 7 D SVDD 1 TP9 SPP 18 4 6 C AK4633VN SDTI 1 C9 4.7n 6 22 1 4 5 23 TP13 SPN 1 19 20 21 22 1 R5 1 8 AVSS AVSS TP6 SVDD 1 C8 0.1u SVSS C7 10u SVDD TP8 AVSS AVDD BEEP 3 AVDD AOUT AVDD MPI 1 (short) 23 U1 1 1 + 2 47u C4 0.1u + C13 2 2 + 24 L1 1 C6 2.2u TP7 AVSS MIC REG + AVDD_IN AVSS TP11 VCOM 1 REG 24 1 CN2 JP3 AVDD_SEL CN3 + R2 2.2k 1 1 2 TP1 TP3 MIC MPI B B AVDD JP9 AVDD DVDD_SEL DVDD_IN L4 C22 + TP17 TP18 CCLK CDTI 1 DVDD DVDD R40 (short) TP19 SDTI 1 TP20 TP21 SDTO FCK 1 1 TP22 BICK 1 TP23 DVDD 1 1 R14 10 2 (short) 1 DVDD R8 51 JP10 LVC_SEL R9 51 R10 51 R11 51 R12 51 R13 51 R22 51 2 47u 1 1 TP16 CSN L5 16 15 14 13 A A B C Title DVDD 4633_BICK CDTI CCLK 4633_FCK VCC 4633_SDTO 1 2 (short) CSN 47u + 2 C23 CN4 32pin_2 D3.3V 4633_SDTI 1 A JP11 VCC_SEL 12 LVC 11 VCC3.3V 10 VCC 9 LVC AVSS Size A3 Date: D AKD4633-A Document Number Rev AK4633-VN Friday, March 30, 2007 Sheet E 3 1 of 5 A B C D E J1 MIC-JACK 6 JP31 Dynamic 4 3 E AVSS JACK JP12 MIC_SEL R15 10 INT J3 MIC RCA 6 JP13 D1 A K MR-552LS AVSS SVSS C26 1u 2 R18 47k MR-552LS R19 1 + 2 3 1 A BEEP 20k SVSS Dynamic(EXT) Piezo(EXT) Dynamic SPK1 SPN_SEL DIODE ZENER JP14 D2 J4 BEEP AVSS E 3 4 SPN 2 3 1 D J2 SPK-JACK SVSS K DIODE ZENER 020S16 CN5 Dynamic(EXT) Piezo(EXT) Dynamic R 2 SPP_SEL 1 L R17 10 AVSS D SPP + C28 1 AOUT R20 220 J5 AOUT 2 2 3 1 1u R21 20k MR-552LS AVSS AVSS C C B B A A Title Size A3 Date: A B C D AKD4633-A Document Number Rev Input/Output Thursday, February 15, 2007 Sheet E 3 2 of 5 A B C D E for 74HCU04,74AC74,74VHC4040,74HC14,74HC14,74LVC541,74HCT04 1 C30 0.1u C31 0.1u C32 0.1u C33 0.1u C34 0.1u C35 0.1u C36 0.1u 2 2 E 1 D3.3V 12.288MHz X1 E + C37 47u R24 1M U2C 5 U2B 6 3 74HCU04 JP17 XTE C38 (open) 4 74HCU04 C39 (open) D D EXT_MCLK Q 10 5 12 D 11 CLK PR Q CL CLK CL MCLK_SEL C 3 U4A 74AC74 6 1 DIR_MCLK R25 short D D3.3V U4B 74AC74 Q Q 9 256fs 512fs 1024fs MCKO JP18 MKFS U3 10 11 8 13 JP21 XTL DIR EXT 2 PR 4 D3.3V CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 74VHC4040 JP19 BICK_SEL 64fs 32fs 16fs EXT THR 1 JP20 BICK EXT_BICK 2 U5A 74HC14 INV C JP22 2fs 1fs EXT EXT_FCK FCK_SEL MCKO J8 EXT/BICK 2 3 1 B B R26 51 MR-552LS AVSS JP23 EXT1 J9 FCK 2 3 1 R27 51 MR-552LS AVSS A JP24 EXT2 A Title Size A3 Date: A B C D AKD4633-A Document Number Rev CLOCK Thursday, February 15, 2007 Sheet E 3 3 of 5 A B C D E C40 C41 0.1u 0.1u D3.3V L6 (short) R28 10k 3 2 1 VCC GND OUT 0.1u C43 10u R29 470 2 4 1 E U5C 3 74HC14 D3.3V + TORX141 U5B D3 HSU119 6 5 74HC14 L C44 0.1u H SW1 DIR 2 C45 0.1u 1 C42 3 PORT1 A 2 E K 1 D3.3V 1 38 37 INT1 R AVDD 40 39 R30 18k VCOM 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 RX2 U6 16 15 14 13 12 11 10 9 NC 48 SW3 1 2 3 4 5 6 7 8 RX3 DIF0 DIF1 DIF2 CM0 CM1 OCKS0 OCKS1 M/S D 47 C46 0.47u D R31 1k U7D IPS0 INT0 36 9 8 LED1 ERF K A D3.3V 74HC04 2 NC OCKS0 35 OCKS0 3 DIF0 OCKS1 34 OCKS1 4 TEST2 CM1 33 CM1 5 DIF1 CM0 32 CM0 6 NC PDN 31 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 DIR_BICK 12 VIN SDTO 25 DIR_SDTI RP1 CM0 CM1 OCKS0 OCKS1 M/S 47k AK4114 C C C47 (open) 1 9 8 7 6 5 4 3 2 1 C48 (open) 2 X2 11.2896MHz DAUX 2 1 C51 10u D3.3V LRCK 24 MCKO1 23 22 C50 0.1u + + C49 0.1u 1 DVSS DVDD 21 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 TVDD 13 TX0 B DVSS B DIR_FCK JP25 MCKO_SEL MCKO2 MCKO1 DIR_MCLK 2 C52 10u D3.3V PORT2 A IN VCC GND 3 2 1 A D3.3V C53 0.1u TOTX141 Title Size A3 Date: A B C D AKD4633-A Document Number Rev DIR/DIT Thursday, February 15, 2007 Sheet E 3 4 of 5 A B C D U8 74HC541 1 E 11 Y8 A8 9 12 Y7 A7 8 4633_MCKO 4633_MCKI 13 Y6 A6 7 EXT_MCLK DAUX 14 Y5 A5 6 4633_SDTO JP26 4633_SDTI DAC/LOOP 4633_SDTI 15 Y4 A4 5 16 Y3 A3 4 17 Y2 A2 3 18 Y1 A1 2 MCKO E LVC DIR 20 VCC E M/S C54 0.1u GND 10 A1 B1 18 3 A2 B2 17 4 A3 B3 16 5 A4 B4 15 6 A5 B5 14 7 A6 B6 13 B7 12 19 G 2 RP2 RP3 7 6 5 4 3 2 1 47k ADC 7 6 5 4 3 2 1 47k D D 10 GND 4633_BICK 19 G2 VCC A7 JP27 BICK ADC DIR C55 0.1u 20 8 4633_FCK 1 G1 9 A8 EXT_BICK DIR_BICK 11 B8 JP28 FCK 74LVC245 ADC DIR U9 EXT_FCK DIR_FCK C C 2 1 LVC JP29 U10F + C56 47u 13 INV 12 THR 74HC14 BICK_INV R32 R34 R36 D3.3V PORT4 1 2 3 4 5 B 10 9 8 7 6 10k 10k 10k R33 R35 R37 U11 470 470 470 CSN CCLK CDTI 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11 1 19 G1 G2 VCC GND 20 10 CSN CCLK CDTI PDN 4633_MCKI MCLK BICK FCK SDTI VCC 10 9 8 7 6 ROM D3.3V B R38 74LVC541 CTRL PORT3 1 2 3 4 5 D3.3V 10k ADC K D3.3V A D4 HSU119 R39 10k U5D 9 11 10 U2A 74HC14 1 1 C57 0.1u 13 10 74HCU04 5 3 11 U10C 10 5 74HC04 74HC04 13 6 U10E 11 74HC14 U7F 6 4 74HC14 U7E 4 U7C U2E U10B 2 74HC04 74HC04 74HCU04 11 1 U7B 3 2 8 12 74HCU04 U2D 9 U7A U2F 2 74HCU04 SW2 PDN A U10D 12 74HC04 9 8 74HC14 10 A 74HC14 U10A 1 Title 2 74HC14 Size A3 Date: A DIR_SDTI DIR U5E 8 74HC14 H 3 L DAUX JP30 SDTI B C D AKD4633-A Document Number Rev LOGIC Thursday, February 15, 2007 3 Sheet E 5 of 5