AKM AKD4634-A

[AKD4634-A]
AKD4634-A
AK4634 Evaluation board Rev.1
GENERAL DESCRIPTION
AKD4634-A is an evaluation board for the AK4634, 16bit mono CODEC with MIC/SPK/VIDEO amplifier.
The AKD4634-A can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). AKD4634-A also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
„ Ordering guide
AKD4634-A
--- Evaluation board for AK4634
(Cable for connecting with printer port of IBM-AT, compatible PC and control software
are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
AVDD DVDD SVDD
5V
GND
3.3V
Regulator
Control Data
MIC-Jack
MIC/
MICP
10pin Header
LIN/
MICN
AOUT
DSP
AK4634
10pin Header
SPK-Jack
AK4114
Opt In
Opt Out
Clock
Gen
Figure 1. AKD4634-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD and VCC are supplied from the regulator. <Default>
JP3
AVDD_SEL
REG
[REG]
[AVDD]
[DVDD]
[SVDD]
[VCC]
[AVSS]
[SVSS]
[DGND]
AVDD SVDD
(red )
(orange)
(orange)
(blue)
(orenge)
(black)
(black)
(black)
JP9
DVDD_SEL
JP4
SVDD_SEL
JP10
LVC_SEL
REG DVDD AVDD VCC
= 5V
= open
= open
= open
= open
= 0V
= 0V
= 0V
JP11
VCC_SEL
DVDD VCC
LVC
: 3.3V is supplied to AVDD of AK4634 from regulator.
: 3.3V is supplied to DVDD of AK4634 from regulator.
: 3.3V is supplied to SVDD of AK4634 from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD and VCC are supplied from the power supply connectors.
JP3
AVDD_SEL
REG
[REG]
[AVDD]
[DVDD]
[SVDD]
[VCC]
[AVSS]
[SVSS]
[DGND]
JP4
SVDD_SEL
AVDD SVDD
(red)
(orange)
(orange)
(blue)
(orenge)
(black)
(black)
(black)
JP9
DVDD_SEL
JP10
LVC_SEL
REG DVDD AVDD VCC
= open.
= 2.2 ∼ 3.6V
= 2.7 ∼ 3.6V
= 2.2 ∼ 4.0V
= 2.7 ∼ 3.6V
= 0V
= 0V
= 0V
JP11
VCC_SEL
DVDD VCC
LVC
: for AVDD of AK4634 (typ. 3.3V)
: for DVDD of AK4634 (typ. 3.3V)
: for SVDD of AK4634 (typ. 3.3V)
: for logic (typ. 3.3V)
: for analog ground
: for analog ground
: for logic ground
* Each supply line should be distributed from the power supply unit.
DVDD and VCC must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4634 and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
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„ Evaluation mode
In case of AK4634 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4634 and AK4114. About AK4634’s audio interface format, refer to datasheet of AK4634. About
AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: MCKI pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: BICK or FCK pin)
(4) Evaluation of loop-back mode (A/D → D/A) : EXT, Master Mode
(5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
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(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
Set “No.8 of SW3” to “H”. X’tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal of 12MHz
(Default) is set on the AKD4634-A.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4634.
There is no necessity for set up JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP29
BICK_INV
JP27
BICK
DIR ADC
THR
INV
THR
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
DAC/LOOP ADC
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(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
X’tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal of 12 MHz (Default) is set on the
AKD4634-A. In this case, the AK4634 corresponds to PLL reference clock of 12MHz. In this evaluation mode,
the output clock from MCKO-pin of the AK4634 is supplied to a divider (U3: 74VHC4040), BICK and FCK
clocks are generated by the divider. Then “MCKO bit” in the AK4634 is set to “1”. When an external clock
through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17
(XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock
generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
THR
JP27
BICK
DIR ADC
JP29
BICK_INV
INV
THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
DAC/LOOP ADC
ADC
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(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: BICK or FCK pin)
a) Set up jumper pins of MCKI clock
An external clock through a RCA connector (J8: EXT/BICK), BICK and FCK clocks are generated by the
divider. JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock
generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select XTL on JP21.
*When X’tal is used, X’tal of 256fs, 512fs or 1024fs can be set in X1. Set OPEN on JP17, and select XTL on
JP21.
b) Set up jumper pins of BICK clock
Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP27
BICK
THR
DIR ADC
JP29
BICK_INV
INV
THR
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP19. JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP22. JP24 (EXT1)
and R27 should be properly selected in order to much the output impedance of the clock generator.
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
ADC
<KM088301>
DAC/LOOP ADC
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[AKD4634-A]
(4) Evaluation of loop-back mode (A/D → D/A) : EXT, Master Mode
a) Set up jumper pins of MCKI clock
Set “No.8 of SW3” to “H”. An external clock (256fs, 512fs or 1024fs) through a RCA connector (J8:
EXT/BICK) is supplied. JP23 (EXT1) and R26 should be properly selected in order to much the output
impedance of the clock generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (32fs or 64fs) of BICK should be set by “BCKO1-0 bit” in the AK4634.
There is no necessity for set up JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
JP26
4632_SDTI
SDTI
DIR
DAC/LOOP ADC
ADC
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(5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
XTL DIR EXT 256fs 512fs 1024fs MCKO
b) Set up jumper pins of BICK clock
JP20
BICK
JP19
BICK_SEL
64fs 32fs 16fs EXT
INV
JP29
BICK_INV
JP27
BICK
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4634 is evaluated by using DIR of AK4114, the jumper pins should be set to the
following.
JP30
JP26
4632_SDTI
SDTI
DAC/LOOP ADC
ADC
DIR
When A/D converter of the AK4634 is evaluated by using DIT of AK4114, the jumper pins should be set to the
following.
JP30
JP26
4632_SDTI
SDTI
DIR
DAC/LOOP ADC
ADC
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„ DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4634 and AK4114
ON is “H”, OFF is “L”.
No.
1
2
3
4
5
6
7
8
Name
OFF (“L”)
ON (“H”)
Default
DIF0
AK4114 Audio Format Setting
Off
DIF1
See Table 2
Off
DIF2
On
CM0
Clock Operation Mode select
Off
CM1
See Table 3
On
OCKS0
Master Clock Frequency Select
Off
OCKS1
See Table 4
Off
M/S
Slave mode
Master mode
On
Note. When the AK4634 is evaluated Master mode, “M/S” is set to “H”.
Table 1. Mode Setting for AK4634 and AK4114
Register setting
for AK4634
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
DAUX
SDTO
0
1
L
L
L
24bit, Left justified
16bit, Right justified
1
0
L
L
H
24bit, Left justified
24bit, Left justified
Default
1
1
H
L
H
24bit, I2S
24bit, I2S
Note. When the AK4634 is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 2. Setting for AK4114 Audio Interface Format
Mode
0
1
CM0
L
H
2
L
3
H
CM1
L
L
UNLOCK
PLL
X'tal
Clock source
ON
OFF
PLL
OFF
ON
X'tal
0
ON
ON
PLL
H
1
ON
ON
X'tal
H
ON
ON
X'tal
ON: Oscillation (Power-up), OFF: STOP (Power-down)
SDTO
RX
DAUX
RX
DAUX
DAUX
Default
Table 3. Clock Operation Mode select
No.
0
2
OCKS0
L
L
OCKS1
L
H
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
Table 4. Master Clock Frequency Select
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„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP3 (AVDD_SEL) : AVDD of the AK4634
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
3. JP4 (SVDD_SEL) : SVDD of the AK4634
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
4. JP9 (DVDD_SEL) : DVDD of the AK4634
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
6. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP25 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4634. < Default >
MCKO2
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4634.
8. JP102 (I2C)
OPEN
SHORT
: Control Interface is selected mode.
: 3-wire Serial Control Mode. < Default >
: I2C-bus Control Mode. (Not used in this board.)
9. JP103 (MCKO)
OPEN
SHORT
: Master Clock Frequency is selected from AK4634.
: Not supply.
: Supplied from AK4634. < Default >
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[AKD4634-A]
„ The function of the toggle SW
[SW1] (DIR)
: Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN)
: Power control of AK4634. Keep “H” during normal operation.
„ Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
„ Serial Control
The AK4634 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4
(CTRL) with PC by 10 wire flat cable packed with the AKD4634-A
Connect
PC
10 wire
flat cable
10pin
Connector
CSN
CCLK
CDTI
AKD4635
10pin Header
Figure 2. Connect of 10 wire flat cable
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[AKD4634-A]
„ Analog Input / Output Circuits
(1) Input Circuits
a) MIC/MICP Input Circuit
J1
MIC-JACK
JP105
MPI
6
4
3
AVSS
J3
MIC/MICP
MPI
JACK
JP12
MIC_SEL
R112
2.2k
MIC/MICP
RCA
C108
1u
2
3
1
MR-552LS
AVSS
Figure 3. MIC/MICP Input Circuit
(a-1) Analog signal is input to MIC pin via J1 connector.
JP105
MPI
JP12
MIC_SEL
RCA JACK
(a-2) Analog signal is input to MIC/MICP pin via J3 connector.
JP105
MPI
JP12
MIC_SEL
RCA JACK
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b) LIN/MICN Input Circuit
J4
LIN/MICN
C112
1u
2
3
1
MR-552LS
LIN/MICN
R18
47k
JP113
MICN
R113
2.2k
AVSS
Figure 4. LIN/MICN Input Circuit
(b-1) LIN is input from J4.
JP104
MICN
(b-2) MICN is input from J4.
JP104
MICN
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(2) Output Circuits
a) AOUT Output Circuit
AOUT
+
C28
1
2
R20
220
1u
2
3
1
R21
20k
AVSS
J5 AOUT
MR-552LS
AVSS
Figure 5. AOUT Output Circuit
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C) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4634 should be set to “0”.
JP31
Dynamic
R15
10
3
4
SVSS
SPP
J2
SPK-JACK
6
JP13
D1
A
K
JP14
D2
A
SVSS
SPK1
SPP_SEL
DIODE ZENER
SVSS
Dynamic(EXT)
Piezo(EXT)
Dynamic
K
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
2
SPN_SEL
DIODE ZENER
020S16
R
1
L
R17
10
SPN
Figure 6. SPK Output Circuit
(C-1) “Dynamic Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(C-2) “Piezo (Ceramic) Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(C-3) Analog signal of SPP/SPN pins are output “Dynamic Speaker” on the evaluation (SPK1).
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
∗ AKEMD assumes no responsibility for the trouble when using the above circuit examples.
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[AKD4634-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4634-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4634-A by 10-line type flat cable (packed with AKD4634-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4634 Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4634.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
„ Explanation of each buttons
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
[Port Reset] :
[Write default] :
[All Write] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5] :
[SAVE] :
[OPEN] :
[Write] :
[Filter] :
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of the AK4634.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Set Programmable Filter (HPF, LPF, EQ1~5) of AK4634 easily.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
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[AKD4634-A]
„ Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL, OVOL.
There are dialogs corresponding to register of 09h and 0Ah.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to the AK4634 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4634, click [OK] button. If not, click [Cancel] button.
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4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4634. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
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[AKD4634-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused
step.
This sequence can be saved and opened by [Save] and [OPEN] button on the Function3 window. The extension of
file name is “aks”.
Figure 7. [F3] Window
<KM088301>
2007/07
- 19 -
[AKD4634-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 8 opens.
Figure 8. [F4] window
<KM088301>
2007/07
- 20 -
[AKD4634-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 9.
Figure 9. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM088301>
2007/07
- 21 -
[AKD4634-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 11.
(2) Click [WRITE] button, then the register setting is executed.
<KM088301>
2007/07
- 22 -
[AKD4634-A]
Figure 11. [F5] window (2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM088301>
2007/07
- 23 -
[AKD4634-A]
8. [Filter Dialog]
A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check
frequency response such as HPF,EQ filter.
Window to show to Figure 12 opens when push a [Filter] button .
Figure12. [Filter] Window
8-1. Setting of a parameter
(1) Please set a parameter of each Filter.
Item
Contents
Setting range
Sampling Rate
Sampling frequency (fs)
7350Hz ≤ fs ≤ 48000Hz
HPF
Cut Off Frequency
High pass filter cut off frequency
fc/fs ≥ 0.0001 (fc min = 1.6Hz at 16kHz)
LPF
Cut Off Frequency
Low pass filter cut off frequency
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Center Frequency
fon / fs < 0.497
EQ1-5 Band Width
EQ1-5 Band Width
(Note 1)
EQ1-5 Gain
EQ1-5 Gain
(Note 2)
-1≤ Kn < 3
Note 1. A gain difference is a bandwidth of 3dB from center frequency.
Note 2. When a gain is smaller than 0 , EQ becomes a notch filter.
<KM088301>
2007/07
- 24 -
[AKD4634-A]
(2) “LPF”, “HPF”, “HPFAD”, “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When checked “Notch Filter Auto Correction”, perform automatic revision of
center frequency of a notch filter. (“Cf. 8-4. automatic revision of center frequency of a notch filter”)
Figure13. Filter ON/OFF setting button
8-2. A calculation of a register
A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error
message is displayed, and, a calculation of register setting is not carried out.
Figure14. A register setting calculation result
When it is as follows that a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
<KM088301>
2007/07
- 25 -
[AKD4634-A]
8-3.Indication of a frequency characteristic
A frequency characteristic is displayed when push a [Frequency Response] button. In addition, a register set point is
updated then, too.
Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure15. A frequency characteristic indication result
When it is as follows that a register set point is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
8-4. Automatic revision of center frequency of a notch filter
When set a gain of 5 band Equalizer to -1, Equalizer becomes a notch filter. When center frequency of plural notch filters
is adjacent, produce a gap to central frequency (Figure 16). When check "a Notch Filter Auto Correction" button, perform
automatic revision of central frequency of a notch filter, display register setting after automatic revision and a frequency
characteristic (Figure 17). This automatic revision is availability for Equalizer Band which set a gain to "-1".
(Note) When distance among center frequency is smaller than band width, there is a possibility that automatic revision is
not performed definitely. Please confirm a revision result by indication of a frequency characteristic.
<KM088301>
2007/07
- 26 -
[AKD4634-A]
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure16. When there is no revision of center frequency
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure17. When there is revision of center frequency
<KM088301>
2007/07
- 27 -
[AKD4634-A]
Revision History
Date
07/04/05
07/07/02
Manual
Revision
KM088300
KM088301
Board
Revision
0
1
Reason
First Edition
Device Rev. changed
Contents
AK4634: Rev.A → Rev.B
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM088301>
2007/07
- 28 -
TP102
(open) 1
DC
SAG
2
C102
(open)
1
2
1
C100
0.1u
TST2
AVDD
E1
D1
D
TP125
VCOC R111
10k
1
CDTIO
MPI
32
JP105 MPI
D3
1
TP122
MIC
CCLK/SCL
MIC/MICP
E3
30
C108 1u
A3
FCK
C4
A4
AK4634
LIN/MICN
E4
29
MCKI
AOUT
D4
28
BICK
SVDD
D5
1
13
14
C
TP111
BICK
TP112
DVDD
1
15
C106
0.1u +
SDTI
A5
SDTO
A6
I2C
27
26
1
B4
TP121
AOUT
C107
10u
1
16
CN104
8P
SPP
E5
NC
E6
25
JP102
C104
0.1u
VSS3
R110
open
+
C112
1u
L100
open
1
1
CN101
8P
D6
C5
SPN
VSS2
C6
B6
B5
R101
10k
DVDD
MCKO
I2C
B
31
1
B3
TP109
SDTO
TP110
R107 51 FCK
TP123
AVSS
2
C110 2.2u
R112
2.2k
12
1
PDN
1 1
C109 0.1u
C3
TP108
R105 51 SDTI
1
VCOM
D2
TP107
CDTI
11
R108 51
E2
1
1
10
R106 51
VCOC
TP124
VCOM
A2
R104 51
CSN/SDA
1
B2
TP106
R103 51 CCLK
C111
4700p
2
R102 51
9
+
TP105
CSN
1
C1
1
TST1
TST3
A1
C2
1
+
D
C
C101
10u
2
+
U100
1
JP100
(open)
DC
JP101
(open)
C103
(open)
E
TP101
AVSS
1
TP103
(open)
VSS1
TP104
PDN 1
SAG
2
E
E
TP100
AVDD 1
+
R100
51
D
3
4
5
CN102
8P
6
C
7
B
8
A
R113
2.2k
2
2
C105
10u
TP115
MCKO
1
B
JP104
MICN
JP103
MCKO
TP119
SVSS 1
1
1
1
A
24
TP120
LIN
23
TP118
SVDD
22
20
19
CN103
8P
TP117
SPP 1
TP116
SPN
18
A
17
TP113
AVSS 1R109
51
21
TP114
MCKI 1
Title
Size
A3
Date:
A
B
C
D
AKD4634-A
Document Number
Rev
AK4634_SUB_29CSP
Monday, February 26, 2007
Sheet
E
1
0
of
1
A
B
REG_IN T1
TA48033F
MOUT
SVSS
AOUT
AVSS
BEEP
C3
+
47u
INT
1
C2
0.1u
E
DGND
T45_BK
T45_BK
C5
(NMT)
+
2
25
MOUT
26
AOUT
C14
(NMT)
2
C11
(NMT)
C15
(NMT)
C12
(NMT)
4
VVDD
SPP
(NMT)
SAGC11
2
1
C17 (NMT)
SPN
20
MCKO
19
SVDD
L2
1
SVDD
21
R4
(NMT)
21
SPP
20
SPN
2
(short)
C16
+
47u
C
MCKI
18
8
PDN
DVSS
17
4632_MCKO
18
4632_MCKI
JP6 (NMT)
17
DVDD
32pin_3
C20
(NMT)
16
BICK
FCK
15
10
14
CCLK
CSN
9
AVSS
SDTO
AVSS
13
+
VSAG
R6 (NMT)
2
19
SVSS
7
1
SAGC11 2
JP7
C18 (NMT)
(NMT)
8
32pin_1
VVDD
VOUT
REG
JP4
SVDD_SEL
SVSS
22
SAGC00
2
(NMT)
6
23
SAGC00
7
PDN
L3
JP5
(NMT)
SDTI
6
VIN
12
VOUT
5
CDTI
5
SVSS
R3 (NMT)
11
VIN
JP8
AVDD (NMT)
VVDD
1
27
22
+
AVDD
+
BEEP
SVDD
R5 (NMT)
AVSS
C19
(NMT)
AIN
MICOUT
AVSS
4
1
28
29
30
MIC
31
MPI
VCOM
3
1
AVSS
AVSS
C
REG
MIN
24
1
1
3
SVSS
2
AVDD
AVDD
23
2
2
AVDD
1
1
(short)
24
2
C10
(NMT)
+
+
47u
+
C9
(NMT)
2
2
MIN
AVSS
1
L1
1
VCOC
+
REG
AVDD_IN
SVSS
D
CN3
CN2
JP3
AVDD_SEL
32
U1
1
SVDD
1
1
C8
(NMT)
REG
VCC_IN
AVSS
R1 C6
C7
(NMT) (NMT) (NMT)
AVSS
R2 (NMT)
VVDD
+
D
REG_IN AVDD_IN DVDD_IN
JP2
(NMT)
2
2
C4
(NMT)
1
SVSS
T45_BU
1
SVDD
T45_O
1
VCC
T45_BK
1
AVSS
(NMT)
1
VVDD
T45_O
1
DVDD
T45_O
1
AVDD
T45_R
1
REG
1
25
26
27
28
29
30
32
CN1
32pin_4
31
AVSS
AVSS
C13
E
REG
OUT
C1
0.1u
2
E
D
JP1
GND
GND
IN
C
B
AVDD
R7
R8
R9
R10
R11
R12
R13
(NMT) (NMT) (NMT) (NMT) (NMT) (NMT) (NMT)
JP9
AVDD DVDD_SEL
DVDD_IN
L4
13
14
15
4632_SDTO
4632_FCK
4632_BICK
16
12
1
VCC
DVDD
A
Title
2
47u
+
JP11
VCC_SEL
D3.3V
2
(short)
4632_SDTI
L5
1
32pin_2
VCC
LVC
11
CN4
10
DVDD
CDTI
AVSS
VCC_IN
C23
C21
(NMT)
JP10
LVC_SEL
CCLK
R40
(short)
9
DVDD
LVC
A
AVSS
DVDD
2
(short)
CSN
+
2
R1410
2
47u
1
1
C22
1
+
B
Size
A3
Date:
A
B
C
D
AKD4634-A
Document Number
Rev
AK4634
Monday, February 26, 2007
Sheet
E
0
1
of
5
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
E
AVSS
JACK
JP12
MIC_SEL
R15
10
INT
J3
MIC
RCA
6
JP13
D1
A
K
MR-552LS
AVSS
SVSS
C24
(NMT)
2
JP15
(MIN short)
2
3
1
R16
(NMT)
OUT
IN
1
C25
(NMT)
A
SVSS
Dynamic(EXT)
Piezo(EXT)
Dynamic
SPK1
SPP_SEL
ZD5.1
JP14
D2
MOUT
+
J4
BEEP/MIN/MOUT
K
ZD5.1
AVSS
C26
(short)
2
1
+
R18
47k
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
R
2
SPN_SEL
1
L
R17
10
JP16
D
SPN
MOUT
MIN
BEEP
MIN
R19
(MIN short)
BEEP
(NMT)
AVSS
+
C28
1
AOUT
R20
220
J5
AOUT
2
2
3
1
1u
R21
20k
MR-552LS
AVSS
AVSS
C
J6
(NMT)
C
J7
(NMT)
R22
(NMT)
C29
VIN
2
3
1
VOUT
(NMT)
R23
(NMT)
AVSS
020S16
AVSS
MR-552LS
2
3
1
E
3
4
SPP
2
3
1
D
J2
SPK-JACK
SVSS
R41
(NMT)
AVSS
AVSS
AVSS
B
B
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4634-A
Document Number
Rev
Input/Output
Monday, February 26, 2007
Sheet
E
0
2
of
5
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
X1
12MHz
1
C30
0.1u
C31
0.1u
C32
0.1u
C33
0.1u
C34
0.1u
C35
0.1u
C36
0.1u
2
2
E
1
D3.3V
E
+ C37
47u
R24
1M
U2C
5
U2B
6
3
74HCU04
JP17
XTE
C38
5p
4
74HCU04
C39
5p
D
D
EXT_MCLK
Q
10
5
12
D
11
CLK
PR
Q
CL
CLK
CL
MCLK_SEL
C
3
U4A
74AC74
6
1
DIR_MCLK
R25
short
D
D3.3V
U4B
74AC74
Q
Q
9
256fs
512fs
1024fs
MCKO
JP18
MKFS
U3
10
11
8
13
JP21
XTL
DIR
EXT
2
PR
4
D3.3V
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
74VHC4040
JP19
BICK_SEL
64fs
32fs
16fs
EXT
THR
1
JP20
BICK
EXT_BICK
2
INV
U5A
74HC14
C
JP22
2fs
1fs
EXT
EXT_FCK
FCK_SEL
MCKO
J8
EXT/BICK
2
3
1
B
B
R26
51
MR-552LS
AVSS
JP23
EXT1
J9
FCK
2
3
1
R27
51
MR-552LS
AVSS
A
JP24
EXT2
A
Title
Size
A3
Date:
A
B
C
D
AKD4634-A
Document Number
Rev
CLOCK
Monday, February 26, 2007
Sheet
E
0
3
of
5
A
B
C
D
E
C40 C41
0.1u 0.1u
D3.3V
L6
(short)
R28
10k
3
2
1
VCC
GND
OUT
0.1u
C43
10u
R29
470
2
4
1
E
U5C
3
74HC14
D3.3V
+
TORX141
U5B
D3
HSU119
6
5
74HC14
L
C44
0.1u
H
SW1
DIR
2
C45
0.1u
1
C42
3
PORT1
A
2
E
K
1
D3.3V
1
38
37
INT1
R
AVDD
40
39
R30
18k
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
45
TEST1
46
RX2
U6
16
15
14
13
12
11
10
9
NC
48
SW3
1
2
3
4
5
6
7
8
RX3
DIF0
DIF1
DIF2
CM0
CM1
OCKS0
OCKS1
M/S
D
47
C46
0.47u
D
R31
1k
U7D
IPS0
INT0
36
9
8
LED1
ERF
K
A
D3.3V
74HC04
2
NC
OCKS0
35
OCKS0
3
DIF0
OCKS1
34
OCKS1
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
6
NC
PDN
31
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
DIR_BICK
12
VIN
SDTO
25
DIR_SDTI
RP1
CM0
CM1
OCKS0
OCKS1
M/S
47k
AK4114
C
C
C47
5p
1
9
8
7
6
5
4
3
2
1
C48
5p
2
X2
11.2896MHz
DAUX
2
1
C51
10u
D3.3V
LRCK
24
MCKO1
23
22
C50
0.1u
+
+
C49
0.1u
1
DVSS
DVDD
21
20
VOUT
UOUT
19
COUT
18
BOUT
17
TX1
16
15
14
TVDD
13
TX0
B
DVSS
B
DIR_FCK
JP25
MCKO_SEL
MCKO2
MCKO1
DIR_MCLK
2
C52
10u
D3.3V
PORT2
A
IN
VCC
GND
3
2
1
A
D3.3V
C53
0.1u
TOTX141
Title
Size
A3
Date:
A
B
C
D
AKD4634-A
Document Number
Rev
DIR/DIT
Monday, February 26, 2007
Sheet
E
0
4
of
5
A
B
C
D
U8
U9
1
E
11
Y8
A8
9
12
Y7
A7
8
4632_MCKO
4632_MCKI
13
Y6
A6
7
EXT_MCLK
DAUX
14
Y5
A5
6
4632_SDTO
MCKO
E
LVC
DIR
20
VCC
E
M/S
C54
0.1u
GND
10
A1
B1
18
3
A2
B2
17
4
A3
B3
16
5
A4
B4
15
6
A5
B5
14
7
A6
B6
13
B7
12
19
G
2
RP2
JP26
4632_SDTI DAC/LOOP
4632_SDTI
15
Y4
A4
5
16
Y3
A3
4
17
Y2
A2
3
18
Y1
A1
2
RP3
7
6
5
4
3
2
1
47k
ADC
7
6
5
4
3
2
1
47k
D
D
10
GND
4632_BICK
19
G2
VCC
A7
JP27
BICK
ADC
DIR
C55
0.1u
20
8
4632_FCK
1
G1
9
A8
DIR_BICK
11
B8
JP28
FCK
74LVC245
74HC541
EXT_BICK
ADC
DIR
EXT_FCK
DIR_FCK
C
C
2
1
LVC
JP29
U10F
+ C56
47u
13
INV
12
THR
74HC14
BICK_INV
R32
R34
R36
D3.3V
PORT4
1
2
3
4
5
B
10
9
8
7
6
10k
10k
10k
R33
R35
R37
U11
470
470
470
CSN
CCLK
CDTI
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
1
19
G1
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
CSN
CCLK
CDTI
PDN
4632_MCKI
MCLK
BICK
FCK
SDTI
VCC
10
9
8
7
6
ROM
B
R38
74HC541
CTRL
PORT3
1
2
3
4
5
D3.3V
10k
ADC
DAUX
K
D3.3V
A
D4
HSU119
JP30
SDTI
R39
10k
U5D
9
74HC14
H
10
U2A
74HC14
1
SW2
PDN
13
C57
0.1u
8
3
10
74HCU04
5
3
11
U10C
10
5
74HC04
74HC04
13
6
U10E
11
74HC14
U7F
6
4
74HC14
U7E
4
U7C
U2E
U10B
2
74HC04
74HC04
74HCU04
11
1
U7B
U2D
9
12
74HCU04
2
A
U7A
U2F
2
74HCU04
1
3
L
11
U10D
12
74HC04
9
8
74HC14
10
A
74HC14
U10A
1
Title
2
74HC14
Size
A3
Date:
A
DIR_SDTI
DIR
U5E
8
B
C
D
AKD4634-A
Document Number
Rev
LOGIC
Monday, February 26, 2007
0
Sheet
E
5
of
5