ASAHI KASEI [AKD5702-A] AKD5702-A AK5702 Evaluation Board Rev.1 GENERAL DESCRIPTION AKD5702-A is an evaluation board for the portable digital audio 16bit A/D converter with MIC-AMP, AK5702. AKD5702-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD5702-A --- AK5702 Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT with optical output • BNC connector for an external clock input • 10pin Header for serial control interface AVDD 3.0V Regulator 5V DVDD VD AGND DGND Control Data 10pin Header LIN3/4/5 DSP 1 10pin Header MIC3/4/5 RIN3/4/5 AK5702 LIN1/2/5 TDM 10pin Header MIC1/2/5 RIN1/2/5 DSP 2 10pin Header EXT_MCLK EXT_LRCK EXT_BCLK CLOCK GEN AK4114 (DIT) Opt In Opt Out Figure 1. AKD5702-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM086501> 2007 / 04 -1- ASAHI KASEI [AKD5702-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD and VD are supplied from the regulator. (Default) [REG] (Red) [AVDD] (Orange) [DVDD] (Orange) [VD] (Orange) [AGND] (Black) [DGND] (Black) = 5V = open (3.0V, supply from regulator, for AVDD of AK5702) = open (3.0V, supply from regulator, for DVDD of AK5702) = 2.7 ∼ 3.6V (typ. 3.0V, for logic of digital part) = 0V (for analog ground) = 0V (for digital ground) 1-2) When AVDD, DVDD and VD are not supplied from the regulator. [REG] (Red) [AVDD] (Orange) [DVDD] (Orange) [VD] (Orange) [AGND] (Black) [DGND] (Black) = open = 2.4 ∼ 3.6V (typ. 3.0V, for AVDD of AK5702) = 1.6 ∼ 3.6V (typ. 3.0V, for DVDD of AK5702) = 2.7 ∼ 3.6V (typ.3.0V, for logic of digital part) = 0V (for analog ground) = 0V (for digital ground) Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5702 and AK4114 should be reset once by bringing SW1, 2 “L” upon power-up. Evaluation mode In case of AK5702 evaluation using AK4114, same audio interface format should be set for both AK5702 and AK4114. About AK5702’s audio interface format, refer to datasheet of AK5702. About AK4114’s audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) PLL Master Mode (Default) (2) PLL Slave Mode 1 (PLL Reference CLOCK: MCKI pin) (3) PLL Slave Mode 2 (PLL Reference CLOCK: BCLK or LRCK pin) (4) EXT Slave Mode (5) EXT Master Mode <KM086501> 2007 / 04 -2- ASAHI KASEI [AKD5702-A] (1) PLL Master Mode (Default) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKO GND BCLK GND LRCK NC SDTOA NC VD SDTOB a) Set up jumper pins of MCKI clock When using X’tal as MCKI clock, X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set to X1. X’tal of 11.2896MHz (Default) is set on the AKD5702-A. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through a BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XTI) and select EXT on JP7 (MCLK_SEL). JP12 (EXT) and R19 should be properly selected in order to match the output impedance of the clock generator. EXT_MCLK MCKO MCKO 384/768fs EXT JP8 MKFS 1024fs DIT JP32 MCLK_SEL 512fs JP5 TDMMCLK_SEL EXT_MCLK MCKO EXT_MCLK JP7 MCKI_SEL 256fs XTI 384fs-768 JP16 *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. b) Set up jumper pins of BCLK clock Output frequency (32fs/64fs) of BCLK should be set by “BCKO1-0 bit” in the AK5702. There is no necessity for set up JP9(BCLKFS). JP28 M/S JP10 BCLK_SEL BNC_BCLK BCLKFS DIT 32fs 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS c) Set up jumper pins of LRCK clock BNC_LRCK DIT <KM086501> LRCKFS JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 JP11 LRCKFS 2007 / 04 -3- ASAHI KASEI [AKD5702-A] d) Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (2) PLL Slave Mode 1 (PLL Reference CLOCK: MCKI pin) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI BCLK GND GND LRCK NC SDTOA NC VD SDTOB a) Set up jumper pins of MCKI clock X’tal of 11.2896MHz (Default) is set on the AKD5702-A. In this case, the AK5702 corresponds to PLL reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5702 is supplied to a divider (U3: 74VHC4040), EXT_BCLK and EXT_LRCK clocks are generated by the divider. Then “MCKO bit” in the AK5702 should be set to “1”. When an external clock is supplied through a BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XTI) and select EXT on JP7 (MCKI_SEL). JP12 (EXT) and R19 should be properly selected in order too match the output impedance of the clock generator. b) Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS MCKO 384/768fs JP10 BCLK_SEL <KM086501> BNC_BCLK BCLKFS DIT 32fs S 64fs-384 M EXT_MCLK 1024fs MCKO JP8 MKFS 256fs EXT 64fs DIT JP32 MCLK_SEL 512fs MCKI_SEL EXT_MCLK MCKO EXT_MCLK JP5 TDMMCLK_SEL 384fs-768 XTI JP7 32fs-384 JP16 2007 / 04 -4- ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock LRCKFS DIT BNC_LRCK JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 JP11 LRCKFS d) Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (2-a) In the case of using AK4114. * In this mode, MCLK of AK5702 should be supplied from J1 (EXT_MCKI), and X1 should be open. This mode is BCLK=64fs, LRCK=1fs only. Set up jumper pins of MCKI clock MCKO EXT_MCLK MCKO EXT JP8 MKFS 384/768fs DIT EXT_MCLK MCKO EXT_MCLK JP32 MCLK_SEL 1024fs JP5 TDMMCLK_SEL 512fs JP7 MCKI_SEL 256fs XTI 384fs-768 JP16 *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. Set up jumper pins of BCLK clock JP28 M/S JP10 BCLK_SEL BNC_BCLK BCLKFS DIT 32fs BNC_LRCK DIT <KM086501> LRCKFS JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 Set up jumper pins of LRCK clock JP11 LRCKFS 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS 2007 / 04 -5- ASAHI KASEI [AKD5702-A] Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (3) PLL Slave Mode 2 (PLL Reference CLOCK: BCLK or LRCK pin) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI BCLK GND GND LRCK NC SDTOA NC VD SDTOB a) Set up jumper pins of MCKI clock EXT_MCLK MCKO MCKO 384/768fs EXT JP8 MKFS 1024fs DIT JP32 MCLK_SEL 512fs MCKI_SEL EXT_MCLK MCKO EXT_MCLK JP5 TDMMCLK_SEL 256fs XTI JP7 384fs-768 JP16 b) Set up jumper pins of BCLK clock When an external clock is supplied through a BNC connector J2 (EXT/BCLK), J3 (EXT/LRCK), JP14 (EXT1) and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock generator. JP28 M/S JP10 BCLK_SEL <KM086501> BNC_BCLK BCLKFS DIT 32fs 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS 2007 / 04 -6- ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock LRCKFS DIT BNC_LRCK JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 JP11 LRCKFS d) Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (4) EXT Slave Mode * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. In this mode, MCKI, BCLK and LRCK should be supplied from PORT4. PORT4 MCKI BCLK GND GND LRCK NC SDTOA NC VD SDTOB a) Set up jumper pins of MCKI clock EXT_MCLK MCKO MCKO 384/768fs EXT JP8 MKFS 1024fs DIT JP32 MCLK_SEL 512fs JP5 TDMMCLK_SEL EXT_MCLK MCKO EXT_MCLK JP7 MCKI_SEL 256fs XTI 384fs-768 JP16 b) Set up jumper pins of BCLK clock JP28 M/S JP10 BCLK_SEL <KM086501> BNC_BCLK BCLKFS DIT 32fs 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS 2007 / 04 -7- ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock LRCKFS DIT BNC_LRCK JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 JP11 LRCKFS d) Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (4-a) In the case of using AK4114. *This mode is BCLK=64fs, LRCK=1fs only. The setting of JP16(XTI) is open, the clock of AK4114 use X’tal of X1. The signal of MCKO, BCLK and LRCK outputted from AK4114 is inputted into AK5702. Set up jumper pins of MCKI clock EXT_MCLK MCKO MCKO 384/768fs EXT JP8 MKFS 256fs DIT EXT_MCLK MCKO EXT_MCLK JP32 MCLK_SEL 1024fs JP5 TDMMCLK_SEL MCKI_SEL 512fs JP7 XTI 384fs-768 JP16 *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. Set up jumper pins of BCLK clock JP28 M/S JP10 BCLK_SEL <KM086501> BNC_BCLK BCLKFS DIT 32fs 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS 2007 / 04 -8- ASAHI KASEI [AKD5702-A] LRCKFS DIT BNC_LRCK JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 Set up jumper pins of LRCK clock JP11 LRCKFS Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B (5) EXT Master Mode * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. In this mode, MCKI should be supplied from PORT4, but BCLK and LRCK should not be supplied. PORT4 MCKI BCLK GND GND LRCK NC SDTOA NC VD SDTOB a) Set up jumper pins of MCKI clock EXT_MCLK MCKO MCKO 384/768fs EXT JP8 MKFS 1024fs DIT JP32 MCLK_SEL 512fs JP5 TDMMCLK_SEL EXT_MCLK MCKO EXT_MCLK JP7 MCKI_SEL 256fs XTI 384fs-768 JP16 *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. b) Set up jumper pins of BCLK clock JP28 M/S JP10 BCLK_SEL <KM086501> BNC_BCLK BCLKFS DIT 32fs 64fs 32fs-384 S 64fs-384 M JP9 BCLKFS 2007 / 04 -9- ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock BNC_LRCK DIT LRCKFS JP13 LRCK_SEL 1fs 2fs 1fs-384 2fs-384 JP11 LRCKFS d) Set up jumper pins of SDTO JP30 SDTO_SEL A JP29 SDTOB B DIP Switch set up [SW1] (MODE): Mode Setting of AK4114 ON is “H”, OFF is “L”. No. 1 2 3 4 5 6 7 Name I2S M/S OCKS0 OCKS1 CAD1 CAD0 TEST 8 I2C ON (“H”) OFF (“L”) AK4114 Audio Format Setting See Table 2 Master Clock Frequency Select See Table 3 Chip Address pin “L” µp Control Mode Select pin “H”: I2C, “L”: 3-wire serial Table 1. Mode Setting Resistor for AK5702 M/S 0 0 1 1 Set up for AK4114 SW1 DIF1 DIF0 DIF1 DIF0 DAUX 1 0 0 0 24bit, Left justified Master 1 1 0 1 24bit, I2S Master 1 0 1 0 24bit, Left justified Slave 1 1 1 1 24bit, I2S Slave Table 2. Setting for AK5702 and AK4114 Audio Interface Format No. 0 2 OCKS1 0 1 OCKS0 0 0 MCKO1 256fs 512fs X’tal 256fs 512fs Default Default Table 3. Master Clock Frequency Select for AK4114 (Stereo mode) <KM086501> 2007 / 04 - 10 - ASAHI KASEI [AKD5702-A] Other jumper pins set up 1. JP1, JP3 (MPWRB) : Connect to MPWRB OPEN : No connect <Default> SHORT : Connect to MPWRB 2. JP2, JP4 (MPWRA) OPEN SHORT : Connect to MPWRA : No connect <Default> : Connect to MPWRA 3. JP17 (LIN125_SEL) LIN1 LIN2 LIN5 : Select input pin from J4 : Enable to input to LIN1 from J4 <Default> : Enable to input to LIN2 from J4 : Enable to input to LIN5 from J4 4. JP18 (RIN125_SEL) RIN1 RIN2 RIN5 : Select input pin from J6 : Enable to input to RIN1 from J6 <Default> : Enable to input to RIN2 from J6 : Enable to input to RIN5 from J6 5. JP19 (LIN5_SEL) LIN125 LIN345 : Select input connecter to LIN5 : Enable to input to LIN5 from J4 <Default> : Enable to input to LIN5 from J7 6. JP20 (RIN5_SEL) RIN125 RIN345 : Select input connecter to RIN5 : Enable to input to RIN5 from J6 <Default> : Enable to input to RIN5 from J9 7. JP21 (LIN345_SEL) LIN3 LIN4 LIN5 : Select input pin from J7 : Enable to input to LIN3 from J7 <Default> : Enable to input to LIN4 from J7 : Enable to input to LIN5 from J7 8. JP22 (RIN345_SEL) RIN3 RIN4 RIN5 : Select input pin from J9 : Enable to input to RIN3 from J9 <Default> : Enable to input to RIN4 from J9 : Enable to input to RIN5 from J9 9. JP35 (SDTOB_SEL) : Select input pin to TDMIN PDOWN : Connect to GND <Default> SDTOB : Connect to SDTOB 10. JP36 (CTRL_SEL) : Select for µp Control Mode 3-WIRE : Select to 3-WIRE <Default> I2C : Select to I2C 11. JP37 (GND) OPEN SHORT : Analog ground and Digital ground : Separated. <Default> : Common. (The connector “DGND” should be open.) 12. JP38 (AVDD_SEL) : AVDD of the AK5702 REG : AVDD is supplied from the regulator (“AVDD” jack should be open). < Default > AVDD : AVDD is supplied from “AVDD ” jack. <KM086501> 2007 / 04 - 11 - ASAHI KASEI [AKD5702-A] 13. JP39 (DVDD_SEL) : DVDD of the AK5702 AVDD : DVDD is supplied from “AVDD”. < Default > DVDD : DVDD is supplied from “DVDD ” jack. 14. JP40 (LVC_SEL) DVDD VD : Supply line selection of Logic block of LVC. : Logic block of LVC is supplied from “DVDD”. < Default > : Logic block of LVC is supplied from “VD ” jack. The function of the toggle SW [SW2] (PDN): Power control of AK5702. Keep “H” during normal operation. [SW3] (DIT): Power control of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK5702 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10-wire flat cable packed with the AKD5702-A CSN Connect CCLK CDTI PC AKD5702-A 10 Wire Flat Cable 10pin Connector 10pin Header Figure 2. Connect of 10 wire flat cable <KM086501> 2007 / 04 - 12 - ASAHI KASEI [AKD5702-A] Analog Input / Output Circuits (1) Input Circuits a) LIN, RIN, MIC Input Circuit R24 (Open) J4 LIN125 JP17 2 3 1 LIN1 LIN1 LIN2 LIN2 LIN125_SEL LIN5 MR-552LS J5 MIC125 6 4 3 J6 RIN125 JP18 2 3 1 RIN1 RIN1 RIN2 RIN2 RIN125_SEL RIN5 MR-552LS JP19 LIN5_SEL R25 (Open) LIN5 JP20 RIN5_SEL RIN5 R26 (Open) J7 LIN345 JP21 2 3 1 LIN3 LIN3 LIN4 LIN4 LIN345_SEL LIN5 MR-552LS J8 MIC345 6 4 3 J9 RIN345 JP22 2 3 1 RIN3 RIN3 RIN4 RIN4 RIN345_SEL RIN5 MR-552LS R27 (Open) Figure 3. LIN, RIN, MIC Input Circuit ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM086501> 2007 / 04 - 13 - ASAHI KASEI [AKD5702-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD5702-A according to previous term. 2. Connect IBM-AT compatible PC with AKD5702-A by 10-line type flat cable (packed with AKD5702-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK5702 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd5702-a.exe” to set up the control program. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK5702. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM086501> 2007 / 04 - 14 - ASAHI KASEI [AKD5702-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL There are dialogs corresponding to register of 18h and 19h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK5702 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. <KM086501> 2007 / 04 - 15 - ASAHI KASEI [AKD5702-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK5702. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM086501> 2007 / 04 - 16 - ASAHI KASEI [AKD5702-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The following is displayed. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 1. [F3] window <KM086501> 2007 / 04 - 17 - ASAHI KASEI [AKD5702-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM086501> 2007 / 04 - 18 - ASAHI KASEI [AKD5702-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 3. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM086501> 2007 / 04 - 19 - ASAHI KASEI [AKD5702-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM086501> 2007 / 04 - 20 - ASAHI KASEI [AKD5702-A] Figure 5. [F5] window (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM086501> 2007 / 04 - 21 - ASAHI KASEI [AKD5702-A] Revision History Date 2006/11/28 2007/04/09 Manual Revision KM086500 KM086501 Board Revision 0 1 Reason First Edition Error Correct Circuit Change Contents P2. Operation Sequence 1) Set up the power supply lines 1-1) Add (default) to the end of sentence. AVDD: open Æ open (3.0V, supply from regulator, for AVDD of AK5702) DVDD: open Æ open (3.0V, supply from regulator, for DVDD of AK5702) VD: for logic Æ (typ 3.0V, for logic of digital part) 1-2) “REG” jack should be open Æ open AVDD: for AVDD of AK5702 (typ.3.0V)Æ (typ.3.0V, for AVDD of AK5702) DVDD: for DVDD of AK5702 (typ.3.0V)Æ (typ.3.0V, for DVDD of AK5702) VD: for logic Æ (typ 3.0V, for logic of digital part) P2. Evaluation Mode Applicable Evaluation Mode (1) Evaluation of PLL, Master Mode Æ PLL Master Mode (2) Evaluation of PLL, Slave Mode Æ PLL Slave Mode 1 (3) Evaluation of PLL, Slave Mode Æ PLL Slave Mode 2 (4) Evaluation of EXT, Slave Mode Æ EXT Slave Mode (5) EXT, Master Mode Æ EXT Master Mode P3-P10 (1) Evaluation of PLL, Master Mode Æ PLL Master Mode a) Set up jumper pins of MCKI clock (J1: EXT_MCKI) Æ J1 (EXT_MCKI) JP8 Æ JP8 (MKFS) b) Set up jumper pins of BCLK clock JP9 Æ JP9 (BCLKFS) (2) Evaluation of PLL, Slave Mode Æ PLL Slave Mode 1 a) Set up jumper pins of MCKI clock (J1: MCLK_SEL) Æ J1 (EXT_MCKI) (2-a) In the case of using AK4114 J1 Æ J1 (EXT_MCLK) JP8 Æ JP8 (MKFS) (3) Evaluation of PLL, Slave Mode Æ PLL Slave Mode 2 (4) Evaluation of EXT, Slave Mode Æ EXT Slave Mode Connect PORT4 (DSP1) with DSP In this mode, BCLK and LRCK should be supplied from PORT4, but MCKI should not be supplied. Æ In this mode, MCKI, BCLK and LRCK should be supplied from PORT4. (4-a) In the case of using AK4114 JP16 Æ JP16 (XTI) JP8 Æ JP8 (MKFS) (5) EXT, Master Mode Æ EXT Master Mode a) Set up jumper pins of MCKI clock JP8 Æ JP8 (MKFS) b) Set up jumper pins of BCLK clock The direction of jumper setup of JP28 (M/S): S (Slave) Æ M (Master) P11. Other jumper pins set up 12. JP38 (AVDD_SEL) OPENÆREG SHORTÆAVDD Resistance value, Capacitance Value Change: MCKI: R13: 51ÆR100:100, C100: OpenÆ22p BICK: R101: ShortÆ100, C101: OpenÆ22p LRCK: R102: ShortÆ100, C102: OpenÆ22p <KM086501> 2007 / 04 - 22 - ASAHI KASEI [AKD5702-A] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM086501> 2007 / 04 - 23 - D E LIN1 RIN1 LIN5 LIN4 LIN3 RIN5 C RIN4 B RIN3 A CN4 32pin_4 25 26 27 28 29 30 31 E 32 E MPWAR R4 2.2k JP4 MPWAR R6 2.2k R7 (open) R8 (open) 1u C6 1u C7 1u 1 C5 1 1u 1 C4 1 1 1 + 1 + + 1 1u + C3 + 1u + C2 + 1u + C1 2 JP2 MPWBR 2 MPWBR JP3 2 JP1 2.2k 2 2.2k R5 2 R3 2 (open) 2 (open) R2 2 R1 C8 1u 25 LIN1 RIN1 26 CN3 C9 1 1 3 4 4 PDN CAD0 AK5702 C 5 1 + C15 10u C16 0.1u 6 7 LRCK I2C MCKI 24 RIN2 1 2 23 LIN2 C13 (open) R11 C14 10k 4.7n 22 21 21 20 19 20 CSN AVDD C18 + 10u 19 R12 51 R100 100 18 17 C100 22p 18 I2C 17 5702_MCKI 32pin_3 16 15 9 22p CCLK BCLK CDTI 8 C102 2 22p 8 32pin_1 1 C 14 C101 TDMIN 100 22 C17 0.1u 13 R102 7 MPWRA VSS1 SDTOA 5702_BCLK 100 23 AVDD VSS2 SDTOB 5702_LRCK R101 6 DVDD 10 5 2 DVDD LIN2 VCOC TEST 51 3 VCOM 12 R10 C12 2 MCKO CAD0 51 24 C10 1u 11 PDN R9 C11 RIN2 + + 2 MPWRB 0.1u 1 2.2u 1u 2 2 1 + 27 LIN5 RIN5 28 29 LIN4 30 RIN4 CN1 LIN3 RIN3 U1 31 D 32 D B B R14 51 R15 51 R16 R17 51 R18 51 16 15 14 13 12 11 10 9 (short) CN2 32pin_2 CSN/CAD1 CCLK/SCL CDTI/SDA 5702_TDMIN TEST 5702_MCKO A 5702_SDTOA 5702_SDTOB A Title Size A3 Date: A B C D AKD5702-A Document Number Rev AK5702 Monday, April 09, 2007 Sheet E 1 1 of 6 A B C D E E E VD D D JP5 EXT_MCLK 384fs-768 EXT_MCLK TDMMCLK_SEL JP6 256fs 128fs JP8 JP7 DIT 4114_MCKO 4 3 2 1 10 11 12 13 EXT J1 EXT_MCKI C 2 3 4 5 MCKI_SEL 1 R19 51 14 7 C19 JP12 EXT 1PR 1CK 1D 1CLR 2PR 2CK 2D 2CLR 1Q 1Q 2Q 2Q TDMBCLK_SEL U3 256fs 512fs 1024fs 384/768fs MCKO U2 5 6 9 8 10 11 CLK RST MKFS 16 VCC GND 8 C20 74AC74 0.1u 0.1u MCKO VDD VSS Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 74HC4040 9 7 6 5 3 2 4 13 12 14 15 1 DIT BCLKFS BNC_BCLK BCLKFS B C21 0.1u CLR RCO LOAD QA ENT QB ENP QC CLK QD A B C D VCC GND 74AC163 JP10 EXT_BCLK BCLK_SEL C 4114_LRCK JP11 2fs-384 1fs-384 2fs 1fs DIT LRCKFS BNC_LRCK JP13 EXT_LRCK LRCK_SEL LRCKFS J2 EXT_BCLK U4 1 9 10 7 2 3 4 5 6 16 8 4114_BICK JP9 64fs-384 32fs-384 64fs 32fs 15 14 13 12 11 U5 1 3 5 9 11 13 14 7 C22 1A 2A 3A 4A 5A 6A VCC GND 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 2 3 4 5 1 R20 51 JP14 EXT B 74HCU04 0.1u J3 EXT_LRCK 2 3 4 5 1 R21 51 JP15 EXT A A Title Size AKD5702-A Document Number A3 Date: A B C D Monday, April 09, 2007 Rev CLOCK Sheet E 1 2 of 6 A B C D E L1 PORT1 1 VCC 3 GND OUT 2 1 C23 0.1u 2 VD (short) TORX141 E E R22 C24 10u 2 1 C25 0.1u VD C26 0.47u SW DIP-8 1 IPS0 2 38 37 INT1 R AVDD 39 40 VCOM 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 RX2 U6 47 16 15 14 13 12 11 10 9 48 1 2 3 4 5 6 7 8 NC D R23 18k SW1 RX3 I2S M/S OCKS0 OCKS1 CAD1 CAD0 TEST I2C VD + 470 DVDD D INT0 36 INT0 NC OCKS0 35 OCKS0 3 DIF0 OCKS1 34 OCKS1 4 TEST2 CM1 33 DIF1 CM0 RP1 OCKS0 OCKS1 CAD1 CAD0 TEST I2C 5 AK4114 47k C 6 7 NC PDN DIF2 XTI 32 VD 31 4114_PDN 30 1 9 8 7 6 5 4 3 2 1 8 29 IPS1 XTO 9 P/SN DAUX 28 10 XTL0 MCKO2 27 XTL1 BICK 11 C28 5p EXT_MCLK MCKO C27 5p 2 X1 11.2896MHz C JP16 XTI DAUX 26 4114_BICK B B LRCK 24 4114_LRCK MCKO1 23 4114_MCKO 22 25 C30 0.1u 2 1 C31 10u + + C29 0.1u 1 DVSS DVDD 21 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 13 TX0 SDTO DVSS VIN TVDD 12 2 C32 10u VD VD PORT2 A IN VCC GND 3 2 1 VD C33 0.1u TOTX141 A Title Size A3 Date: A B C D AKD5702-A Document Number Rev DIT Monday, April 09, 2007 1 Sheet E 3 of 6 A B C D E R24 (Open) E E J4 LIN125 JP17 2 3 1 LIN1 LIN1 LIN2 LIN2 LIN125_SEL LIN5 MR-552LS J5 MIC125 6 4 3 D J6 RIN125 JP18 2 3 1 RIN1 RIN1 RIN2 RIN2 D RIN125_SEL RIN5 MR-552LS JP19 LIN5_SEL R25 (Open) LIN5 JP20 RIN5_SEL RIN5 R26 (Open) C C J7 LIN345 LIN3 LIN3 LIN4 LIN4 JP21 2 3 1 LIN345_SEL LIN5 MR-552LS J8 MIC345 6 4 3 B J9 RIN345 RIN3 RIN3 RIN4 RIN4 JP22 2 3 1 B RIN345_SEL RIN5 MR-552LS R27 (Open) A A Title Size A3 Date: A B C D AKD5702-A Document Number Rev Input Monday, April 09, 2007 1 Sheet E 4 of 6 A B C D E U7 EXT_BCLK 3 EXT_LRCK 4 5 E A1 B1 A2 B2 A3 B3 21 5702_BCLK 20 5702_LRCK LVC C34 19 E VCCA VCCB DIR VCCB 24 10 9 8 7 6 8 9 3A 10 3B 11 4Y 12 7 13 4A 4B 3Y 2Y 6 R-PACK6R 1 VD PORT3 1 2 3 4 5 DSP2 74LVC32 2B 14 R-PACK6R RP3 2A B8 U8 7 6 5 4 3 2 1 15 5 A8 MCKO BCLK LRCK SDTO VCC 4 B7 1Y B6 A7 R28 (open) 16 3 10 A6 17 1B 9 18 1A 7 6 5 4 3 2 1 B5 1 RP2 B4 A5 2 8 A4 VCC 7 GND 6 14 0.1u LVC JP28 2 PORT4 MCKI 1 BCLK 2 LRCK 3 SDTOA4 5 VD D 10 9 8 7 6 M/S 23 C35 0.1u C36 0.1u 11 GND OE GND GND D 22 SDTOB DSP1 12 JP29 R29 10k VD 13 SDTOB U10 74AVC8T245 3 MCKO A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 21 5702_MCKO JP30 DAUX 4 JP32 U9 SDTO_SEL 5 MCLK_SEL 3 EXT_MCLK MCKI1 BCLK2 LRCK3 4 TDMIN VD 5 10 9 8 7 6 4 TDM JP35 SDTOB A1 B1 A2 B2 A3 B3 21 5702_MCKI 6 PORT5 5 C 20 19 18 20 7 19 5702_TDMIN 8 17 C 16 5702_SDTOB 15 5702_SDTOA R30 (open) 6 VD TDMIN P_DOWN SDTOB_SEL CAD1 A4 B4 A5 B5 18 9 JP36 I2C 7 R31 R33 R35 VD R37 100k 10k 10k 10k R32 R34 R36 3-WIRE CTRL_SEL 470 470 470 8 9 PORT6 1 2 3 4 5 10 9 8 7 6 CSN/CAD1 CCLK/SCI CDTI/SDA CDTO/SDA(ACK) A6 B6 A7 B7 17 CSN/CAD1 16 10 10 A8 B8 1 VD 15 14 PDN 2 VCCA VCCB DIR VCCB 24 K A 12 OE GND GND LVC 12 OE GND GND 13 74AVC8T245 B 13 R40 1k C41 0.1u U11 2 1 3 5 9 11 13 14 VD VD VD 0.1u 1A 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 VCC C42 7 GND 74LVC07 K A 22 1 SW2 PDN D2 HSU119 A R41 10k U12 1 3 5 9 11 13 14 7 1 3 INT0 L LVC 23 22 74AVC8T245 H 3 L R39 10k GND VCCB GND C40 0.1u 11 VD D1 HSU119 DIR 24 23 C39 0.1u B VCCB C38 0.1u CTRL 1 VCCA C37 0.1u 11 VD CDTI/SDA CCLK/SCL 2 R38 (short) 14 H C43 0.1u C44 0.1u 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 PDN R42 1k LED1 ERF K A A VD 4114_PDN 74HC14 2 SW3 4114_PDN 1A 2A 3A 4A 5A 6A VCC GND Title Size AKD5702-A Document Number Date: A B C D Rev LOGIC A2 Monday, April 09, 2007 E 1 Sheet 5 of 6 A C GND E REG1 AVDD1 DVDD1 VD1 AGND1 T45_R T45_O T45_O T45_O T45_BK T45_BK AVDD1 47u 1 2 AVDD AVDD1 (short) 1 1 1 VD1 TP1_AGND1 TP1_DGND1 TP2_AGND1 TP2_DGND1 TP3_AGND1 TP3_DGND1 AVDD_SEL 2 D + DVDD1 JP38 REG L2 C48 1 C46 + 47u 1 1 C45 0.1u REG_IN AVDD1 1 DGND1 OUT 2 C47 0.1u E JP37 GND T1 REG_IN TA48M03F IN D 1 E B D AVDD JP39 DVDD1 L3 47u + 2 DVDD DVDD (short) 5.1 DVDD_SEL 2 C49 1 1 R43 AVDD C C JP40 VD1 + 2 LVC VD LVC_SEL 2 47u 1 1 C50 DVDD L4 (short) VD B B A A Title Size A3 Date: A B C D AKD5702-A Document Number Rev 1 POWER Monday, April 09, 2007 Sheet E 6 of 6