[AKD4648-C] AKD4648-C Evaluation board Rev.1 for AK4648 GENERAL DESCRIPTION AKD4648 is an evaluation board for the AK4648, stereo CODEC with MIC/HP/SPK amplifier. The AKD4648 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The AKD4648 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4648 --- Evaluation board for AK4648 (Cable, USB interface board for connecting with USB port, and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • 10pin Header for digital audio interface • 10pin Header for serial control mode TVDD Regulator VCC 3.3 V HVDD AVDD DVDD D3V TVDD MIC PORT1 DIR Opt In MIN AK4115 LINE IN DIT Opt out PORT2 AK4648 HP DSP 10pin Header LINE OUT PORT3 SPK Control Data 10pin Header PORT4 AGND Figure 1. AKD4648-C Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM088701> 2007/04 -1- [AKD4648-C] Evaluation Board Manual Operation sequence (1) Set up the power supply lines. (1-1) In case of using the regulator. (1-1-1) TVDD is supplied from the regulator. Set up the jumper pins. JP22 JP REG_SEL State REG JP23 TVDD_SEL Short Set up the power supply lines. [VCC] (red) = 4.3 ~ 5.0V : typ. 4.5V for regulator and HVDD of AK4648 (regulator 3.3V output : AVDD, DVDD and TVDD of the AK4648 and logic) [TVDD] (orange) = Open [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground (1-1-2) TVDD is supplied from the power supply connector of “TVDD”. Set up the jumper pins. JP22 JP REG_SEL State REG JP23 TVDD_SEL Open Set up the power supply lines. [VCC] (red) = 4.3 ~ 5.0V : typ. 4.5V for regulator and HVDD of AK4648 (regulator 3.3V output : AVDD and DVDD of the AK4648 and logic) [TVDD] (orange) = 1.6 ~ 3.6V : typ. 3.3V for TVDD of AK4648 (TVDD ≤ DVDD) [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground (1-2) When the regulator is not used. Set up the jumper pins. JP22 JP REG_SEL State VCC JP23 TVDD_SEL Open Set up the power supply lines. [VCC] (red) = 2.6 ~ 3.6V [TVDD] (orange) = 1.6 ~ 3.6V [AGND] (black) = 0V [DGND] (black) = 0V : typ. 3.3V for AVDD, DVDD and HVDD of AK4648 and logic : typ. 3.3V for TVDD of AK4648 (TVDD ≤ DVDD) : for analog ground : for logic ground * Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) (3) Power on. The AK4648 and AK4115 should be reset once bringing SW1 (PDN) “L” upon power-up. <KM088701> 2007/04 -2- [AKD4648-C] Evaluation mode In case of AK4648 evaluation using AK4115, it is necessary to correspond to audio interface format for AK4648 and AK4115. About AK4648’s audio interface format, refer to datasheet of AK4648. About AK4115’s audio interface format, refer to Table 2 on page 11 in this manual. Sampling frequency (fs) of AK4115 is 22kHz or more. If the fs is slower than 22kHz, please use other mode. In addition, MCLK of AK4115 supports 256fs and 512fs. When evaluating it in a condition except this, please use other mode. (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4115 (1-2) Evaluation of D/A using DIR of AK4115 (1-3) Evaluation of Loop-back using AK4115 <Default> (1-4) All interface signals are fed externally (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4115 (2-2) Evaluation of D/A using DIR of AK4115 (2-3) Evaluation of Loop-back using AK4115 (2-4) All interface signals are fed externally (3) PLL Slave Mode (3-1) Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4115 (3-1-2) Evaluation of Loop-back using AK4115 (3-1-3) All interface signals are fed externally (3-2) Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4115 (3-2-2) Evaluation of D/A using DIR of AK4115 (3-2-3) Evaluation of Loop-back using AK4115 (3-2-4) All interface signals are fed externally (4) PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4115 (4-2) Evaluation of Loop-back using AK4115 (4-3) All interface signals are fed externally <KM088701> 2007/04 -3- [AKD4648-C] (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X’tal) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master (1-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP21 SDTI DIR ADC (1-3) Evaluation of Loop-back using AK4115 <Default> X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP21 SDTI DIR ADC (1-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set follows. JP20 SDTO-IN JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master <KM088701> JP21 SDTI DIR ADC 2007/04 -4- [AKD4648-C] (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and X1 (X’tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master (2-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP21 SDTI DIR ADC (2-3) Evaluation of Loop-back using AK4115 X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP21 SDTI DIR ADC (2-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as follows. JP20 SDTO-IN JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master <KM088701> JP21 SDTI DIR ADC 2007/04 -5- [AKD4648-C] (3) PLL Slave Mode (3-1) Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be input to AK4115’s XTI. X’tal oscillator should be removed from X1. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC (3-1-2) Evaluation of Loop-back using AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1 (DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. MCKO of AK4648 should be input to AK4115’s XTI. X’tal oscillator should be removed from X1. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC (3-1-3) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). BICK and LRCK inputs should be synchronized with MCKO of AK4648. MCLK (PLL reference clock), BICK, LRCK and SDTI are supplied from PORT3. The JP14 (4115_MCKI)’s lower side (MCKO of AK4648) should be connected to MCLK of DSP. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC <KM088701> 2007/04 -6- [AKD4648-C] (3-2) Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4115 X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC (3-2-2) Evaluation of D/A using DIR of AK4115 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC (3-2-3) Evaluation of Loop-back using AK4115 X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT), and PORT3 (DSP). The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC <KM088701> 2007/04 -7- [AKD4648-C] (3-2-4) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). BICK, LRCK, and SDTI are supplied from PORT3. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN DIR ADC JP2 VCOC RIN3 (4) JP21 SDTI PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4115 PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP. X’tal oscillator should be removed from X1. In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP20 SDTO_IN JP2 JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master RIN3 JP21 SDTI DIR ADC VCOC (4-2) Evaluation of Loop-back PORT2 (DIT) and PORT3 (DSP) are used. Nothing should be connected to PORT1(DIR). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP. X’tal oscillator should be removed from X1. The jumper pins should be set as follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC <KM088701> 2007/04 -8- [AKD4648-C] (4-3) All interface signals are fed externally PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The system clock (PLL reference clock) should be connected to MCLK of PORT3. In case of supplying MCKO to DSP, the JP14 (4115_MCKI)’s lower side should be connected to MCLK of DSP. X’tal oscillator should be removed from X1. The jumper pins should be set as the follows. JP14 4115_MCKI JP15 DIR_MCLK JP16 BICK JP17 LRCK JP19 DIR_SEL Slave Master JP20 SDTO_IN JP21 SDTI DIR ADC JP2 RIN3 VCOC <KM088701> 2007/04 -9- [AKD4648-C] DIP Switch set up [S1] (SW DIP1-4): Mode setting for AK4648 and AK4115. No. 1 2 3 4 Name CAD0 OCKS1 DIF0 DIF1 ON (“H”) OFF (“L”) AK4648 Chip Address Setting: (See Table 4) AK4115 Master Clock Setting: (See Table 3) AK4115 Audio Format Setting See Table 2 Default OFF OFF OFF OFF Table 1. Mode Setting for AK4648 and AK4115 Mode DIF1 DIF0 1 2 3 4 0 0 1 1 0 1 0 1 DAUX LRCK SDTO 24bit, Left justified 24bit, Left justified H/L O 24bit, I2S 24bit, I2S L/H O 24bit, Left justified 24bit, Left justified H/L I 24bit, I2S 24bit, I2S L/H I Table 2. Setting for AK4115 Audio Interface Format Mode 0 1 OCKS1 0 1 MCKO1 pin 256fs 512fs BICK I/O I/O 64fs 64fs 64-128fs 64-128fs O O I I X’tal 256fs 512fs Table 3. Setting for AK4115 Master Clock <KM088701> 2007/04 - 10 - [AKD4648-C] Other jumper pins set up [JP1] (GND) : Analog ground and Digital ground. SHORT : Common. (The connector “DGND” can be open.) OPEN : Separated. <Default> [JP2] : Selection of RIN3 path or PLL Mode. RIN3 : RIN3 path. VCOC : PLL Mode. <Default> [JP4] (LIN1) : Selection of using MIC-power supply for LIN1. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. <Default> [JP7] (RIN1) : Selection of using MIC-power supply for RIN1. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. <Default> [JP8] (LIN2) : Selection of using MIC-power supply for LIN2. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. <Default> [JP9] (RIN2) : Selection of using MIC-power supply for RIN2. SHORT : MIC-power is supplied. OPEN : MIC-power is not supplied. <Default> [JP12] : Selection of LIN3 path or MIN path. SHORT : LIN3 path. OPEN: MIN path. <Default> [JP14] (4114_MCKI) : AK4115 Clock Source. OPEN : X’tal of AK4115 is used. <Default> SHORT : MCKO of AK4648 (X’tal oscillator should be removed from X1). [JP18] (Signal V_select) : Selection of power supply for logic(U4). D3V : It is supplied from D3V. <Default> TVDD : It is supplied from TVDD. [JP20] (SDTO_IN) : SDTO of PORT3. SHORT : It supply SDTO to PORT3. OPEN : It does not supply SDTO to PORT3. <Default> <KM088701> 2007/04 - 11 - [AKD4648-C] The function of the toggle SW [SW1] (PDN): Power down of AK4648. Keep “H” during normal operation. [SW2] (DIR): Power down of AK4115. Keep “H” during normal operation. Keep “L” when AK4115 is not used. *Upper-side is “H” and lower-side is “L”. Indication for LED [LED1] (ERF): Monitor INT0 pin for the AK4115. LED turns on when some error has occurred to AK4115. Serial Control The AKD4648-C can be connected via the USB port with attached USB interface board. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4648-C. Table 4 shows switch and jumper settings for serial control. Note) When I2C-bus is controlled by µP via PORT4, resistor value of R100 should be properly selected. PORT4 1 for PC Connect USB I/F Board USB Cable 5 10 wire flat cable 10pin Connector 10 SCL SDA 6 AKD4648-C 10pin Header Figure 2. Connect of 10 wire flat cable S1 CAD0 OFF ON Mode I2C CAD0=0 CAD0=1 Default Table 2. Serial Control Setting <KM088701> 2007/04 - 12 - [AKD4648-C] Analog Input/Output Circuits (1) Input Circuits Input Circuits of LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN. J1 LIN1/RIN1 C13 1u 6 RIN1 + 4 3 C15 1u LIN1 + JP4 R12 2.2k LIN1 JP7 R13 2.2k RIN1 JP8 R16 2.2k MPWR LIN2 JP9 R17 2.2k RIN2 J3 LIN2/RIN2 C19 1u 6 RIN2 + 4 3 C20 1u LIN2 + C21 1u J5 MIN/LIN3/RIN3 RIN3 + 6 LIN3 JP12 + 4 3 C22 1u MIN/LIN3 R18 20k C23 1u J8 LIN4/RIN4 RIN4 + 6 LIN4 + 4 3 C25 1u Figure 3. Input circuits LIN1/RIN1, LIN2/RIN2, LIN3/RIN3, LIN4/RIN4, and MIN <KM088701> 2007/04 - 13 - [AKD4648-C] When LIN3/RIN3 paths of AK4648 are used, JP2 and JP12 should be set as follows. AIN3 bit = “1” (Register Address 21H) JP12 LIN3 JP2 RIN3 VCOC When MIN path of AK4648 is used, JP12 should be set as follows. AIN3 bit = “1” (Register Address 21H) JP12 LIN3 When MIC- power output (MPWR pin) of AK4648 is used, JP4 (LIN1) / JP7 (RIN1) and / or JP8 (LIN2) / JP9 (RIN2) should be short. <KM088701> 2007/04 - 14 - [AKD4648-C] (2) Output Circuits (2-1) HP Output Circuit JP3 HPR Cap-less C14 220u R10 + short 6 HPR + 4 3 J2 HP HPL R11 C16 220u C17 0.22u short C18 0.22u JP5 HPL Cap-less HVCM JP6 R14 10 R15 10 GND HVCM Figure 4. HP Output Circuit (2-1-1) Single-ended Mode The jumper pins should be set as follows. JP3 HPR Cap-less JP6 JP5 HPL Cap-less HVCM GND (2-1-2) Pseudo Cap-less Mode The jumper pins should be set as follows. JP3 HPR Cap-less JP5 HPL Cap-less JP6 HVCM GND <KM088701> 2007/04 - 15 - [AKD4648-C] (2-2) LOUT/ROUT Output Circuit + C24 1u 6 ROUT 4 3 + R19 open J7 LOUT/ROUT LOUT 1u C26 JP13 LINEOUT Figure 5. LOUT/ROUT Output Circuit The jumper pins should be set as follows. JP13 LINEOUT <KM088701> 2007/04 - 16 - [AKD4648-C] (2-3) SPK Output Circuit TP1 SPLP J4 6 1 SPLN 1 SPLP JP10 High SPN TP3 SPRP JP11 High SPP J6 6 1 SPRP 4 3 TP2 SPLN 1 SPRN SPK/L SPK/R 4 3 TP4 SPRN Figure 6. SPK Output Circuit (2-3-1) Stereo SPK Mode The jumper pins should be set as follows. JP10 High SPN JP11 High SPP (2-3-2) Mono SPK Mode The jumper pins should be set as follows. JP10 High SPN JP11 High SPP (2-3-3) High Power SPK Mode The jumper pins should be set as follows. JP10 High SPN JP11 High SPP ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM088701> 2007/04 - 17 - [AKD4648-C] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4648-C according to previous term. 2. Connect IBM-AT compatible PC with AKD4648-C by 10-line type flat cable via the USB port with attached USB interface board (packed with AKD4648-C). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4648-C Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD4648.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : [5 Band EQ] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4648. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4648. Set 5-Band Equalizer of AK4648. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM088701> 2007/04 - 18 - [AKD4648-C] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4648 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4648, click [OK] button. If not, click [Cancel] button. <KM088701> 2007/04 - 19 - [AKD4648-C] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4648. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM088701> 2007/04 - 20 - [AKD4648-C] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 7. Window of [F3] <KM088701> 2007/04 - 21 - [AKD4648-C] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 8 opens. Figure 8. [F4] window <KM088701> 2007/04 - 22 - [AKD4648-C] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 9. Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed. 3-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 3-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM088701> 2007/04 - 23 - [AKD4648-C] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 10 opens. Figure 10. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 11. (2) Click [WRITE] button, then the register setting is executed. <KM088701> 2007/04 - 24 - [AKD4648-C] Figure 11. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM088701> 2007/04 - 25 - [AKD4648-C] 8. [Filter Dialog] This dialog can easily set the AK4648’s programmable filter. Figure 12. [Filter] window 8-1. Value input columns on left side [Sampling Rate] [Cut Off Frequency of FIL1] [Cut Off Frequency of FIL3] [Pole Frequency of EQ] [Zero Frequency of EQ] [FIL3 GAIN] [EQ GAIN] Æ Input value of sampling frequency [unit : Hz] <default : 44100> Æ Input value of cut off frequency of FIL1 [unit : Hz] <default : 150> Æ Input value of cut off frequency of FIL3 [unit : Hz] <default : 4000> Æ Input value of pole frequency of EQ [unit : Hz] Æ Input value of zero frequency of EQ [unit : Hz] Æ Input value of gain of FIL3 (0~−10dB) [unit : dB] Æ Input value of gain of EQ (+12~0dB) [unit : dB] 8-2. Check box on left side Check Box FIL1 FIL3 EQ LPF of FIL1 LPF of FIL3 Check FIL1 bit =“1” FIL3 bit =“1” EQ bit =“1” F1AS bit =“1”(LPF) F3AS bit =“1”(LPF) Check off FIL1 bit =“0” FIL3 bit =“0” EQ bit =“0” F1AS bit =“0”(HPF) F3AS bit =“0”(HPF) 8-2. [Register Setting] panel and [Register Setting] button on right side Click [Register setting] button, then filter coefficient set by 8-1 and 8-2 is written on [Register setting] panel. (It is also written to the actual control register of the AK4648.) <KM088701> 2007/04 - 26 - [AKD4648-C] 9. [5 Band EQ Dialog] This dialog can easily set the AK4648’s 5-Band Equalizer. Figure 13. [5 Band EQ] window When the check box of “5 Band EQ” is checked, 5-Band Equalizer is ON (FBEQ bit = ”1”). When the slide button is changed, its value is written to the internal register immediately. <KM088701> 2007/04 - 27 - [AKD4648-C] MEASUREMENT RESULTS [Measurement condition] ● Measurement unit: Audio Precision, System two Cascade Dual Domain ● EXT Slave Mode ● BICK: 64fs ● Bit: 16bit ● Measurement Frequency: <10Hz ∼ 20kHz (ADC) <10Hz ∼ 22kHz (DAC) ● Power Supply: AVDD=DVDD=TVDD=3.3V, HVDD=4.5V ● Temperature: Room ● Input Frequency: 1kHz ● Sampling Frequency: 44.1kHz <KM088701> 2007/04 - 28 - [AKD4648-C] 1. TABLE DATA ADC (LIN2/RIN2) characteristics (IVOL=0dB, ALC = OFF, LIN2/RIN2 Æ ADC Æ IVOL) Parameter Lch [dB] Rch [dB] MIC-Amp Gain 0dB +20dB 0dB +20dB S/(N+D) 20kHzLPF (−1dB) D-range 20kHzLPF + A-weighted S/N 20kHzLPF + A-weighted 88.6 95.2 95.3 83.2 86.5 86.5 88.5 95.2 95.3 83.2 86.5 86.5 DAC (LOUT/ROUT) characteristics (DAC Æ LOUT/ROUT) Parameter Lch [dB] Rch [dB] S/(N+D) 20kHzLPF (−3dB) 87.5 87.4 S/N A-weighted 92.3 92.3 DAC (HP(Single-ended Mode)) characteristics (DAC-->HP(Single-ended Mode)), RL=16Ω Parameter Lch [dB] Rch [dB] S/(N+D) 20kHzLPF (−3dB) (HPG=0dB) 69.4 69.5 S/N A-weighted 91.1 91.1 DAC (HP(Pseudo Cap-less Mode)) characteristics (DAC-->HP(Pseudo Cap-less Mode)), RL=16Ω Parameter Lch [dB] Rch [dB] S/(N+D) 20kHzLPF (−3dB) (HPG=0dB) 64.7 65.0 S/N A-weighted 90.1 90.1 DAC (SP(Stereo)) characteristics (DAC-->SP(Stereo)), RL=8Ω Parameter Lch [dB] Rch [dB] 20kHzLPF (-0.5dBFS) S/(N+D) 61.5 61.6 (SPKG2-0:+4.43dB) S/N A-weighted 90.4 90.3 DAC (SP(High Power Mode)) characteristics (DAC-->SP(High Power Mode)), RL=8Ω Parameter [dB] 20kHzLPF (-0.5dBFS) 61.5 S/(N+D) (SPKG2-0:+4.43dB) S/N A-weighted 91.4 <KM088701> 2007/04 - 29 - [AKD4648-C] 2. PLOT DATA 2-1 ADC (LIN2/RIN2 Æ ADC)(MIC-Amp Gain:+20dB) AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) THD + N vs Input Level, fs=44.1kHz, fin=1kHz -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 14. THD+N vs. Input Level AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) THD + N vs Input Frequency, fs=44.1kHz, -1dB Input -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. THD+N vs. Input Frequency <KM088701> 2007/04 - 30 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) Linearity, fs=44.1kHz, fin=1kHz +0 -5 -10 -15 -20 -25 -30 -35 -40 d B F S -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBr Figure 16. Linearity AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) Frequency Response, fs=44.1kHz, -1dB Input +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k Hz Figure 17. Frequency Response <KM088701> 2007/04 - 31 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, -1dB Input +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 18. FFT Plot (Input level= -1dBFS) AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 19. FFT Plot (Input level= -60dBFS) <KM088701> 2007/04 - 32 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN+20dB) FFT fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 20. FFT Plot (No signal) AK4648 LIN2/RIN2=>ADC (MGAIN+20dB) Crosstalk, fs=44.1kHz, -1dB Input, red R=>L, blue L=>R -70 TTTTTTTTTTT TTTTT T TTT T -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 21. Crosstalk Plot <KM088701> 2007/04 - 33 - [AKD4648-C] 2-2 ADC (LIN2/RIN2 Æ ADC)(MIC-Amp Gain:0dB) AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Level , fs=44.1kHz, fin=1kHz -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBr Figure 22. THD+N vs. Input Level AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) THD + N vs Input Frequency, fs=44.1kHz, -1dB Input -60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 1k 2k Hz Figure 23. THD+N vs. Input Frequency <KM088701> 2007/04 - 34 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Linearity, fs=44.1kHz, fin=1kHz +0 -5 -10 -15 -20 -25 -30 -35 -40 d B F S -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBr Figure 24. Linearity AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Frequency Response, fs=44.1kHz, -1dB Input +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 d B F S -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k Hz Figure 25. Frequency Response <KM088701> 2007/04 - 35 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, -1dB Input +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 26. FFT Plot (Input level= -1dBFS) AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 27. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 36 - [AKD4648-C] AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) FFT fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 28. FFT Plot ( No signal ) AK4648 LIN2/RIN2 => ADC (MGAIN 0dB) Crosstalk, fs=44.1kHz, -1dB Input, red R=>L, blue L=>R -70 TTTT -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k Hz Figure 29. Crosstalk Plot <KM088701> 2007/04 - 37 - [AKD4648-C] 2-3 DAC (DACÆ LOUT/ROUT) AK4648 DAC => LINEOUT THD + N vs Input Level , fs=44.1kHz, fin=1kHz -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 30. THD+N vs. Input Level AK4648 DAC => LINEOUT THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 31. THD+N vs. Input Frequency <KM088701> 2007/04 - 38 - [AKD4648-C] AK4648 DAC => LINEOUT Linearity, fs=44.1kHz, fin=1kHz +0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBFS Figure 32. Linearity AK4648 DAC => LINEOUT Frequency Response, fs=44.1kHz, 0dB Input +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r -0.4 -0.6 A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k Hz Figure 33. Frequency Response <KM088701> 2007/04 - 39 - [AKD4648-C] AK4648 DAC => LINEOUT FFT, fs=44.1kHz, 0dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 34. FFT Plot (Input level= 0dBFS) AK4648 DAC => LINEOUT FFT, fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 35. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 40 - [AKD4648-C] AK4648 DAC => LINEOUT FFT, fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 36. FFT Plot (No signal) AK4648 DAC => LINEOUT Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R -80 TTT TTTT T -82 -84 -86 -88 -90 -92 -94 -96 -98 d B -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 20 50 100 200 500 1k 2k Hz Figure 37. Crosstalk Plot <KM088701> 2007/04 - 41 - [AKD4648-C] 2-4 DAC (DACÆHP(Single-ended Mode))(HPG=0dB) AK4648 DAC =>HP (Single-end) THD + N vs Input Level , fs=44.1kHz, fin=1kHz -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 38. THD+N vs. Input Level AK4648 DAC =>HP (Single-end) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 39. THD+N vs. Input Frequency <KM088701> 2007/04 - 42 - [AKD4648-C] AK4648 DAC => HP (Single-end) Linearity, fs=44.1kHz, fin=1kHz +0 T -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 16k 18k 20k dBFS Figure 40. Linearity AK4648 DAC => HP (Single-end) Frequency Response, fs=44.1kHz, 0dB Input +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r -0.4 -0.6 A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 2k 4k 6k 8k 10k 12k 14k Hz Figure 41. Frequency Response <KM088701> 2007/04 - 43 - [AKD4648-C] AK4648 DAC =>HP (Single-end) FFT, fs=44.1kHz, 0dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 42. FFT Plot (Input level= 0dBFS) AK4648 DAC => HP (Single-end) FFT, fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 43. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 44 - [AKD4648-C] AK4648 DAC => HP (Single-end) FFT, fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 44. FFT Plot (No signal) AK4648 DAC =>HP (Single-end) Crosstalk, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 -65 -70 -75 d B -80 -85 -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k Hz Figure 45. Crosstalk Plot <KM088701> 2007/04 - 45 - [AKD4648-C] 2-5 DAC (DACÆHP(Pseudo Cap-less Mode))(HPG=0dB) AK4648 DAC =>HP (Pseudo Cap-less) THD + N vs Input Level, fs=44.1kHz, fin=1kHz -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 46. THD+N vs. Input Level <KM088701> 2007/04 - 46 - [AKD4648-C] AK4648 DAC =>HP (Pseudo Cap-less) THD + N vs Input Frequencyl, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 47. THD+N vs. Input Frequency (Non invert signal input) AK4648 DAC => HP (Pseudo Cap-less) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k Hz Figure 48. THD+N vs. Input Frequency (Invert signal input) <KM088701> 2007/04 - 47 - [AKD4648-C] AK4648 DAC => HP (Pseudo Cap-less) Linearity, fs=44.1kHz, fin=1kHz +0 T -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBFS Figure 49. Linearity AK4648 DAC => HP (Pseudo Cap-less) Frequency Response, fs=44.1kHz, 0dB Input +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r -0.4 -0.6 A -0.8 -1 -1.2 -1.4 -1.6 -1.8 20 50 100 200 500 1k 2k Hz Figure 50. Frequency Response <KM088701> 2007/04 - 48 - [AKD4648-C] AK4648 DAC =>HP (Pseudo Cap-less) FFT, fs=44.1kHz, 0dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 51. FFT Plot (Input level= 0dBFS) AK4648 DAC => HP (Pseudo Cap-less) FFT, fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 52. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 49 - [AKD4648-C] AK4648 DAC => HP (Pseudo Cap-less) FFT, fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 53. FFT Plot (No signal) AK4648 DAC=>HP (Pseudo Cap-less) Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R +0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 54. Crosstalk Plot <KM088701> 2007/04 - 50 - [AKD4648-C] 2-6 DAC (DAC-->SP(Stereo))(SPKG2-0:+4.43dB) AK4648 DAC =>SPK (stereo) THD + N vs Input Level, fs=44.1kHz, fin=1kHz -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 55. THD+N vs. Input Level AK4648 DAC =>SPK (stereo) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 56. THD+N vs. Input Frequency <KM088701> 2007/04 - 51 - [AKD4648-C] AK4648 DAC =>SPK (stereo) Linearity, fs=44.1kHz,fin=1kHz +0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBFS Figure 57. Linearity AK4648 DAC =>SPK (stereo) Frequency Response, fs=44.1kHz, 0dB Input +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r -0.4 -0.6 A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k Hz Figure 58. Frequency Response <KM088701> 2007/04 - 52 - [AKD4648-C] AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, 0dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 59. FFT Plot (Input level= 0dBFS) AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 60. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 53 - [AKD4648-C] AK4648 DAC =>SPK (stereo) FFT, fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 61. FFT Plot (No signal) AK4648 DAC =>SPK (stereo) Crosstalk, fs=44.1kHz, 0dB Input, red R=>L, blue L=>R -70 TTT T T -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 -92.5 d B -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 20 50 100 200 500 1k 2k Hz Figure 62. Crosstalk Plot <KM088701> 2007/04 - 54 - [AKD4648-C] AK4648 DAC =>SPK (stereo) Level (W) vs Amplitude Lch Green, Rch Yellow, THD + N vs Amplitude Lch Red, Rch Blue d B +0 1.2 -10 1.1 -20 1 -30 .9 -40 800m -50 700m -60 600m W -70 500m -80 400m -90 300m -100 200m -110 100m -120 -60 0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dBFS Figure 63. THD+N & Output Power vs. Input Level (SPKG=+12.65dB) <KM088701> 2007/04 - 55 - [AKD4648-C] 2-7 DAC (DAC-->SP(High Power Mode))(SPKG2-0:+4.43dB) AK4648 DAC =>SPK (High power) THD + N vs Input Level, fs=44.1kHz, fin=1kHz -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 66. THD+N vs. Input Level AK4648 DAC =>SPK (High power) THD + N vs Input Frequency, fs=44.1kHz, 0dB Input -40 -45 -50 -55 -60 d B r A -65 -70 -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 67. THD+N vs. Input Frequency <KM088701> 2007/04 - 56 - [AKD4648-C] AK4648 DAC =>SPK (High power) Linearity, fs=44.1kHz, fin=1kHz +0 -5 -10 -15 -20 -25 -30 -35 -40 d B r A -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 5k 10k 20k dBFS Figure 68. Linearity AK4648 DAC =>SPK (High power) Frequency Response, fs=44.1kHz, 0dB Input +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 d B r -0.4 -0.6 A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k Hz Figure 69. Frequency Response <KM088701> 2007/04 - 57 - [AKD4648-C] AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, 0dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 70. FFT Plot (Input level= 0dBFS) AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, -60dB Input +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k Hz Figure 71. FFT Plot (Input level = -60dBFS) <KM088701> 2007/04 - 58 - [AKD4648-C] AK4648 DAC =>SPK (High power) FFT, fs=44.1kHz, No Signal +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 72. FFT Plot (No signal) AK4648 DAC =>SPK (High power) Level (W) vs Amplitude Green THD + N vs Amplitude Red d B +0 1.2 -10 1.1 -20 1 -30 .9 -40 800m -50 700m -60 600m W -70 500m -80 400m -90 300m -100 200m -110 100m -120 -60 0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dBFS Figure 73. THD+N & Output Power vs. Input Level (SPKG=+12.65dB) <KM088701> 2007/04 - 59 - [AKD4648-C] Revision History Date (YY/MM/DD) Manual Revision Board Revision 07/03/19 KM088700 0 07/04/13 KM088701 1 Reason First Edition Parts Change Contents AK4648 Rev.A → Rev.B IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei EMD Corporation (EMD) sales office or authorized distributor concerning their current status. • EMD assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • EMD products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and EMD assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of EMD. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an EMD product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold EMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM088701> 2007/04 - 60 - SDTO JP1 GND DGND C3 4.7n F2 51 R4 AGND SDTO HPR D2 SDTI MUTET D1 LRCK AVDD C7 LIN3/MIN C6 MIN/LIN3 LIN2/IN2+ C5 LIN2 RIN4/IN4- C4 HVCM C2 VSS2 C1 VCOM B7 RIN2/IN2- B6 NC E5 NC E4 NC AGND G6 G5 C6 1u + R6 51 LRCK R7 51 G4 BICK G3 MCKO BICK R8 MCKO 51 D AGND F3 E7 RIN3/VCOC DVDD E6 E3 E2 E1 VSS3 PDN D6 LIN1/IN1- G7 D7 VSS1 R5 51 51 R3 TVDD JP2 HPL U1 R1 10k VCOC R2 51 MCKI C5 0.1u D3 C4 10u + C MCKI RIN3 RIN3 DVDD SDTI 1 C2 0.1u F1 C1 10u MPWR + 2 G2 TVDD G1 NC AK4648 HPR C7 0.1u + TVDD LIN1 D MPWR 3 PDN 4 HPL 5 C8 10u C AVDD RIN4 HVCM C9 0.1u C10 2.2u B NC RIN2 D5 NC D4 LOUT/LOP B5 SPRN B4 VSS2 B3 SPLP B2 SPLN B1 HVDD NC A2 A1 SDA TEST SDA A7 F4 RIN1 LIN4/IN4+ RIN1/IN1+ A6 F5 ROUT/LON SCL A5 F6 A4 SCL CAD0 + R9 51 B F7 SPRP AGND CAD0 AGND HVDD + C11 10u C12 0.1u AGND A A LOUT SPRN SPLP SPLN LIN4 AGND ROUT SPRP Title Size B Date: 5 4 3 2 AKD4648-C Document Number Rev 1 AK4648 Friday, March 30, 2007 Sheet 1 1 of 5 A B C D E JP3 HPR Cap-less J1 LIN1/RIN1 C13 1u 6 C14 220u RIN1 short 6 HPR C15 1u LIN1 J2 HP 4 3 + E R10 + + 4 3 E HPL + JP4 C17 0.22u short C18 0.22u JP5 HPL Cap-less LIN1 JP7 R11 C16 220u R12 2.2k R13 2.2k HVCM JP6 R14 10 R15 10 GND RIN1 JP8 R16 2.2k MPWR HVCM LIN2 D JP9 R17 2.2k D RIN2 J3 LIN2/RIN2 C19 1u 6 RIN2 + 4 3 C20 1u TP1 SPLP J4 SPK/L LIN2 + 1 SPLP JP10 High SPN C C21 1u J5 MIN/LIN3/RIN3 6 1 SPLN TP3 SPRP RIN3 4 3 TP2 SPLN C JP11 High SPP J6 SPK/R + LIN3 JP12 SPRN 6 1 SPRP + 4 3 1 C22 1u 6 4 3 TP4 SPRN MIN/LIN3 R18 20k B C24 1u + C23 1u RIN4 ROUT LIN4 LOUT B J7 LOUT/ROUT 6 + J8 LIN4/RIN4 R19 open + 4 3 + C25 1u 6 1u C26 4 3 JP13 LINEOUT A A Title Size A3 Date: A B C D AKD4648-C Document Number Rev Input/Output Friday, March 30, 2007 Sheet E 1 2 of 5 A B C D E 1 D3V L1 2 47u PORT1 E VCC 3 GND OUT 2 1 C27 0.1u TORX141 + C28 10u D3V R20 E 470 + C29 10u C30 0.1u + C31 10u C32 4.7u C34 0.1u R21 10k + C33 0.1u DIF1 5 DIF0 6 OCKS1 7 CAD0 8 D DIF0/RX5 2 TEST 3 4 5 XSEL/RX7 6 7 8 9 DVSS 49 50 R AVSS 52 51 VCOM 53 P/SN AVDD 54 ACKS 55 RXN0 56 RXP0 57 AVSS 59 58 RX1 AVDD 61 60 RX2 62 RX3 AVSS FILT 48 XTL1 47 DIF1/RX6 XTL0 46 PDN PSEL 45 IPS1/IIC 44 DVDD BVSS 43 VIN DVSS 42 DAUX DVDD 41 OCKS0/CSN/CAD0 40 OCKS1/CCLK/SCL 39 D 4 3 2 1 CAD0 1 AVDD IPS0/RX4 SW DIP-4 S1 L 64 U2 H 63 4 3 2 1 TVDD 4115_PDN 47k C35 0.1u C36 0.1u SDTO AK4115 C37 10u R22 5.1 + RP1 D3V C C 14 BICK INT0 35 DIR_SDTO 15 SDTO ELRCK 34 DIR_LRCK 16 LRCK EMCK 33 5p C40 1 32 OVSS 31 5p C42 + 4115_MCKI JP14 PORT2 GND 30 XTI2 C41 0.1u X1 D3V 3 2 B 11.2896MHz 1 2 C39 0.1u IN VCC 29 28 XTI1 27 26 25 24 23 22 21 20 C U 19 17 B 18 B C38 0.1u INT0 EBICK 36 DIR_BICK OVDD INT1 XTO2 OVSS XTO1 37 13 TVSS 38 CM0/CDTO/CAD1 TXN1 CM1/CDTI/SDA OVDD TXP1 MCKO2 12 TX0 11 TVDD MCKO1 VOUT 10 DIR_MCLK C43 10u MCKO TOTX141 C44 0.1u A A Title Size A2 Date: A B C D AKD4648-C Document Number Rev DIR/DIT Sheet Friday, March 30, 2007 E 1 3 of 5 A B C D E JP15 MCLK DIR_MCLK JP16 BICK DIR_BICK U3 U4 E E MCKI 3 A1 B1 21 SDTI 4 A2 B2 20 SCL 5 A3 B3 19 PDN 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 9 A7 B7 15 10 A8 B8 14 R100 BICK LRCK RP2 6 5 4 3 2 1 47k 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 9 A7 B7 15 10 A8 B8 14 JP17 LRCK DIR_LRCK RP3 6 5 4 3 2 1 47k 1k AVC SDA TVDD TVDD C46 0.1u D 1 VCCA VCCB 24 2 DIR VCCB 23 11 GND OE 22 12 GND GND 13 C45 0.1u D3V 1 VCCA VCCB 24 C47 2 DIR VCCB 23 0.1u 11 GND OE 22 12 GND GND 13 AVC C48 0.1u D3V TVDD TVDD D JP18 Signal V select Master 74AVC8T245 JP19 DIR-SEL R24 AVC C 1 2 3 4 5 PORT3 10 9 8 7 6 R23 10k R25 10k 74AVC8T245 Slave 470 SCL SDA R30 1k CTRL LED1 A D3V C MCLK BICK LRCK SDTI VCC R26 1k K PORT4 10 9 8 7 6 1 2 3 4 5 GND GND NC NC SDTO ERF DSP 4115_PDN D3V R27 K INT0 D1 A 1 2 3 4 5 6 SW1 C49 4Y 4A 5Y 5A 6Y 6A JP20 SDTO-IN 8 9 10 11 12 13 ADC PDN 0.1u SDTO B JP21 SDTI 14 7 D3V 2 3 H 1A 1Y 2A 2Y 3A 3Y 1 L 10k U5 10k HSU119 B D3V R28 C50 Vcc GND DIR_SDTO DIR 74HC14 0.1u A A Title Size A3 Date: A B C D AKD4648-C Document Number Friday, March 30, 2007 Rev LOGIC 1 Sheet E 4 of 5 5 4 3 2 1 L4 (short) 2 VCC1 1 1 HVDD 1 D3V L2 T45_RED 10u D 2 T1 VCC TA48033F D JP22 REG-SEL 1 2 + AGND1 C51 47u GND AVDD IN OUT REG C52 C53 0.1u 0.1u R29 10 DVDD 1 1 + 2 T45_BK AGND C54 47u AGND JP23 TVDD-SEL L3 (short) TVDD1 1 2 T45_OR + 2 DGND1 C 1 TVDD 1 C C55 47u 1 T45_BK B B A A Title Size B Date: 5 4 3 2 AKD4648-C Document Number Rev 1 POWER Friday, March 30, 2007 Sheet 1 5 of 5