PA7536 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other wide-gate functions Development and Programmer Support - Anachip WinPLACE Development Software - Fitters for ABEL and other software - Programming support by popular third-party programmers High-Speed Commercial and Industrial Versions - As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures General Description The PA7536 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7536 offers a versatile logic array architecture with 12 I/O pins, 14 input pins and 36 registers/latches (12 buried logic cells, 12 Input registers/latches and 12 buried registers/latches). Its logic array implements 50 sum-of-products logic functions that share 64 product terms. The PA7536’s logic and I/O cells (LCCs, IOCs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells). Cells are configurable as D, T, and JK registers with Figure 1. Pin Configuration I/CLK1 1 28 I/CLK2 I 2 27 I/O I 3 26 I/O I 4 25 I/O I 5 24 I/O I 6 23 I/O VCC 7 22 I/O I 8 21 GND I 9 20 I/O I 10 19 I/O I 11 18 I/O I 12 17 I/O I 13 16 I/O I 14 15 I/O Figure 2. Block Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/CLK1 I I I I I VCC I I I I I I I 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Global Cells 12 Input Pins I/CL K2 G lo ba l Ce lls I 1 28 27 26 I/O Ce lls In p ut C ells I/O I/O I I/O I 5 25 I/O I I/O I 6 24 I/O VC C I/O VCC 7 23 I/O I G ND I 8 22 I/O I I/O I 9 21 GND I I/O I 10 20 I/O I I 11 19 I/O I I I/O I/O I/O I/O I I 12 13 14 15 16 17 18 I I/O Cells (IOC) 12 I PLCC L og ic Array I/O I I 2 2 2 sum terms 3 product term s for Global Cells A B C D 12 I/O Pins Buried logic 12 I/CL K1 D IP 3 Input Cells (INC) 76 (38X2) Array Inputs true and com plement 12 I/O I/O I/CLK2 I/CLK1 I I I 2 Input/ Global Clock Pins I/CLK2 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O S O IC 4 independent or global clocks, resets, presets, clock polarity, and other special features, making the PA7536 suitable for a variety of combinatorial, synchronous and asynchronous logic applications. The PA7536 offers pin compatibility and super-set functionality to popular 28-pin PLDs, such as the 26V12. Thus, designs that exceed the architectures of such devices can be expanded upon. The PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3MHz (fMAX) at moderate power consumption 105mA (75mA typical). Packaging includes 28-pin DIP, SOIC, and PLCC (see Figure 1). Development and programming support for the PA7536 is provided by Anachip and popular third-party development tool manufacturers. Logic Control Cells (LCC) 12 Logic functions to I/O cells 12 48 sum term s (four per LCC) 12 Logic Control Cells up to 3 output functions per cell (36 total output functions possible) I/O L og ic Co ntro l C e lls P A7536 I/O I/O I/O 0 8-1 6-0 02 A 08 -16 -0 01A 1 04-02-052A Inside the Logic Array The heart of the PEEL™ Array architecture is based on a logic array structure similar to that of a PLA (programmable AND, programmable OR). The logic array implements all logic functions and provides interconnection and control of the cells. Depending on the PEEL™ Array selected, a range of 38 to 62 inputs is available into the array from the I/O cells, inputs cells and input/global-clock pins. All inputs provide both true and complement signals, which can be programmed to any product term in the array. The number of product-terms among PEEL™ Arrays ranges from 67 to 125. All product terms (with the exception of certain ones fed to the global cells) can be programmably connected to any of the sum-terms of the logic control cells (four sum-terms per logic control cell). Product-terms and sum-terms are also routed to the global cells for control purposes. Figure 3 shows a detailed view of the logic array structure. From IO C ells (IO C,INC, I/CLK) ensures that product-terms are used where they are needed and not left unutilized or duplicated. Secondly, the sum-of-products functions provided to the logic cells can be used for clocks, resets, presets and output enables instead of just simple product-term control. The PEEL™ logic array can also implement logic functions with many product terms within a single-level delay. For example a 16-bit comparator needs 32 shared product terms to implement 16 exclusive-OR functions. The PEEL™ logic array easily handles this in a single level delay. Other PLDs/CPLDs either run out of product-terms or require expanders or additional logic levels that often slow performance and skew timing. Logic Control Cell (LCC) Logic Control Cells (LCC) are used to allocate and control the logic functions created in the logic array. Each LCC has four primary inputs and three outputs. The inputs to each LCC are complete sum-of-product logic functions from the array, which can be used to implement combinatorial and sequential logic functions, and to control LCC registers and I/O cell output enables. From G lobal C ell 38 Array Inputs System Clock Preset RegType Reset O n/O ff MUX From Logic Control Cells (LCC) To G lobal Cells 67 Product T erm s P Q D ,T,J MUX To Array R EG K R From Array A B C D To I/O Cell MUX To Logic Control Cells (LCC) Figure 4. Logic Control Cell Block Diagram 08-16-003A PA 7536 Logic Array 08 -16-0 04A 50 Sum Term s Figure 3 PA7536 Logic Array True Product-Term Sharing The PEEL™ logic array provides several advantages over common PLD logic arrays. First, it allows for true productterm sharing, not simply product-term steering, as commonly found in other CPLDs. Product term sharing 2 As shown in Figure 4, the LCC is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous D, T, or JK registers (clocked-SR registers, which are a subset of JK, are also possible). See Figure 5. EEPROM memory cells are used for programming the desired configuration. Four sum-ofproduct logic functions (SUM terms A, B, C and D) are fed into each LCC from the logic array. Each SUM term can be selectively used for multiple functions as listed below. 04-02-052A third, an output enable or an additional buried logic function. The multi-function PEEL™ Array logic cells are equivalent to two or three macrocells of other PLDs, which have only one output per cell. They also allow registers to be truly buried from I/O pins without limiting them to inputonly (see Figure 8 and Figure 9). Sum-A = D, T, J or Sum-A Sum-B = Preset, K or Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable, Sum-D D P D R e g is te r Q = D after clocked Q Best for storage, sim ple counters, shifters and state m achines with few hold (loop) conditions. R From Global Cell Input Cell Clock T P Q T R e g is te r Q toggles when T = 1 Q holds when T = 0 REG / Latch Best for wide binary counters (saves product term s) and state m achines with m any hold (loop) conditions. R Q M UX Input J K P Q J K R e g is te r Q toggles when J/K = 1/1 Q holds when J/K = 0/0 Q =1 when J/K = 1/0 Q =0 when J/K = 0/1 Input To Array Input Cell (INC) R From Global Cell Com bines features of both D and T registers. Input Cell Clock 08-16-005A REG / Latch Figure 5. LCC Register Types SUM-A can serve as the D, T, or J input of the register or a combinatorial path. SUM-B can serve as the K input, or the preset to the register, or a combinatorial path. SUM-C can be the clock, the reset to the register, or a combinatorial path. SUM-D can be the clock to the register, the output enable for the connected I/O cell, or an internal feedback node. Note that the sums controlling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other PLDs. This also means that any input or I/O pin can be used as a clock or other control function. Several signals from the global cell are provided primarily for synchronous (global) register control. The global cell signals are routed to all LCCs. These signals include a high-speed clock of positive or negative polarity, global preset and reset, and a special register-type control that selectively allows dynamic switching of register type. This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from D-type registers to load and T-type registers to count (see Figure 11). Q To Array Input M UX M UX A,B,C or Q From Logic Control Cell M UX I/O Pin M UX D 1 0 I/O Cell (IOC) 08-16-006A Figure 6. I/O Cell Block Diagram D Q IO C /IN C R e g is te r Q = D after rising edge of clock holds until next rising edge L Q IO C /IN C L a tc h Q = L when clock is high holds value when clock is low 08-16-007A Multiple Outputs Per Logic Cell An important feature of the logic control cell is its capability to have multiple output functions per cell, each operating independently. As shown in Figure 4, two of the three outputs can select the Q output from the register or the Sum A, B or C combinatorial paths. Thus, one LCC output can be registered, one output can be combinatorial and the 3 Figure 7. IOC Register Configurations 04-02-052A Input Cells (INC) Global Cells Input cells (INC) are included on dedicated input pins. The block diagram of the INC is shown in Figure 6. Each INC consists of a multiplexer and a register/transparent latch, which can be clocked from various sources selected by the global cell. The register is rising edge clocked. The latch is transparent when the clock is high and latched on the clock’s failing edge. The register/latch can also be bypassed for a non registered input. The global cells, shown in Figure 10, are used to direct global clock signals and/or control terms to the LCCs, IOCs and INCs. The global cells allow a clock to be selected from the CLK1 pin, CLK2 pin, or a product term from the logic array (PCLK). They also provide polarity control for IOC clocks enabling rising or falling clock edges for input registers/latches. Note that each individual LCC clock has its own polarity control. The global cell includes sum-ofproducts control terms for global reset and preset, and a fast product term control for LCC register-type, used to save product terms for loadable counters and state machines (see Figure 11). The PA7536 provides two global cells that divide the LCC and IOCs into two groups, A and B. Half of the LCCs and IOCs use global cell A, half use global cell B. This means, for instance, two high-speed global clocks can be used among the LCCs. I/O Cell (IOC) All PEEL™ Arrays have I/O cells (IOC) as shown above in Figure 6. Inputs to the IOCs can be fed from any of the LCCs in the array. Each IOC consists of routing and control multiplexers, an input register/transparent latch, a threestate buffer and an output polarity control. The register/ latch can be clocked from a variety of sources determined by the global cell. It can also be bypassed for a nonregistered input. A feature of the 7536 IOC is the use of SUM-D as a feed-back to the array when the I/O pin is a dedicated output. This allows for additional buried registers and logic paths. (See Figure 8 & Figure 9). CLK1 CLK2 INC Clocks M UX PCLK Global C ell: IN C G roup A & B CLK1 Q M UX LCC Clocks M UX IO C Clocks D CLK2 Input w ith optional register/latch I/O PCLK Reg-Type I/O w ith independent output enable A D Q B LCC Reg-Typ e Preset LCC Presets LCC Resets Reset 1 G lobal C ell: LC C & IO C 08-16-010A 2 C OE D Figure 10. Global Cells 08-16-008A Reg-Type from G lobal Cell Figure 8. LCC & IOC With Two Outputs R e g is te r T yp e C h a n g e F e a tu re Q D D Buried register or logic paths P Q O utput R A B C D D Q G lobal Cell can dynam ically change userselected LCC registers from D to T or from D to JK. This saves product terms for loadable counters or sta te m achines. Use as D register to load, use as T or JK to count. Tim ing allo ws dynam ic opera tion. 1 2 3 T 08-16-009A P R E x a m p le : Product terms for 10 bit loadable binary co unter Q D uses 57 prod uct term s (47 count, 10 load ) T uses 30 prod uct term s (10 count, 20 load ) D/T uses 20 product term s (10 count, 10 lo ad) 08-16-011A Figure 9. LCC & IOC With Three Outputs Figure 11. Register Type Change Feature 4 04-02-052A PEEL™ Array Development Support Development support for PEEL™ Arrays is provided by Anachip and manufacturers of popular development tools. Anachip offers the powerful PLACE Development Software (free to qualified PLD designers). The PLACE software includes an architectural editor, logic compiler, waveform simulator, documentation utility and a programmer interface. The PLACE editor graphically illustrates and controls the PEEL™ Array’s architecture, making the overall design easy to understand, while allowing the effectiveness of boolean logic equations, state machine design and truth table entry. The PLACE compiler performs logic transformation and reduction, making it possible to specify equations in almost any fashion and fit the most logic possible in every design. PLACE also provides a multi-level logic simulator allowing external and internal signals to be simulated and analyzed via a waveform display.(See Figure 12, Figure 13 and Figure 14) waste. Programming of PEEL™ Arrays is supported by popular third party programmers. Design Security and Signature Word The PEEL™ Arrays provide a special EEPROM security bit that prevents unauthorized reading or copying of designs. Once set, the programmed bits of the PEEL™ Arrays cannot be accessed until the entire chip has been electrically erased. Another programming feature, signature word, allows a user-definable code to be programmed into the PEEL™ Array. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed in the device or to record the design revision. Figure 13 - PLACE LCC and IOC screen Figure 12 - PLACE Architectural Editor for PA7536 PEEL™ Array development is also supported by popular development tools, such as ABEL and CUPL, via ICT’s PEEL™ Array fitters. A special smart translator utility adds the capability to directly convert JEDEC files for other devices into equivalent JEDEC files for pin-compatible PEEL™ Arrays. Programming PEEL™ Arrays are EE-reprogrammable in all package types, plastic-DIP, PLCC and SOIC. This makes them an ideal development vehicle for the lab. EEreprogrammability is also useful for production, allowing unexpected changes to be made quickly and without 5 Figure 14 - PLACE simulator screen 04-02-052A Table 1. Absolute Maximum Ratings Symbol Parameter Conditions Ratings Unit VCC Supply Voltage Relative to Ground -0.5 to + 7.0 V 1 VI, VO Voltage Applied to Any Pin Relative to Ground -0.5 to VCC + 0.6 V IO Output Current Per pin (IOL, IOH) ±25 mA TST Storage Temperature TLT Lead Temperature -65 to + 150 °C +300 °C Soldering 10 seconds Table 2. Operating Ranges Symbol Parameter Conditions Min Max Commercial 4.75 5.25 Industrial 4.5 5.5 VCC Supply Voltage TA Ambient Temperature TR Clock Rise Time See Note 2 20 ns TF Clock Fall Time See Note 2 20 ns TRVCC VCC Rise Time See Note 2 250 ms Commercial 0 +70 Industrial -40 +85 Unit V °C Over the Operating Range Table 3. D.C. Electrical Characteristics Symbol Parameter Conditions Min Max Unit VOH Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA VOHC Output HIGH Voltage CMOS VCC = Min, IOH = -10µA VOL Output LOW Voltage - TTL VCC = Min, IOL = 16mA 0.5 V VOLC Output LOW Voltage CMOS VCC = Min, IOL = -10µA 0.15 V 2.4 V VCC - 0.3 V VIH Input HIGH Level 2.0 VCC + 0.3 V VIL Input LOW Level -0.3 0.8 V IIL Input Leakage Current VCC = Max, GND ≤VIN ≤VCC ±10 µA IOZ Output Leakage Current I/O = High-Z, GND ≤VO ≤VCC ±10 µA ISC Output Short Circuit Current4 VCC = 5V, VO = 0.5V, TA= 25°C -30 -120 mA 45 (typ.)19 70 mA 6 pF 12 pF ICC11 VCC Current CIN7 Input Capacitance5 COUT7 Output Capacitance5 VIN = 0V or VCC3,11 f = 25MHz All outputs disabled4 -15 TA = 25°C, VCC = 5.0V @ f = 1 MHz 6 04-02-052A Over the Operating Range Table 4. A.C Electrical Characteristics Combinatorial Symbol tPDI tPDX tIA tAL tLC tLO tOD, tOE tOX -15/I-15 Min Max 6,12 Parameter Propagation delay Internal (tAL + tLC) Propagation delay External (tIA + tAL +tLC + tLO) Input or I/O pin to array input Array input to LCC LCC input to LCC output10 LCC output to output pin Output Disable, Enable from LCC output7 Output Disable, Enable from input pin7 9 15 2 8 1 4 4 15 Unit ns ns ns ns ns ns ns ns This device has been designed and tested for the recommended operating conditions. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Figure 15. Combinatorial Timing - Waveforms and Block Diagram 7 04-02-052A Table 5. A.C. Electrical Characteristics Sequential Symbol 6,1 Parameter tSCX Internal set-up to system clock8 - LCC14 (tAL + tSK + tLC - tCK) Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI) tCOI System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC) tCOX System-clock to Output Ext. - LCC (tCOI + tLO) tHX Input hold time from system clock - LCC tSCI -15/I-15 Min Max Unit ns 5 7 ns 7 ns 11 ns 0 ns tSK 13 LCC Input set-up to async. clock - LCC 2 ns tAK Clock at LCC or IOC - LCC output 1 ns tHK LCC input hold time from system clock - LCC 4 ns ns 14 tSI Input set-up to system clock - IOC/INC (tSK - tCK) 0 tHI Input hold time from system clock - IOC/INC (tSK - tCK) 4 tPK Array input to IOC PCLK clock ns 6 17 ns tSPI Input set-up to PCLK clock - IOC/INC (tSK-tPK-tIA) 0 ns tHPI 6 ns 7 ns 0 ns 7 ns tCK Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK) Input set-up to system clock - IOC/INC Sum-D15 (tIA + tAL + tLC + tSK - tCK) Input hold time from system clock - IOC Sum-D Input set-up to PCLK clock (tIA + tAL + tLC + tSK – tpK) - IOC Sum-D Input hold time from PCLK clock - IOC Sum-D System-clock delay to LCC/IOC/INC tCW System-clock low or high pulse width tSD tHD tSDP 6 ns ns fMAX1 Max. system-clock frequency Int/Int 1/(tSCI + tCOI) 83.3 MHz fMAX2 Max. system-clock frequency Ext/Int 1/(tSCX + tCOI) 71.4 MHz fMAX3 Max. system-clock frequency Int/Ext 1/(tSCI + tCOX) 62.5 MHz fMAX4 Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX) 55.5 MHz fTGL Max. system-clock toggle frequency 1/(tCW + tCW)9 83.3 MHz tPR LCC presents/reset to LCC output 1 ns tST Input to Global Cell present/reset (tIA + tAL + tPR) 11 ns tAW Asynch. preset/reset pulse width tRT Input to LCC Reg-Type (RT) 7 ns tRTV LCC Reg-Type to LCC output register change 1 ns tRTC Input to Global Cell register-type change (tRT + tRTV) 8 tRW Asynch. Reg-Type pulse width tRESET Power-on reset time for registers in clear state2 tHDP 0 6 ns 8 ns 10 5 8 ns ns µs 04-02-052A Figure 16. Sequential Timing – Waveforms and Block Diagram Notes 1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for periods less than 20ns. 2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at 10% and 90% levels. 3. I/O pins are 0V or VCC. 4. Test one output at a time for a duration of less than 1 sec. 5. Capacitances are tested on a sample basis. 6. Test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 7. tOE is measured from input transition to VREF ±0.1V (See test loads at end of Section 6 for VREF value). tOD is measured from input transition to VOH -0.1V or VOL +0.1V. 8. “System-clock” refers to pin 1 or pin 28 high speed clocks. 9. For T or JK registers in toggle (divide by 2) operation only. 10. For combinatorial and async-clock to LCC output delay. 11. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit D-type counter. 12. Test loads are specified in Section 5 of the Data Book. 13. “Async. Clock” refers to the clock from the Sum term (OR gate). 9 14. The “LCC” term indicates that the timing parameter is applied to the LCC register. The “IOC” term indicates that the timing parameter is applied to the IOC register. The “LCC/IOC” term indicates that the timing parameter is applied to both the LCC and IOC registers. The “LCC/IOC/INC” term indicates that the timing parameter is applied to the LCC,IOC, and INC registers. 15. This refers to the Sum-D gate routed to the IOC register for an additional buried register. 16. The term “input” without any reference to another term refers to an (external) input pin. 17. The parameter tSPI indicates that the PCLK signal to the IOC register is always slower than the data from the pin or input by the absolute value of (tSK -tPK -tIA). This means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. Additionally, the data from the pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at the IOC register. 18. Typical (typ) ICC is measured at TA = 25° C, freq = 25MHZ, VCC = 5V 04-02-052A Table 6. Ordering Information Part Number Speed Temperature Package PA7536P-15 P28 PA7536J-15 PA7536S-15 J28 C S28 9/15ns PA7536PI-15 PA7536JI-15 PA7536SI-15 P28 J28 S28 I Figure 17. Part Number Device Suffix PA7536JI-15 Package Speed P = Plastic 600mil DIP S = SOIC J = Plastic (J) Leaded Chip Carrier (PLCC) -15 = 9ns/15ns tpd/tpdx Temperature Range (Blank) = Commercial 0 to 70° C I = Industrial -40 to +85° C 08-16-017A Anachip USA, Inc. Email: [email protected] 780 Montague Expressway, #201 San Jose, CA 95131 TEL (408) 321-9600 FAX (408) 321-9696 Website: http://www.anachip.com ©2002 Anachip Corp. Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life support devices or systems. © Marks bearing or ™ are registered trademarks and trademarks of Anachip Corp. 10 04-02-052A