Commercial/ Industrial PA7024 PA7024 PEELTM Array Programmable Electrically Erasable Logic Array Features ■ CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground compatibility ■ Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried ■ Flexible Logic Cell - Multiple output functions per cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables -Sum of products logic for output enable ■ High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX) - Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85°C temperatures ■ Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other wide-gate functions ■ Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software -Programming support by ICT PDS-3 and popular thirdparty programmers General Description The PA7024 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7024 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40 registers/latches (20 buried logic cells and 20 I/O registers/latches). Its logic array implements 84 sum-of-product logic functions that share 80 product terms. The PA7024’s logic and I/O cells (LCCs, IOCs) are extremely flexible, offering two output functions per logic cell (a total of 40 for all 20 logic cells). Logic cells are configurable as D, T, and JK registers with independent Figure 1: Pin Configuration DIP PLCC-J or global clocks, resets, presets, clock polarity, and other special features. This makes them suitable for a wide variety of combinatorial, synchronous and asynchronous logic applications. With pin compatibility and super-set functionality to most 24-pin PLDs, (22V10, EP610/630, GAL6002), the PA7024 can implement designs that exceed the architectures of such devices. The PA7024 supports speeds as fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at moderate power consumption 120mA (85mA typical). Packaging includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure 1). Development and programming support for the PA7024 is provided by ICT and popular third-party development tool manufacturers. Figure 2. Block Diagram SOIC PLCC-JN 1 of 6 PA7024 Table 1. Absolute Maximum Ratings Symbol Parameter VCC Supply Voltage This device has been designed and tested for the recommended operating conditions. Proper operation outside these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage. Conditions Relative to Ground VI, VO Voltage Applied to Any Pin IO Output Current TST Storage Temperature TLT Lead Temperature 2 1 Relative to Ground Ratings Unit -0.5 to + 7.0 V -0.5 to V CC + 0.6 V ±25 mA Per pin (IOL, IOH) -65 to + 150 °C +300 °C Soldering 10 seconds Table 2. Operating Ranges Symbol Parameter Conditions Min Max Commercial 4.75 5.25 VCC Supply Voltage 4.5 5.5 TA Ambient Temperature 0 +70 -40 +85 TR Clock Rise Time TF Clock Fall Time See Note 2 20 ns TRVCC VCC Rise Time See Note 2 250 ms Industrial Commercial Industrial See Note 2 20 Unit V °C ns Table 3. D.C. Electrical Characteristics over the recommended operating conditions Symbol Parameter Conditions VOH Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA 2.4 VCC - 0.3 VOHC Output HIGH Voltage - CMOS VCC = Min, IOH = -10µA VOL Output LOW Voltage - TTL V CC = Min, IOL = 16mA V CC = Min, IOL = 10µA VOLC Output LOW Voltage - CMOS VIH Input HIGH Level VIL Input LOW Level IIL Input Leakage Current V CC = Max, GND ≤ VIN ≤ VCC IOZ Output Leakage Current I/O = High-Z, GND ≤ VO ≤ VCC ISC Output Short Circuit Min 2.0 -0.3 Current4 VCC = 5V, VO = 0.5V, TA= 25°C -30 -15 ICC11 VCC Current VIN = 0V or VCC3,11 f = 25MHz All outputs disabled4 -20 -25 I-25 CIN7 Capacitance5 Input COUT7 Output Capacitance5 TA = 25°C, VCC = 5.0V @ f = 1 MHz 2 of 6 Max Unit V V 0.5 V 0.15 V VCC + 0.3 V 0.8 V ±10 µA ±10 µA -120 mA 120 85 (typ.) 17 120 120 mA 130 6 pF 12 pF PA7024 Table 1. A.C Electrical Characteristics Combinatorial Over the operating range -15 Min I -25 Min Max Parameter tPDI Propagation delay Internal (tAL + tLC) 10 13 17 ns tPDX Propagation delay External (tIA + tAL +tLC + tLO) 15 20 25 ns tIA Input or I/O pin to array input 2 2 2 ns tAL Array input to LCC tLC LCC input to LCC output tLO LCC output to output pin tOD, tOE tOX 10 Max -20 Min Max Symbol 6,12 Unit 9 12 16 ns 1 1 1 ns 3 5 6 ns Output Disable, Enable from LCC output7 3 5 6 ns Output Disable, Enable from input pin7 15 20 25 ns Combinatorial Timing - Waveforms and Block Diagram 3 of 6 PA7024 Table 1. A.C. Electrical Characteristics Sequential over the operating range -15 6,12 Min -20 Parameter tSCI Internal set-up to system clock8 - LCC14 (tAL + tSK + tLC - tCK) 6 9 15 ns tSCX Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI) 8 11 17 ns tCOI System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC) 8 8 8 ns tCOX System-clock to Output Ext. - LCC (t COI + tLO) 12 13 13 ns tHX Input hold time from system clock - LCC LCC Input set-up to async. tAK Clock at LCC or IOC - LCC output tHK LCC input hold time from system clock - LCC clock13 - LCC Min Max Min Max Unit Symbol tSK Max I-25 0 0 0 ns 3 3 4 ns 1 1 1 ns 4 4 4 ns 0 0 0 ns tSI Input set-up to system clock - IOC/INC tHI Input hold time from system clock - IOC/INC14 (tSK - tCK) tPK Array input to IOC PCLK clock tSPI Input set-up to PCLK clock18 - IOC/INC (tSK-tPK-tIA)16 0 0 0 ns tHPI Input hold from PCLK clock18 - IOC/INC (tPK+tIA-tSK)16 5 6 7 ns 14 (tSK - tCK) 4 4 6 4/3 7 ns 9 ns tCK System-clock delay to LCC/IOCINC tCW System-clock low or high pulse width fMAX1 Max. system-clock frequency Int/Int 1/(tSCI + tCOI) 71.4 58.8 43.5 MHz fMAX2 Max. system-clock frequency Ext/Int 1/(tSCX + tCOI) 62.5 52.6 40.0 MHz 7 7 7 7 7 8 ns ns fMAX3 Max. system-clock frequency Int/Ext 1/(tSCI + tCOX) 55.5 45.5 35.7 MHz fMAX4 Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX) 50.0 41.6 33.3 MHz fTGL Max. system-clock toggle frequency 1/(tCW + tCW)9 71.4 71.4 62.5 MHz tPR LCC presents/reset to LCC output 1 1 2 ns tST Input to Global Cell present/reset (tIA + tAL + tPR) 12 15 20 ns tAW Asynch. preset/reset pulse width tRT Input to LCC Reg-Type (RT) 10 ns tRTV LCC Reg-Type to LCC output register change 1 1 2 ns tRTC Input to Global Cell register-type change (tRT + tRTV) 7 9 12 ns tRW Asynch. Reg-Type pulse width 5 µs tRESET Power-on reset time for registers in clear state 8 8 6 10 10 5 2 4 of 6 8 8 ns 10 5 ns PA7024 Sequential Timing - Waveforms and Block Diagram Notes 1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for periods less than 20ns. 2. Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at 10% and 90% levels. 3. I/O pins are 0V or VCC. 4. Test one output at a time for a duration of less than 1 sec. 5. Capacitances are tested on a sample basis. 6. Test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 7. tOE is measured from input transition to V REF ±0.1V (See test loads for VREF value). tOD is measured from input transition to VOH -0.1Vor VOL +0.1V. 8. “System-clock” refers to pin 1 or 13 (2 or 16 PLCC) high speed clocks. 9. For T or JK registers in toggle (divide by 2) operation only. 10. For combinatorial and async-clock to LCC output delay. 11. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit D-type counter. 12. Test loads are specified in Section 5 of this Data Book. 13. “Async. clock” refers to the clock from the Sum term (OR gate). 14. The “LCC” term indicates that the timing parameter is applied to the LCC register. The “IOC” term indicates that the timing parameter is applied to the IOC register. The “LCC/IOC/INC” term indicates that the timing parameter is applied to both the LCC, IOC and INC registers. 15. The term “Input” without any reference to another term refers to an (external) input pin. 16. The parameter tSPI indicates that the PCLK signal to the IOC register is always slower than the data from the pin or input by the absolute value of (tSK -tPK -tIA). This means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. Additionally, the data from the pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at the IOC register. 17. Typical (typ) ICC is measured at TA =25°C, Freq = 25MHz, VCC =5V. 5 of 6 PA7024 Ordering Information Part Number Speed Temperature Package PA7024P-15 P24 PA7024J-15 10/15ns PA7024JN-15 J28 C JN28 PA7024S-15 S24 PA7024P-20 P24 PA7024J-20 13/20ns PA7024JN-20 J28 C JN28 PA7024S-20 S24 PA7024PI-25 17/25ns I P24 PA7024JI-25 17/25ns I J28 PA7024JNI-25 17/25ns I JN28 PA7024SI-25 17/25ns I S24 Part Number Device Suffix PA7024J-20 Package Speed P = Plastic 300mil DIP J = Plastic (J) Leaded Chip Carrier JN = PLCC Alternate Pin Out S = SOIC 300mil Gullwing -15 = 10ns/15ns tpdi/tpdx -20 = 13ns/20ns tpdi/tpdx -25 = 17ns/25ns tpdi/tpdx Temperature Range (Blank) = Commercial 0 to 70°C I = Industrial -40 to +85°C 6 of 6