® ADC601 12-Bit 900ns ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS ● ● ● ● ● DIGITAL SIGNAL PROCESSING ● HIGH-SPEED DATA ACQUISITION SYSTEMS FAST CONVERSION: 900ns CAN BE SHORT-CYCLED INPUT RANGES: ±5V, ±10V, 0 to –10V HIGH SIGNAL/NOISE RATIO: 68dB ● ● ● ● ● LOW IMD: 75dB ● PARALLEL AND SERIAL OUTPUT ● 32-PIN CERAMIC DIP PACKAGE DESCRIPTION with no missing codes over the full input voltage, power supply, and operating temperature range. The gain and offset errors are laser trimmed to specification. Optionally they may be externally adjusted to zero. The ADC601 is a high-speed Duolithic™ (two chips) successive approximation analog-to-digital converter. This unique two-chip design utilizes a bipolar technology with on-chip thin film resistors to preserve analog accuracy and a high-speed CMOS chip to perform digital logic control. Outstanding linearity, noise, and dynamic range are achieved by this converter design. The ADC601 has been tested with several sample/hold amplifiers and distortion results are documented in this data sheet. Internal scaling resistors are provided for the selection of analog signal input ranges of ±5V, ±10V and 0V to –10V. The ADC601’s input is specifically designed to be easily driven with minimal disturbance to the driving amplifier. Output codes are available in complementary binary for unipolar inputs and bipolar offset binary for bipolar inputs. Comparator In 12-Bit D/A Converter Input Range Select Reference The ADC601 is complete with internal reference, clock, and comparator and is packaged in a 32-pin ceramic DIP. Conversion time is set at the factory to 900ns. Serial and parallel output performance is guaranteed Bipolar Offset MEDICAL INSTRUMENTATION ANALYTICAL INSTRUMENTATION TEST AND IMAGING SYSTEMS WAVEFORM ANALYZERS All digital inputs and outputs are TTL-compatible. Power supply requirements are ±15V and +5V. Convert Command 12-Bit Successive Approx Register (SAR) – + Parallel Digital Output Clock Clock Rate Control Clock Out Status Serial Out Comparator Duolithic™ Burr-Brown Corporation International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-867C Printed in U.S.A. March, 1992 SPECIFICATIONS ELECTRICAL TCASE = +25°C, 900ns conversion time, ±VCC = ±15V, +VDD = +5V, and 6-minute warm-up in a normal convection environment unless otherwise noted. ADC601JG PARAMETER CONDITIONS MIN TYP RESOLUTION ADC601KG MAX MIN TYP 12 MAX UNITS * Bits ANALOG CHARACTERISTICS INPUTS Voltage Ranges: Bipolar Unipolar Impedance: –10V to 0V, ±5V ±10V Full Scale(FSR)(1)(2) Full Scale(FSR)(1)(2) ±5, ±10 0 to –10 1.4 2.4 990ns Conversion Time 990ns Conversion Time 990ns Conversion Time 990ns Conversion Time 990ns Conversion Time ±0.08 ±0.12 ±0.08 ∆ +VCC = ±5% ∆ –VCC = ±5% ∆ +VDD = ±5% ±0.0036 ±0.0005 ±0.001 * * * * V V kΩ kΩ TRANSFER CHARACTERISTICS ACCURACY Gain Error(3) Input Offset Error(3): Unipolar Bipolar Integral Linearity Error Differential Linearity Error No Missing Codes Power Supply Rejection of Offset and Gain ±0.55 ±1.2 ±0.8 ±0.024 ±0.024 Guaranteed * * * ±0.2 ±0.5 ±0.25 ±0.012 ±0.012 % % of FSR % of FSR % of FSR % of FSR * %FSR/%VCC %FSR/%VCC %FSR/%VDD * * DIGITAL CHARACTERISTICS INPUT Logic Family Convert Command Logic Voltages Convert Command Currents Logic Low Logic High Logic Low Logic High 0 +2 Convert Command TTL-Compatible CMOS +0.8 * +VDD * –150 –150 High Level When Converting * * V V µA µA * µs ns/%VDD * * V V MHz CONVERSION TIME Factory Set Power Supply Rejection of Conversion Time Without User Adjustment D +VDD = ±5% 0.9 ±1 1 * * OUTPUT Logic Family Bits 1 through 12, Serial, Status, Clock Out Logic Low, IOL = 3.2mA Logic High, IOH = –1mA +2.7 Internal Clock Frequency Status TTL-Compatible CMOS +0.1 +0.4 * +4.9 * * 13 * Low Level When Data Valid DYNAMIC CHARACTERISTICS (4) (5) (6) Tested using Sample/Hold Amplifier SHC804 and ADC601 (See Typical Performance Curves) Differential Linearity Error fC = 10kHz: 68.3% of All Codes 99.7% of All Codes 100% of All Codes 0.5 0.8 1.0 0.4 0.6 0.7 LSB LSB LSB Total Harmonic Distortion fC = 10kHz, fC = 10kHz, fC = 250kHz, fC = 500kHz, fS = 500kHz fS = 1MHz fS = 500kHz fS = 1MHz –70 –74 –70 –68 * * * * dBc dBc dBc dBc –79 –78 –77 * * * dBc dBc dBc Two-Tone Intermodulation Distortion(7) fC = 11kHz and 15kHz, fS = 500kHz fC = 50kHz and 55kHz, fS = 500kHz fC = 90kHz and 110kHz, fS = 500kHz Signal-to-Noise and Distortion (SINAD) Ratio fC = 250kHz, fS = 500kHz fC = 500kHz, fS = 1MHz 66 65 * * dB dB Signal-to-Noise Ratio (SNR) fC = 250kHz, fS = 500kHz fC = 500kHz, fS = 1MHz 68 67 * * dB dB PERFORMANCE OVER TEMPERATURE Gain Input Offset: Unipolar Bipolar Internal Linearity Error Differential Linearity Error No Missing Codes Conversion Drift TMIN to TMAX TMIN to TMAX TMIN to TMAX 0.9µs Conversion Time TMIN to TMAX 0.9µs Conversion Time TMIN to TMAX 0.9µs Conversion Time TMIN to TMAX` 2 ±30 ±7 ±10 * * * ±0.015 ±0.015 * * * ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C % of FSR % of FSR Guaranteed 2 ® ADC601 ±10 ±2 ±3 ±0.02 ±0.02 * ns/°C SPECIFICATIONS (CONT) ELECTRICAL TCASE = +25°C, 900ns conversion time, ±VCC = ±15V, +VDD = +5V, and 6-minute warm-up in a normal convection environment unless otherwise noted. ADC601JG PARAMETER CONDITIONS ADC601KG MIN TYP MAX MIN TYP MAX UNITS +14.25 –14.25 +4.75 +15 –15 +5 5.4 –65 53 1.3 25 +15.75 –15.75 +5.25 7.0 –84.5 68.9 1.7 * * * * * * * * * * * * * * * * * * * V V V mA mA mA W °C/W +70 +85 * * * * °C °C POWER SUPPLY REQUIREMENTS Supply Voltages: +VCC –VCC +VDD Supply Currents: +ICC –ICC +IDD Power Consumption Thermal Resistance, θJC Nominal ±VCC and +VDD TEMPERATURE RANGE(8) Specification Operating 0 –25 * Same specifications as for ADC601JG. NOTES: (1) Over or under range on the analog input results in constant maximum or minimum digital output. (2) FSR = Full Scale Range. (3) Adjustable to zero. (4) Dynamic tests are performed using SHC804 with ADC601 unless otherwise specified. Performance may vary depending upon choice of sample/hold. (5) See Typical Performance Curves. (6) dBc = level referred to carrier input signal = 0dB; fC = input frequency; fS = sampling frequency. (7) IMD is referred to the larger of the two input test signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 6dB lower. For example, unit connected for ±10V has 20V FSR. (8) Temperature ranges refer to case temperature. Thermal resistance was measured on a small (5" diameter) handwired circuit board; with the test device in a (zero insertion force) socket. Thermal resistance will be lower if the ADC601 is soldered into the PC board, a ground plane is used directly underneath the package, multiple PC board layers are used, or forced air cooling is employed. Use heat sinking if necessary to keep the case at specified and operating temperatures. ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS ±VCC ................................................................................................... ±18V +VDD .................................................................................................... +7V Digital Inputs ..................................................................................... +5.5V Analog Inputs ...................................................................................... ±VCC Comparator Input ............................................................... –3.7V to +0.7V Case Temperature ......................................................................... +125°C Junction Temperature .................................................................... +165°C Storage Temperature ...................................................... –65°C to +150°C ADC601 ( ) G Basic Model Number Performance Grade Code J, K: 0°C to +70°C Case Temperature Package Code G: Ceramic DIP Stresses above these ratings may permanently damage the device. PACKAGE INFORMATION(1) MODEL ADC601JG ADC601KG PACKAGE PACKAGE DRAWING NUMBER 32-Pin Hermetic DIP 32-Pin Hermetic DIP 172–2 172–2 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADC601 PIN CONFIGURATION (MSB) Bit 1 1 32 Common (Analog) Bit 2 2 31 NC (1) Bit 3 3 30 –VCC (–15V) Analog Bit 4 4 29 Bipolar Offset Current Bit 5 5 28 Common (Analog) Bit 6 6 27 Ground Sense +V DD (+5V) Digital 7 26 Comparator Input Common (Digital) 8 25 10V Input Serial Out 9 24 20V Input 23 –VCC (–15V) Analog 22 +VDD (+5V) Digital (2) 21 Common (Digital) 20 +VCC (+15V) Analog 19 Clock Rate Control 18 Convert Command 17 Clock Out Status 10 Bit 7 11 Bit 8 12 Bit 9 13 Bit 10 14 Bit 11 15 Bit 12 16 Bipolar Reference 12-Bit D/A Converter 12-Bit (SAR) CMOS 1kΩ 2kΩ – 545Ω + Clock (1) NC = No internal connection. Any voltage may be connected to pin 31, however. (2) Pin 22 must be very cleanly decoupled to keep digital noise out of the analog circuits. PIN DEFINITIONS PIN NUMBER DESIGNATION 1-6 and 11-16 Bit 1 to Bit 12 DESCRIPTION 12-bit parallel output data capable of sinking 3.2mA. 9 Serial Out 10 Status Conversion status strobe is high during data conversion; low when parallel data is valid. Negative edge may be used to latch parallel data, however, appropriate latch set-up time must be provided. Refer to tBBL in the ADC601 timing diagram. 12-bit serial data output synchronized with the negative edge of each appropriate clock cycle. 17 Clock Out Negative edge indicates when serial data is valid. After convert command goes high, fist cycle clocks bit 1 (MSB). The clock continues to run when convert command is high and resets low with convert command. 18 Convert Command High transition starts conversion; and should remain high during conversion. Low will reset clock and SAR logic. 19 Clock Rate Control May be used to increase clock speed, by increasing the positive portion of the clock. High is normal operation. 24 20V Input 25 10V Input 26 Comparator In Only used in bipolar mode when it is connected to bipolar offset pin through short lead with low resistance. 27 Ground Sense Ground Sense pin. (See text for use). 29 Bipolar Offset Current 20V input range allows ±10Vp-p analog input signal. Short to ground when not used. 10V input range allows 0 to –10Vp-p or ±5Vp-p input range. Bipolar offset current short to comparator In through very short lead with very low resistance for bipolar operation. Short to ground for unipolar operation. ® ADC601 4