® ADC71 16-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 16-BIT RESOLUTION ● ±0.003% MAXIMUM NONLINEARITY ● COMPACT DESIGN: 32-pin Hermetic Ceramic Package The ADC71 is a low cost, high quality, 16-bit successive approximation analog-to-digital converter. It uses laser-trimmed ICs and is packaged in a convenient 32-pin hermetic ceramic dual-in-line package. The converter is complete with internal reference, clock, comparator, and thin-film scaling resistors, which allow selection of analog input ranges of ±2.5V, ±5V, ±10V, 0 to +5V, 0 to +10V and 0 to +20V. ● CONVERSION SPEED: 50µs max Data is available in parallel and serial form with corresponding clock and status output. All digital inputs and outputs are TTL-compatible. Power supply voltages are ±15VDC and +5VDC. Reference Parallel Digital Output Short Cycle Convert Command Ref Out (+6.3V) 16-Bit D/A Converter 16-Bit Successive Approx. Register (SAR) Range }Input Select Comparator In Clock Out Clock Status International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1060A Printed in U.S.A. December, 1993 SPECIFICATIONS ELECTRICAL At +25°C and rated power supplies, unless otherwise noted. ADC71J, K MODEL MIN ADC71A, B TYP MAX RESOLUTION MIN TYP 16 INPUTS ANALOG Voltage Ranges: Bipolar Unipolar Input Impedance (Direct Input) 0 to +5V, ±2.5V 0 to +10V, ±5.0V 0 to +20V, ±10V MAX UNITS 16 Bits ±2.5, ±5, ±10 0 to +5, 0 to +10, 0 to +20 ±2.5, ±5, ±10 0 to +5, 0 to +10, 0 to +20 V V 2.5 5 10 2.5 5 10 kΩ kΩ kΩ DIGITAL(1) Convert Command Positive pulse 50ns wide (min) trailing edge (“1” to “0” initiates conversion) 1 TTL Load Logic Loading TRANSFER CHARACTERISTICS ACCURACY Gain Error(2) Offset(2): Unipolar Bipolar Linearity Error: K, B J, A Inherent Quantization Error Differential Linearity Error ±1/2 ±0.003 POWER SUPPLY SENSITIVITY ±15VDC +5VDC 0.003 0.001 ±0.1 ±0.05 ±0.1 ±0.2 ±0.1 ±0.2 ±0.003 ±0.006 50 5 DRIFT Gain Offset: Unipolar Bipolar Linearity No Missing Codes Temp Range J, A (13 Bits) K, B (14 Bits) POWER SUPPLY REQUIREMENTS Power Consumption Rated Voltage, Analog Rated Voltage, Digital Supply Drain +15VDC Supply Drain –15VDC Supply Drain +5VDC TEMPERATURE RANGE Specification Operating (Derated Specs) Storage 50 ±15 ±4 ±10 ±3 % % of FSR(3) % of FSR % of FSR % of FSR LSB % of FSR % of FSR/%VS % of FSR/%VS * ±10 ±2 ±8 ±2 µs min * ±2 ±10 ±2 ppm/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C +85 +85 °C °C 2 * TTL Loads 2 Logic “1” During Conversion 2 2 280 * TTL Loads 2 2 TTL Loads TTL Loads kHz 6.6 V ±200 * µA ppm/°C * * * * * mW VDC VDC mA mA mA +85 +125 +125 °C °C °C 0 0 OUTPUT DIGITAL DATA (All Codes Complementary) Parallel Output Codes(5): Unipolar Bipolar Output Drive Serial Data Code (NRZ) Output Drive Status Status Output Drive Clock Output Drive Frequency(7) INTERNAL REFERENCE VOLTAGE Max External Current with No Degradation of Specs Temp Coefficient ±1/2 ±0.003 ±0.2 ±0.1 ±0.2 ±0.003 ±0.006 0.003 0.001 CONVERSION TIME(4) 14 Bits WARM-UP TIME ±0.1 ±0.05 ±0.1 +70 +70 * ±5 –25 –25 CSB COB, CTC(6) CSB, COB 6.0 6.3 6.6 * 6.0 6.3 ±200 ±10 ±11.4 +4.75 655 ±15 +5 +10 –28 +17 0 –25 –55 ±16 +4.75 +15 –35 +20 * * +70 +85 +125 –25 –55 –55 655 * * * * * NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = +0.4V, max Logic “1” = 2.4V min. (2) Adjustable to zero. (3) FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. (4) Conversion time may be shortened with “Short Cycle” set for lower resolution, see “Additional Connections Required” section. (5) See Table I. CSB = Complementary Straight Binary. COB = Complementary Offset Binary. CTC = Complementary Two’s Complement. (6) CTC coding obtained by inverting MSB (Pin 1). ® ADC71 2 PIN CONFIGURATION Top View DIP 32 Short Cycle Bit 2 2 Bit 3 3 31 Convert Command 30 Bit 4 +5VDC Supply 4 29 Gain Adjust Bit 5 5 28 +15VDC Supply Bit 6 6 27 Comparator In Bit 7 7 26 Bipolar Offset Bit 8 8 25 10V Bit 9 9 24 20V Bit 10 10 23 Ref Out 6.3V Bit 11 11 22 Analog Common(1) Bit 12 12 21 –15VDC Supply (LSB for 13 bits) Bit 13 13 20 Clock Out (LSB for 14 bits) Bit 14 14 19 Digital Common Bit 15 15 18 Status Bit 16 16 17 Serial Out Reference 16-Bit D/A Converter 1 16-Bit SAR (MSB) Bit 1 6.3kΩ 5kΩ 5kΩ Comparator Clock NOTE: (1) Metal lid of package is connected to pin 22 (Analog Common). ABSOLUTE MAXIMUM SPECIFICATIONS PACKAGE INFORMATION +VCC to Common .................................................................... 0 to +16.5V –VCC to Common .................................................................. 0V to –16.5V +VDD to Common ....................................................................... 0V to +7V Analog Common to Digital Common ............................................... ±0.5V Logic Inputs to Common ........................................................... 0V to VDD Maximum Power Dissipation ....................................................... 1000mW Lead Temperature (10s) .................................................................. 300°C MODEL ADC71JG ADC71KG ADC71AG ADC71BG PACKAGE DRAWING NUMBER(1) PACKAGE 32-Pin 32-Pin 32-Pin 32-Pin Hermetic Hermetic Hermetic Hermetic DIP DIP DIP DIP 172-5 172-5 172-5 172-5 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL ADC71JG ADC71KG ADC71AG ADC71BG TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C –25°C to +85°C –25°C to +85°C NONLINEARITY ±0.006% ±0.003% ±0.006% ±0.003% FSR FSR FSR FSR The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADC71 Convert Command Maximum Throughput Time(2) Conversion Time (1) Internal Clock Status (EOC) “0” MBS Bit 2 “1” Bit 3 “1” “0” Bit 4 “0” Bit 5 Bit 6 “1” Bit 7 “1” Bit 8 “1” “0” Bit 9 Bit 10 “1” Bit 11 “1” “0” Bit 12 Bit 13 “1” “0” Bit 14 “0” Bit 15 Bit 16 Serial Data Out LSB MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 “1” 16 “0” “1” “1” “0” “0” “1” “1” “1” “0” “1” “1” “0” “1” “0” “0” “1” NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is initiated by the “trailing edge” of the convert command. (2) 57µs for 16 bits. FIGURE 1. ADC71 Timing Diagram. Serial Out 40-125ns 40-125ns Bit 16 Valid Bit 16 Clock Out 40-125ns Status FIGURE 2. Timing Relationship of Serial Data to Clock. Binary (BIN) Output FIGURE 3. Timing Relationship of Valid Data to Status. INPUT VOLTAGE RANGE AND LSB VALUES Analog Input Voltage Range ±10V ±5V ±2.5V 0 to +10V 0 to +5V 0 to +20V COB(1) or CTC(2) COB(1) or CTC(2) COB(1) or CTC(2) CSB(3) CSB(3) CSB(3) FSR 2n n = 12 n = 13 n = 14 20V 2n 4.88mV 2.44mV 1.22mV 10V 2n 2.44mV 1.22mV 610µV 5V 2n 1.22mV 610µV 305µV 10V 2n 2.44mV 1.22mV 610µV 5V 2n 1.22mV 610µV 305µV 20V 2n 4.88mV 2.44mV 1.22mV +Full Scale Mid Scale –Full Scale +10V–3/2LSB 0 –10V +1/2LSB +5V–3/2LSB 0 –5V +1/2LSB +2.5V–3/2LSB 0 –2.5V +1/2LSB +10V–3/2LSB +5V 0 +1/2LSB +5V–3/2LSB +2.5V 0 +1/2LSB +20V–3/2LSB +10V 0 +1/2LSB Defined As: Code Designation One Least Significant Bit (LSB) Transition Values MSB LSB 000 ... 000(4) 011 ... 111 111 ... 110 NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Two’s Complement—obtained by inverting the most significant bit MSB (pin 1). (3) CSB = Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified. TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions. ® ADC71 4 TYPICAL PERFORMANCE CURVES At +25°C and rated power supplies unless otherwise noted. POWER SUPPLY REJECTION vs SUPPLY RIPPLE FREQUENCY % of FSR Error per % of Change In VSUPPLY GAIN DRIFT ERROR (% OF FSR) vs TEMPERATURE +0.10 Gain Drift Error (% of FSR) +0.08 +0.06 ADC71AG, BG ADC71JG,KG +0.04 +0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 –25°C 0°C +25°C +70°C +85°C The accuracy of a successive approximation A/D converter is described by the transfer function shown in Figure 1. All successive approximation A/D converters have an inherent Quantization Error of ±1/2 LSB. The remaining errors in the A/D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure 1) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of A/D Digital Output (COB Code)(1) 0.01 +15VDC 0.006 0.004 +5VDC 0.002 0.001 10 100 1k Frequency (Hz) 10k 100k converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the A/D converter. A Differential Linearity error of ±1/2 LSB means that the width of each bit step over the range of the A/D converter is 1 LSB, ±1/2 LSB. The ADC71 is monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown guarantees that these converters will have no missing codes over a specified temperature range when short-cycled for 14-bit operation. TIMING CONSIDERATIONS The timing diagram (Figure 2) assumes an analog input such that the positive true digital word 1001 1000 1001 0110 exists. The output will be complementary as shown in Figure 2 (0110 0111 0110 1001 is the digital output). Figures 3 and 4 are timing diagrams showing the relationship of serial data to clock and valid data to status. All Bits On Gain Error 0000 ... 0001 0111 ... 1101 DEFINITION OF DIGITAL CODES Parallel Data Two binary codes are available on the ADC71 parallel output; they are complementary (logic “0” is true) straight binary (CSB) for unipolar input signal ranges and complementary offset binary (COB) for bipolar input signal ranges. Complementary two’s complement (CTC) may be obtained by inverting MSB (Pin 1). –1/2LSB 0111 ... 1110 0111 ... 1111 1000 ... 0001 0.02 1 DISCUSSION OF PERFORMANCE 1000 ... 0000 –15VDC 0.04 NOTE: Pages 4&5 were switched for Abridged Version for '96 data book. Temperature (°C) 0000 ... 0000 0.1 0.06 +1/2LSB Offset Error 1111 ... 1110 All Bits Off 1111 ... 1111 Analog Input –FSR/2 eIN On Table I shows the LSB, transition values, and code definitions for each possible analog input signal range for 12-, 13and 14-bit resolutions. Figure 5 shows the connections for 14-bit resolution, parallel data output, with ±10V input. +FSR/2–1LSB eIN Off NOTE: (1) See Table I for Digital Code Definitions. FIGURE 1. Input vs Output for an Ideal Bipolar A/ D Converter. ® 5 ADC71 MSB 1 32 2 31 Dotted Lines Are External Connections 3 Logic Output 14 Bits 4 NC 30 28 6 27 7 26 ADC71 Offset Convert Command From Control Logic Adjust +5VDC 270kΩ 29 5 8 0.01µF(1) 1.8MΩ Gain Adjust Bipolar Offset 1µF 10kΩ to 100kΩ 25 9 24 10 23 NC 11 22 12 21 13 20 14 19 15 18 16 17 NC +15VDC + 10kΩ to 100kΩ + + 1µF –15VDC 1µF Digital Common Status Output to Control Logic Analog Input ±10V Analog Common NOTE: (1) Capacitor should be connected even if external gain adjust is not used. FIGURE 5. ADC71 Connections for: ±10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output. SERIAL DATA Two straight binary (complementary) codes are available on the serial output line: CSB and COB. The serial data is available only during conversion and appears with MSB occurring first. The serial data is synchronous with the internal clock as shown in the timing diagrams of Figures 2 and 3. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. +15VDC (a) 1.8MΩ 27 10kΩ to 100kΩ Offset Adjust Comparator In –15VDC +15VDC (b) DISCUSSION OF SPECIFICATIONS 27 180kΩ Comparator In 180kΩ 22kΩ –15VDC The ADC71 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an A/D converter are linearity, drift, gain and offset errors. This ADC is factory-trimmed and tested for all critical key specifications. FIGURE 6. Two Methods of Connecting Optional Offset Adjust with a 0.4% of FSR of Adjustment. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±0.1% of FSR (typically ±0.05% for unipolar offset) at 25°C. These errors may be trimmed to zero by connecting external trim potentiometers as shown in Figures 6 and 7. +15VDC 29 270kΩ Gain Adjust 0.01µF 10kΩ to 100kΩ Gain Adjust –15VDC 22 POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The power supply sensitivity is specified for ±0.003% of FSR/ %∆VS for ±15V supplies and ±0.001% of FSR/%∆S for +5 supplies. Normally, regulated power supplies with 1% or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling and Figure 8. Analog Common FIGURE 7. Connecting Optional Gain Adjust with a 0.2% Range of Adjustment. ® ADC71 10kΩ to 100kΩ Offset Adjust 6 +5VDC Direct Input –15VDC 21 30 24 1µF + 22 + Analog Common 1µF Digital Common 25 22 1µF 19 R2 5kΩ R1 5kΩ Comp In + 27 28 6.3kΩ 26 Bipolar Offset +15VDC FIGURE 8. Recommended Power Supply Decoupling. VREF From D/A Converter Comparator to Logic FIGURE 9. ADC71 Input Scaling Circuit. LAYOUT AND OPERATING INSTRUCTIONS Layout Precautions Analog and digital common are not connected internally in the ADC71 but should be connected together as close to the unit as possible, preferably to a large plane under the ADC. If these grounds must be run separately, use wide conductor patterns and a 0.01µF to 0.1µF non-polarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital commons returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (Pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common patterns. OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figure 6 and 7. Multiturn potentiometers with 100ppm/°C or better TCRs are recommended for minimum drift over temperature and time. These pots may be any value from 10kΩ to 100kΩ. All resistors should be 20% carbon or better. Pin 29 (Gain Adjust) and Pin 27 (Offset Adjust) may be left open of no external adjustment is required. ADJUSTMENT PROCEDURE OFFSET — Connect the Offset potentiometer (make sure R1 is as close to pin 27 as possible) as shown in Figure 6. Sweep the input through the end point transition voltage that should cause an output transition to all bits Off (EIN). POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum capacitors as shown in Figure 8 to obtain noise free operation. These capacitors should be located close to the ADC. Adjust the Offset potentiometer until the actual end point transition voltage occurs at EIN. The ideal transition voltage values of the input are given in Table I. INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the A/D converter. Connect the input signal as shown in Table II. See Figure 9 for circuit details. GAIN — Connect the Gain Adjust potentiometer as shown in Figure 7. Sweep the input through the end point transition voltage that should cause an output transition to all bits on (EIN). Adjust the Gain potentiometer until the actual end point transition voltage occurs at EIN. Table I details the transition voltage levels required. CONNECT INPUT SIGNAL RANGE ±10V ±5V ±2.5V 0 to +5V 0 to +10V 0 to +20V OUTPUT CODE CONNECT PIN 26 TO PIN CONNECT PIN 24 TO INPUT SIGNAL TO PIN COB or CTC(1) COB or CTC(1) COB or CTC(1) CSB CSB CSB 27 27 27 22 22 22 Input Signal Open Pin 27 Pin 27 Open Input Signal 24 25 25 25 25 24 CONVERT COMMAND CONSIDERATIONS Convert command resets the converter whenever taken high. This insures a valid conversion on the first conversion after power-up. Convert command must stay low during a conversion unless it is desired to reset the converter during a conversion. NOTE: (1) Obtained by inverting MSB pin 1. ADDITIONAL CONNECTIONS REQUIRED The ADC71 may be operated at faster speeds by connecting the Short-Cycle Input, pin 32, as shown in Table III. Conversion speeds, linearity, and resolutions are shown for reference. TABLE II. ADC71 Input Scaling Connections. ® 7 ADC71 OUTPUT DRIVE Normally all ADC71 logic outputs will drive two standard TTL loads; however, if long digital lines must be driver, external logic buffers are recommended. RESOLUTION (Bits) 16 14 13 12 Open Pin 15 Pin 14 Pin 13 Maximum Conversion Speed (µs)(1) 57 50 46.5 43 Maximum Nonlinearity at 25°C (% of FSR) 0.003(2) 0.003(2) 0.006 0.006 Connect Pin 32 to HEAT DISSIPATION The ADC71 dissipates approximately 0.6W (typical) and the packages have a case-to-ambient thermal resistance (θCA) of 25°C/W. For operation above 85°C, θCA should be lowered by a heat sink or by forced air over the surface of the package. See Figure 10 for θCA requirement above 85°C. If the converter is mounted on a PC card, improved thermal contact with the copper ground plane under the case can be achieved using a silicone heat sink compound. On a 0.062" thick PC card with a 16 square in (min) area, this techniques will allow operation to 85°C. NOTES: (1) Max conversion time to maintain specified nonlinearity error. (2) BH and KH models only. TABLE III. Short-Cycle Connections and Specifications for 12- to 14-Bit Resolutions. θCA (°C/W) 25 10 0 60 70 80 90 100 Ambient Temperature (°C) FIGURE 10. θCA Requirement Above 85°C. ® ADC71 8 110 125 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.