DA C8 552 DAC8552 SLAS430 – JULY 2006 16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • DESCRIPTION Relative Accuracy: 4LSB Glitch Energy: 0.15nV-s MicroPower Operation: 155µA per Channel at 2.7V Power-On Reset to Zero-Scale Power Supply: 2.7V to 5.5V 16-Bit Monotonic Over Temperature Settling Time: 10µs to ±0.003% FSR Ultra-Low AC Crosstalk: –100dB Typ Low-Power Serial Interface With Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Double-Buffered Input Architecture Simultaneous or Sequential Output Update and Powerdown Available in a Tiny MSOP-8 Package The DAC8552 is a 16-bit, dual channel, voltage output digital-to-analog converter (DAC) offering low power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30MHz for VDD = 5V. The DAC8552 requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8552 provides a flexible power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 700nA at 5V. The low-power consumption of this device in normal operation makes it ideally suited for portable battery-operated equipment and other low-power applications. The power consumption is 0.5mW per channel at 2.7V, reducing to 1µW in power-down mode. APPLICATIONS • • • • • • Portable Instrumentation Closed-Loop Servo Control Process Control Data Acquisition Systems Programmable Attenuation PC Peripherals The DAC8552 is available in a MSOP-8 package with a specified operating temperature range of –40°C to +105°C. VDD VREF Data Buffer A DAC Register A DAC A VOUTA Data Buffer B DAC Register B DAC B VOUTB Channel Select Load Control 16 SYNC SCLK DIN 24-Bit, Serial-toParallel 8 Shift Register Control Logic Power-Down Control Logic 2 Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSP are trademarks of Motorola. Microwire is a trademark of National Semiconductor. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DAC8552 www.ti.com SLAS430 – JULY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION (1) PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) PACKAGE LEAD PACKAGE DESIGNATOR SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING DAC8552 ±12 ±1 MSOP-8 DGK –40°C to +105°C D82 (1) TRANSPORT MEDIA, QUANTITY ORDERING NUMBER DAC8552IDGKT Tape and Reel, 250 DAC8552IDGKR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD to GND –0.3V to 6V Digital input voltage to GND –0.3V to VDD + 0.3V VOUTA or VOUTB to GND –0.3V to VDD + 0.3V Operating temperature range –40°C to +105°C Storage temperature range –65°C to +150°C Junction temperature (TJ max) +150°C Power dissipation (TJ max – TA)/θJA θJA thermal impedance 206°C/W θJC thermal impedance 44°C/W (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±4 ±12 LSB ±0.35 ±1 LSB ±2.5 ±12 mV STATIC PERFORMANCE (1) Resolution 16 Relative accuracy Measured by line passing through codes 513 and 64741 Differential nonlinearity 16-bit monotonic Zero code error Measured by line passing through codes 485 and 64741 Bits ±5 Zero code error drift µV/°C Full-scale error Measured by line passing through codes 485 and 64741 ±0.1 ±0.5 % of FSR Gain error Measured by line passing through codes 485 and 64741 ±0.08 ±0.2 % of FSR ±1 Gain temperature coefficient PSRR Output unloaded ppm of FSR/°C 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage range (1) (2) 2 0 Linearity calculated using a reduced code range of 513 to 64741. Output unloaded. Specified by design and characterization, not production tested. Submit Documentation Feedback VREF V DAC8552 www.ti.com SLAS430 – JULY 2006 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted) PARAMETER Output voltage settling time TEST CONDITIONS MIN To ±0.003% FSR 0200H to FD00H, RL = 2kΩ; 0pF < CL < 200pF RL = 2kΩ; CL = 500pF TYP MAX 8 10 µs 12 Slew rate 1.8 Capacitive load stability UNIT RL = ∞ V/µs 470 pF RL = 2kΩ 1000 Code change glitch impulse 1LSB change around major carry 0.15 nV-s Digital feedthrough 50kΩ series resistance on digital lines 0.15 nV-s DC crosstalk Full-scale swing on adjacent channel. VDD = 5V, VREF = 4.096V 0.25 LSB AC crosstalk 1kHz Sine wave –100 dB DC output impedance At mid-point input 1 Ω Short circuit current Power-up time VDD = 5V 50 VDD = 3V 20 Coming out of power-down mode VDD = 5V 2.5 µs Coming out of power-down mode VDD = 3V 5 µs mA AC PERFORMANCE SNR 95 BW = 20kHz, VDD = 5V, fOUT = 1kHz, 1st 19 harmonics removed for SNR calculation THD SFDR -85 dB 87 SINAD 84 REFERENCE INPUT Reference current VREF = VDD = 5.5V 90 120 VREF = VDD = 3.6V 60 100 Reference input range 0 Reference input impedance LOGIC INPUTS VDD 62 µA V kΩ (3) ±1 Input current VINL, Input LOW voltage VINH, Input HIGH voltage VDD = 5V 0.8 VDD = 3V 0.6 VDD = 5V 2.4 VDD = 3V 2.1 µA V V Pin capacitance 3 pF 5.5 V POWER REQUIREMENTS VDD 2.7 IDD (normal mode) VDD = 3.6V to 5.5V VDD = 2.7V to 3.6V Input Code = 32768, no load, does not include reference current VIH = VDD and VIL = GND 340 500 310 480 0.7 2 0.4 2 µA IDD (all power-down modes) VDD = 3.6V to 5.5V VDD = 2.7V to 3.6V VIH = VDD and VIL = GND µA POWER EFFICIENCY IOUT/IDD ILOAD = 2mA, VDD = 5V 89% TEMPERATURE RANGE Specified performance (3) –40 +105 °C Specified by design and characterization, not production tested. Submit Documentation Feedback 3 DAC8552 www.ti.com SLAS430 – JULY 2006 PIN CONFIGURATION DGK PACKAGE MSOP-8 (Top View) VDD 1 VREF 2 VOUTB VOUTA 8 GND 7 DIN 3 6 SCLK 4 5 SYNC DAC8552 PIN DESCRIPTIONS PIN 4 NAME FUNCTION 1 VDD Power supply input, 2.7V to 5.5V 2 VREF Reference voltage input 3 VOUTB Analog output voltage from DAC B 4 VOUTA Analog output voltage from DAC A 5 SYNC Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the 8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8552). Schmitt-Trigger logic input. 6 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input. 7 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input. 8 GND Ground reference point for all circuitry on the part. Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 SERIAL WRITE OPERATION t9 t1 SCLK 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 TIMING CHARACTERISTICS DB0 DB23 (1) (2) VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted) PARAMETER t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 24th SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 24th SCLK falling edge to SYNC falling edge (1) (2) (3) TEST CONDITIONS MIN VDD = 2.7V to 3.6V 50 VDD = 3.6V to 5.5V 33 VDD = 2.7V to 3.6V 13 VDD = 3.6V to 5.5V 13 VDD = 2.7V to 3.6V 22.5 VDD = 3.6V to 5.5V 13 VDD = 2.7V to 3.6V 0 VDD = 3.6V to 5.5V 0 VDD = 2.7V to 3.6V 5 VDD = 3.6V to 5.5V 5 VDD = 2.7V to 3.6V 4.5 VDD = 3.6V to 5.5V 4.5 VDD = 2.7V to 3.6V 0 VDD = 3.6V to 5.5V 0 VDD = 2.7V to 3.6V 50 VDD = 3.6V to 5.5V 33 VDD = 2.7V to 5.5V 100 TYP MAX UNIT ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram. Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V. Submit Documentation Feedback 5 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. 8 6 4 2 0 -2 -4 -6 -8 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE LE (LSB) VDD = 5V, VREF = 4.9V, TA = +25°C Channel A Output 1.0 0.5 0.5 0 -0.5 -1.0 8 6 4 2 0 -2 -4 -6 -8 8192 16384 24576 32768 40960 49152 Digital Input Code 0 -0.5 57344 65536 0 8192 16384 24576 32768 40960 49152 Digital Input Code Figure 2. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE LE (LSB) VDD = 2.7V, VREF = 2.5V, TA = +25°C Channel A Output 8 6 4 2 0 -2 -4 -6 -8 1.0 1.0 0.5 0.5 0 -0.5 -1.0 VDD = 2.7V, VREF = 2.5V, TA = +25°C Channel B Output 0 -0.5 -1.0 0 8192 16384 24576 32768 40960 49152 Digital Input Code 57344 65536 0 8192 16384 24576 32768 40960 49152 Digital Input Code Figure 3. ZERO-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 7.5 VDD = 5V VREF = 4.99V 5.0 Zero-Scale Error − mV Zero-Scale Error − mV 5.0 2.5 CH B 0.0 −2.5 CH A −5.0 −7.5 −40 57344 65536 Figure 4. 7.5 6 57344 65536 Figure 1. DLE (LSB) LE (LSB) VDD = 5V, VREF = 4.9V, TA = +25°C Channel B Output -1.0 0 DLE (LSB) 8 6 4 2 0 -2 -4 -6 -8 1.0 DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE VDD = 2.7V VREF = 2.69V 2.5 CH B 0.0 −2.5 CH A −5.0 0 40 80 120 −7.5 −40 0 40 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 5. Figure 6. Submit Documentation Feedback 120 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 5 5 VDD = 2.7V VREF = 2.69V CH B Full-Scale Error − mV Full-Scale Error − mV VDD = 5V VREF = 4.99V 0 CH A −5 −10 −40 0 40 80 CH A −5 0 40 80 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 7. Figure 8. SINK CURRENT CAPABILTY AT NEGATIVE RAIL 120 SOURCE CURRENT CAPABILITY AT POSITIVE RAIL 0.150 6.0 VO − Output Voltage − V VREF = VDD − 10mV DAC loaded with 0000H 0.125 VO − Output Voltage − V 0 −10 −40 120 CH B 0.100 VDD = 2.7V 0.075 VDD = 5.5V 0.050 0.025 0.000 5.6 5.2 4.8 VREF = VDD − 10mV DAC loaded with FFFFH VDD = 5.5V 4.4 4.0 0 2 4 6 8 10 0 2 ISINK − Sink Current − mA 4 6 8 10 ISOURCE − Source Current − mA Figure 9. Figure 10. SOURCE CURRENT CAPABILITY AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 600 3.0 IDD − Supply Current − µA VO − Output Voltage − V Reference Current Included 2.7 2.4 2.1 VDD = 2.7 V VREF = VDD − 10mV DAC loaded with FFFFH 1.8 500 VDD = VREF = 5.5V 400 VDD = VREF = 3.6V 300 200 100 0 1.5 0 2 4 6 8 ISOURCE − Source Current − mA 10 0 Figure 11. 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 12. Submit Documentation Feedback 7 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs TEMPERATURE 600 600 IDD − Supply Current − µA Reference Current Included 500 IDD − Supply Current − µA VREF = VDD, All DAC’s Powered, Reference Current Included, No Load 550 500 450 400 350 300 VDD = VREF = 5.5V 400 200 100 250 200 2.70 3.05 3.40 3.75 4.10 4.45 4.80 5.15 0 −40 5.50 80 Figure 13. Figure 14. 120 SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 2400 IDD − Supply Current − µA TA = 25°C, SYNC Input (All other inputs = GND) CH A powered up; All other channels in powerdown 700 600 500 VDD = VREF = 2.7V 400 300 200 0 0.0 0.5 1.0 1.5 2.0 1600 VDD = VREF = 5.5V 1200 800 400 0 0.0 2.5 1.0 2.0 3.0 4.0 5.0 VLOGIC − Logic Input Voltage − V VLOGIC − Logic Input Voltage − V Figure 15. Figure 16. POWER SPECTRAL DENSITY TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY −40 THD − Total Harmonic Distortion − dB VDD = 5V, VREF = 4.096V fOUT = 1kHz fCLK = 1MSPS −10 −30 −50 −70 −90 −110 −130 0 TA = 25°C, SYNC Input (All other inputs = GND) CH A powered up; All other channels in powerdown 2000 100 5000 10000 15000 20000 VDD = 5V, VREF = 4.9V −50 −1dB FSR Digital Input, fS = 1MSPS Measurement Bandwidth = 20kHz −60 −70 THD 2nd Harmonic −80 3rd Harmonic −90 −100 0 1 2 3 Output Tone − kHz f − Frequency − Hz Figure 17. 8 40 TA − Free-Air Temperature − °C SUPPLY CURRENT vs LOGIC INPUT VOLTAGE IDD − Supply Current − µA 0 VDD − Supply Voltage − V 800 Gain − dB VDD = VREF = 3.6V 300 Figure 18. Submit Documentation Feedback 4 5 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY OUTPUT NOISE DENSITY 350 VDD = 5 V VREF = 4.096 Code = 7FFF No Load Hz VDD = VREF = 5V 96 −1dB FSR Digital Input, fS = 1MSPS Measurement Bandwidth = 20kHz 94 V n − Voltage Noise − nV/ SNR − Signal-to-Noise Ratio − dB 98 92 90 88 86 84 0 0.5 1 1.5 2 2.5 3 3.5 f − Output Frequency − kHz 4 4.5 5 300 250 200 150 100 100 1000 10000 100000 f − Frequency − Hz Figure 19. Figure 20. FULL-SCALE SETTLING TIME: 5V RISING EDGE FULL-SCALE SETTLING TIME: 5V FALLING EDGE Trigger Pulse 5V/div VDD = 5V VREF = 4.096V From Code: D000 To Code: FFFF Rising Edge 1V/div Zoomed Rising Edge 1mV/div Trigger Pulse 5V/div VDD = 5V VREF = 4.096V From Code: FFFF To Code: 0000 Falling Edge 1V/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 21. Figure 22. HALF-SCALE SETTLING TIME: 5V RISING EDGE HALF-SCALE SETTLING TIME: 5V FALLING EDGE Trigger Pulse 5V/div Trigger Pulse 5V/div VDD = 5V VREF = 4.096V From Code: CFFF To Code: 4000 Rising Edge 1V/div VDD = 5V VREF = 4.096V From Code: 4000 To Code: CFFF Zoomed Rising Edge 1mV/div Falling Edge 1V/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 23. Figure 24. Submit Documentation Feedback 9 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div VDD = 2.7V VREF = 2.5V From Code: FFFF To Code: 0000 Rising Edge 0.5V/div VDD = 2.7V VREF = 2.5V From Code: 0000 To Code: FFFF Falling Edge 0.5V/div Zoomed Rising Edge 1mV/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 25. Figure 26. HALF-SCALE SETTLING TIME: 2.7V RISING EDGE HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div VDD = 2.7V VREF = 2.5V From Code: CFFF To Code: 4000 VDD = 2.7V VREF = 2.5V From Code: 4000 To Code: CFFF Rising Edge 0.5V/div Falling Edge 0.5V/div Zoomed Rising Edge 1mV/div Time (2ms/div) Time (2ms/div) Figure 28. GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE VDD = 5V VREF = 4.096V From Code: 7FFF To Code: 8000 Glitch: 0.08nV-s VOUT (500mV/div) Figure 27. VOUT (500mV/div) 10 Zoomed Falling Edge 1mV/div VDD = 5V VREF = 4.096V From Code: 8000 To Code: 7FFF Glitch: 0.16nV-s Measured Worst Case Time (400ns/div) Time (400ns/div) Figure 29. Figure 30. Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. VDD = 5V VREF = 4.096V From Code: 8010 To Code: 8000 Glitch: 0.08nV-s VOUT (500mV/div) VDD = 5V VREF = 4.096V From Code: 8000 To Code: 8010 Glitch: 0.04nV-s GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE Time (400ns/div) Time (400ns/div) Figure 31. Figure 32. GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE VOUT (5mV/div) VDD = 5V VREF = 4.096V From Code: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case VDD = 5V VREF = 4.096V From Code: 80FF To Code: 8000 Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure 33. Figure 34. GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE VDD = 2.7V VREF = 2.5V From Code: 7FFF To Code: 8000 Glitch: 0.08nV-s VOUT (200mV/div) VOUT (200mV/div) VOUT (5mV/div) VOUT (500mV/div) GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE VDD = 2.7V VREF = 2.5V From Code: 8000 To Code: 7FFF Glitch: 0.16nV-s Measured Worst Case Time (400ns/div) Time (400ns/div) Figure 35. Figure 36. Submit Documentation Feedback 11 DAC8552 www.ti.com SLAS430 – JULY 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. 12 VDD = 2.7V VREF = 2.5V From Code: 8010 To Code: 8000 Glitch: 0.12nV-s VOUT (200mV/div) VDD = 2.7V VREF = 2.5V From Code: 8000 To Code: 8010 Glitch: 0.04nV-s GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE Time (400ns/div) Time (400ns/div) Figure 37. Figure 38. GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE VDD = 2.7V VREF = 2.5V From Code: 8000 To Code: 80FF Glitch: Not Detected Theoretical Worst Case VOUT (5mV/div) VOUT (5mV/div) VOUT (200mV/div) GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE VDD = 2.7V VREF = 2.5V From Code: 80FF To Code: 8000 Glitch: Not Detected Theoretical Worst Case Time (400ns/div) Time (400ns/div) Figure 39. Figure 40. Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 THEORY OF OPERATION DAC SECTION VREF The architecture of each channel of the DAC8552 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 41 shows a simplified block diagram of the DAC architecture. VREF 50kΩ RDIVIDER VREF 2 R 50kΩ 62kΩ DAC Register V OUT REF (+) Register String REF (−) R To Output Amplifier (2x Gain) GND Figure 41. DAC8552 Architecture The input coding for each device is unipolar straight binary, so the ideal output voltage is given by: D V A, B + V OUT REF 65536 (1) R where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. VOUTA,B refers to channel A or B. R RESISTOR STRING The resistor string section is shown in Figure 42. It is simply a divide-by-2 resistor followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then applied to the output amplifier by closing one of the switches connecting the string to the amplifier. OUTPUT AMPLIFIER Each output buffer amplifier is capable of generating rail-to-rail voltages on its output which approaches an output range of 0V to VDD (gain and offset errors must be taken into account). Each buffer is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. SERIAL INTERFACE The DAC8552 uses a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI™ and QSP™, and Microwire™ interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. Figure 42. Resistor String The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8552 compatible with high speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the shift register is locked. Further clocking does not change the shift register data. Once 24 bits are locked into the shift register, the 8 MSBs are used as control bits and the 16 LSBs are used as data. After receiving the 24th falling clock edge, the DAC8552 decodes the 8 control bits and 16 data bits to perform the required function, without waiting for a SYNC rising edge. A new SPI sequence starts at the next falling edge of SYNC. A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs. After the 24th falling edge of SCLK is received, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next Submit Documentation Feedback 13 DAC8552 www.ti.com SLAS430 – JULY 2006 cycle. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible. (See the Typical Characteristics section for the Supply Current vs Logic Input Voltage transfer characteristic curve). INPUT SHIFT REGISTER The input shift register of the DAC8552 is 24 bits wide (see Figure 45) and is made up of 8 control bits (DB16–DB23) and 16 data bits (DB0–DB15). The first two control bits (DB22 and DB23) are reserved and must be '0' for proper operation. LDA (DB20) and LD B (DB21) control the updating of each analog output with the specified 16-bit data value or powerdown command. Bit DB19 is a Don't Care bit, which does not affect the operation of the DAC8552 and can be '1' or '0'. The following control bit, Buffer Select (DB18), controls the destination of the data (or power-down command) between DAC A and DAC B. The final two control bits, PD0 (DB16) and PD1 (DB17), select the power-down mode of one or both of the DAC channels. The four modes are normal mode or any one of three power-down modes. A more complete description of the operational modes of the DAC8552 can be found in the Power-Down Modes section. The remaining sixteen bits of the 24-bit input word make up the data bits. These are transferred to the specified Data Buffer or DAC Register, depending on the command issued by the control byte, on the 24th falling edge of SCLK. See Table 2 and Table 3 for more information. Resistor String DAC Amplifier Power-Down Circuitry VOUTA,B Resistor Network Figure 43. Output Stage During Power-Down (High Impedance) SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents or a change in the operating mode occurs (see Figure 44). 14 POWER-ON RESET The DAC8552 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. POWER-DOWN MODES The DAC8552 utilizes four modes of operation. These modes are accessed by setting two bits (PD1 and PD0) in the control Load action to one or both DACs. Table 1 shows how the state of the bits correspond to the register and performing a mode of operation of each channel of the device. (Each DAC channel can be powered down simultaneously or independently of each other. Power-down occurs after proper data is written into PD0 and PD1 and a Load command occurs.) See the Operation Examples section for additional information. Table 1. Modes of Operation for the DAC8552 PD1 (DB17) PD0 (DB16) 0 0 OPERATING MODE Normal Operation — — Power-down modes 0 1 Output typically 1kΩ to GND 1 0 Output typically 100kΩ to GND 1 1 High impedance When both bits are set to 0, the device works normally with a typical power consumption of 450µA at 5V. For the three power-down modes, however, the supply current falls to 700nA at 5V (400nA at 3V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: The output is connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 43. All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 and PD1 are set to 0, new data is written to the Data Buffer, and the DAC channel receives a Load command. The time to exit power-down is typically 2.5µs for VDD = 5V and 5µs for VDD = 3V (see the Typical Characteristics). Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 24th Falling Edge SCLK 1 24th Falling Edge 2 1 2 SYNC Invalid Write − Sync Interrupt: SYNC HIGH before 24th Falling Edge DIN DB23 DB22 Valid Write - Buffer/DAC Update: SYNC HIGH after 24th Falling Edge DB0 DB23 DB22 DB1 DB0 Figure 44. Interrupt and Valid SYNC Timing DB23 DB12 0 0 LDB LDA X Buffer Select PD1 PD0 D15 D14 D13 D12 DB11 DB0 D11 D10 D9 D8 D7 D6 D5 D5 D3 D2 D1 D0 Figure 45. DAC8552 Data Input Register Format Table 2. Control Matrix D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13–D0 Reserved Reserved Load B Load A Don't Care Buffer Select PD1 PD0 MSB MSB-1 MSB-2... LSB 0 0 DESCRIPTION 0 = A, 1=B (Always Write 0) 0 0 0 0 X # 0 0 0 0 X # 0 0 0 1 X # 0 0 0 1 X 0 See Table 3 0 0 0 1 X 1 See Table 3 0 0 1 0 X # 0 0 1 0 X 0 See Table 3 X WR Buffer A w/Power-Down Command and LOAD DAC B 0 0 1 0 X 1 See Table 3 X WR Buffer B w/Power-Down Command and LOAD DAC B (DAC B Powered Down) 0 0 1 1 X # 0 0 1 1 X 0 See Table 3 X WR Buffer A w/Power-Down Command and Load DACs A and B (DAC A Powered Down) 0 0 1 1 X 1 See Table 3 X WR Buffer B w/Power-Down Command and Load DACs A and B (DAC B Powered Down) See Table 3 0 0 0 0 0 0 Data WR Buffer # w/Data X WR Buffer # w/Power-down Command Data WR Buffer # w/Data and Load DAC A X WR Buffer A w/Power-Down Command and LOAD DAC A (DAC A Powered Down) X WR Buffer B w/Power-Down Command and LOAD DAC A Data WR Buffer # w/Data and Load DAC B Data WR Buffer # w/Data and Load DACs A and B Table 3. Power-Down Commands D17 D16 PD1 PD0 0 1 1 0 100kΩ 1 1 High Impedance OUTPUT IMPEDANCE POWER DOWN COMMANDS 1kΩ Submit Documentation Feedback 15 DAC8552 www.ti.com SLAS430 – JULY 2006 OPERATION EXAMPLES Example 1: Write to Data Buffer A; Through Buffer B; Load DACA Through DACB Simultaneously • 1st — Write to DataBuffer A: • Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0 0 0 0 0 X 0 0 0 D15 — D1 D0 2nd — Write to Data Buffer B and Load DAC A and DAC B simultaneously: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0 0 0 1 1 X 1 0 0 D15 — D1 D0 The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK edge after SYNC LOW.) Example 2: Load New Data to DACA and DACB Sequentially • 1st — Write to Data Buffer A and Load DAC A: DACA output settles to specified value upon completion: • Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0 0 0 0 1 X 0 0 0 D15 — D1 D0 2nd — Write to Data Buffer B and Load DAC B: DACB output settles to specified value upon completion: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 — DB1 DB0 0 0 1 0 X 1 0 0 D15 — D1 D0 After completion of the 1st write cycle, the DACA analog output settles to the voltage specified; upon completion of write cycle 2, the DACB analog output settles. Example 3: Power-Down DACA to 1kΩ and Power-Down DACB to 100kΩ Simultaneously • 1st — Write power-down command to Data Buffer A: • Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 0 0 X 0 0 1 DB15 — DB1 DB0 Don't Care 2nd — Write power-down command to Data Buffer B and Load DACA and DACB simultaneously: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 1 1 X 1 1 0 DB15 — DB1 DB0 Don't Care The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon completion of the 2nd write sequence. Example 4: Power-Down DACA and DACB to High-Impedance Sequentially: • 1st — Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z: • Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 0 1 X 0 1 1 DB15 — DB1 DB0 Don't Care 2nd — Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 1 0 X 1 1 1 DB15 — DB1 DB0 Don't Care The DACA and DACB analog outputs sequentially power-down to high-impedance upon completion of the 1st and 2nd write sequences, respectively. 16 Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 MICROPROCESSOR INTERFACING DAC8552 to 8051 INTERFACE DAC8552 to 68HC11 INTERFACE Figure 46 shows a serial interface between the DAC8552 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8552, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8552, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second and third write cycle is initiated to transmit the remaining data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which presents the LSB first, while the DAC8552 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and mirror the data as needed Figure 48 shows a serial interface between the DAC8552 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8552, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram. DAC8552 (1) 80C51/80L51(1) P3.3 SYNC TXD SCLK RXD DIN (1)Additional pins omitted for clarity. Figure 46. DAC8552 to 80C51/80L51 Interface DAC8552 (1) 68HC11(1) PC7 SYNC SCK SCLK MOSI DIN (1)Additional pins omitted for clarity. Figure 48. DAC8552 to 68HC11 Interface The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8552, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure. DAC8552 to TMS320 DSP INTERFACE DAC8552 to Microwire INTERFACE Figure 47 shows an interface between the DAC8552 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8552 on the rising edge of the SK signal. Figure 49 shows the connections between the DAC8552 and a TMS320 digital signal processor. By decoding the FSX signal, multiple DAC8552s can be connected to a single serial port of the DSP. Positive Supply DAC8552 VDD MicrowireTM DAC8552(1) 0.1µF CS SYNC TMS320 DSP SK SCLK FSX SO DIN DX CLKX (1) Additional pins omitted for clarity. 10µF SYNC DIN VOUTA Output A VOUTB Output B SCLK VREF 0.1µF Microwire is a registered trademark of National Semiconductor. 1µF to 10µF Reference Input GND Figure 47. DAC8552 to Microwire Interface Figure 49. DAC8552 to TMS320 DSP Submit Documentation Feedback 17 DAC8552 www.ti.com SLAS430 – JULY 2006 APPLICATION INFORMATION CURRENT CONSUMPTION OUTPUT VOLTAGE STABILITY The DAC8552 typically consumes 170µA at VDD = 5 V and 155µA at VDD = 2.7V for each active channel, excluding reference current consumption. Additional current consumption can occur at the digital inputs if VIH<< VDD. For most efficient power operation, CMOS logic levels are recommended at the digital input to the DAC. The DAC8552 exhibits excellent temperature stability of 5ppm/°C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a ±25µV window for a ±1°C ambient temperature change. In power-down mode, typical current consumption is 700nA. A delay time of 10ms to 20ms after a power-down command is issued to the DAC is typically sufficient for the power-down current to drop below 10µA. Good power-supply rejection ratio (PSRR) performance reduces supply noise present on VDD from appearing at the outputs. Combined with good DC noise performance and true 16-bit differential linearity, the DAC8552 becomes an ideal choice for closed-loop control applications. DRIVING RESISTIVE AND CAPACITIVE LOADS SETTLING TIME AND OUTPUT GLITCH PERFORMANCE The DAC8552 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC8552 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2kΩ can be driven by the DAC8552 while achieving good load regulation. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 100mV of the DACs output voltage characteristic. Under resistive loading conditions, good linearity is preserved as long as the output voltage is at least 100 mV below the VDD voltage. The DAC8552 settles to ±0.003% of its full-scale range within 10µs, driving a 200pF, 2kΩ load. For good settling performance the outputs should not approach the top and bottom rails. Small signal settling time is under 1µs, enabling data update rates exceeding 1MSPS for small code changes. CROSSTALK AND AC PERFORMANCE The DAC8552 uses precision, thin-film resistors to achieve monotonicity and good linearity. Typical linearity error is ±4LSBs; ±0.3mV error for a 5V range. Differential linearity is typically ±0.35LSBs, ±27µV error for a consecutive code change. The DAC8552 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel is typically less than 0.5 LSBs. The AC crosstalk measured (for a full-scale, 1kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under –100dB. In addition, the DAC8552 can achieve typical AC performance of 96dB signal-to-noise ratio (SNR) and -85dB total harmonic distortion (THD), making the DAC8552 a solid choice for applications requiring high SNR at output frequencies at or below 10kHz. 18 Many applications are sensitive to undesired transient signals such as glitch. The DAC8552 has a proprietary, ultra-low glitch architecture addressing such applications. Code-to-code glitches rarely exceed 1mV and they last under 0.3µs. Typical glitch energy is an outstanding 0.15nV-s. Theoretical worst cast glitch should occur during a 256LSB step, but it is so low, it cannot be detected. DIFFERENTIAL AND INTERGRAL NONLINEARITY USING REF02 AS A POWER SUPPLY FOR DAC8552 Due to the extremely low supply current required by the DAC8552, a possible configuration is to use a REF02 +5V precision voltage reference to supply the required voltage to the DAC8552s supply input as well as the reference input, as shown in Figure 50. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8552. If the REF02 is Submit Documentation Feedback DAC8552 www.ti.com SLAS430 – JULY 2006 used, the current it needs to supply to the DAC8552 is 340µA typical and 500µA max for VDD = 5V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The typical current required (with a 5kΩ load on a given DAC output) is: 340µA + (5V/5kΩ) = 1.34mA V OUT ƪ A, B + V REF where D represents the input code in decimal (0–65535). With VREF = 5 V, R1 – R2 = 10kΩ. V A, B + 10 D * 5 V OUT 65536 ǒ +15 D Ǔ ǒR1 ) R2Ǔ * V ǒ65536 ǒR2 Ǔƫ REF R1 R1 Ǔ (3) This is an output voltage range of ±5V with 0000H corresponding to a –5V output and FFFFH corresponding to a 5V output. Similarly, using VREF = 2.5V, a ±2.5V output voltage range can be achieved. +5V REF02 1.34mA LAYOUT VDD, VREF SYNC 3−Wire Serial Interface VOUT = 0V to 5V SCLK DAC8552 The DAC8552 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. DIN Figure 50. REF02 as a Power Supply to the DAC8552 BIPOLAR OPERATION USING THE DAC8552 The DAC8552 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 51. The circuit shown will give an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an amplifier such as the OPA703, seeFigure 51. R2 10kΩ +5V +6V R1 10kΩ OPA703 VOUTA,B VDD, VREF 10µF ±5V DAC8552 −6V 0.1µF A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. NOTE: Other pins omitted for clarity. Figure 51. Bipolar Operation with the DAC8552 The output voltage for any input code can be calculated as follows: Due to the single ground pin of the DAC8552, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, a 1µF to 10µF capacitor in parallel with a 0.1µF bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors–all designed to essentially low-pass filter the supply, removing the high-frequency noise. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8552IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8552IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8552IDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DAC8552IDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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