CM1208-07/08 7 & 8-Channel High-Speed ESD Protection Arrays Features Product Description • The CM1208-07/CM1208-08 is a diode array designed to provide either 7 or 8 channels of ESD protection for electronic components or sub-systems. Each channel consists of a pair of diodes, which steers the ESD current pulse to either the positive (VP) or negative (VN) supply. The CM1208-07/08 devices will protect against ESD pulses up to 15kV contact discharge per the International Standard IEC61000-4-2. • • • • • • Seven or eight channels of high-speed ESD protection Meets IEC-61000-4-2 Level 4 ESD protection requirements (+8kV contact discharge) Meets IEC-61000-4-2 +15kV air discharge requirements Low loading capacitance at 3pF typical Low supply and leakage currents – ideal for battery-powered devices Small MSOP-10 package Lead-free versions available Applications • • • • • High speed data line ESD protection DVI ports High resolution video (e.g. VGA ports) Expansion ports for Notebook/Handheld Computers 5V pseudo RS-232 ports These devices are particularly well-suited for portable electronics (e.g.handheld and notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. They are also suitable for protecting video output lines and I/O ports in computers, set top boxes, digital TVs and peripheral equipment. The CM1208-07/CM1208-08 is housed in a 10 pin MSOP package and is available with optional lead-free finishing. Electrical Schematics CH7 VN CH1 CH2 VP CH5 CH6 CH3 CH4 CH7 CH8 VN CH1 CM1208-07 CH2 VP CH5 CH6 CH3 CH4 VN CM1208-08 © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM1208-07/08 PACKAGE / PINOUT DIAGRAMS Top View Top View CH1 1 10 VN CH1 1 10 CH8 CH2 2 9 CH7 CH2 2 9 CH7 CH3 3 8 VP CH3 3 8 VP 4 7 CH6 5 6 CH5 CH4 4 7 CH6 CH4 VN 5 6 CH5 VN 10-pin MSOP CM1208-08MS CM1208-08MR 10-pin MSOP CM1208-07MS CM1208-07MR Note: These drawings are not to scale. PIN DESCRIPTIONS DEVICE PIN NAME TYPE DESCRIPTION -07,-08 1 CH 1 I/O ESD Channel -07,-08 2 CH 2 I/O ESD Channel -07,-08 3 CH 3 I/O ESD Channel -07,-08 4 CH 4 I/O ESD Channel -07,-08 5 VN GND -07,-08 6 CH 5 I/O ESD Channel -07,-08 7 CH 6 I/O ESD Channel -07,-08 8 VP Supply -07,-08 9 CH 7 I/O -07 10 VN GND -08 10 CH 8 I/O Negative voltage supply rail or ground reference rail Positive voltage supply rail ESD Channel Negative voltage supply rail or ground reference rail ESD Channel Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Pins Package Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking 10 MSOP CM1208-07MS 0807 CM1208-07MR 807R 10 MSOP CM1208-08MS 0808 CM1208-08MR 808R Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM1208-07/08 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Supply Voltage (VP - VN) 6.0 V Diode Forward DC Current (Note 1) 20 mA -40 to +85 °C Operating Temperature Range Storage Temperature Range DC Voltage at any channel input -65 to +150 °C (VN - 0.5) to (VP + 0.5) V 300 mW RATING UNITS -40 to +85 °C 0 to 5.5 V Package Power Rating MSOP Package Note 1: Only one diode conducting at a time. STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range Operating Supply Voltage (VP - VN) © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM1208-07/08 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS IP Supply Current (VP-VN)=5.0V VF Diode Forward Voltage Top Diode Bottom Diode IF = 20mA; TA=25°C Channel Leakage Current TA=25°C Channel Input Capacitance At 1 MHz, OSC Level = 30mV, VP=5V, VN=0V, VCH=2.5V; Note 2 applies ILEAK CIN VESD VCL MIN TYP 0.60 0.65 ESD Protection Peak Discharge Voltage at any channel input a) Contact discharge per IEC 61000-4-2 standard b) Human Body Model, MILSTD-883, Method 3015 MAX UNITS 10 µA 0.7 0.8 0.95 0.95 V V ±0.1 ±1.0 µA 3 5 pF Notes 2, 3 & 5 ±8 kV Notes 2, 3 & 4 ±15 kV At 8kV ESD HBM; TA=25°C; Note 2, 3 & 4 Channel Clamp Voltage Positive Transients Negative Transients VP + 5.0 VN - 5.0 V V Note 1: All parameters specified at TA=-40 to +85°C unless otherwise noted. Note 2: These parameters guaranteed by design and characterization. Note 3: From I/O pins to VP or VN only. A bypass capacitor between VP and VN is required. It is recommended that VP be bypassed to VN with a 0.2µF ceramic capacitor. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded. Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded. Performance Information Typical Channel Input Capacitance vs. Channel Input Voltage at TA=25°C Input Capacitance (pF) 5 4 3 T y p ic a l V a r ia t io n o f C IN vs. VIN (VP = 5V, VN = 0V, 0.2 µF chip capacitor between VP and VN) 2 1 0 0 1 2 3 4 5 Input Voltage © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM1208-07/08 Application Information Design Considerations ance of the power supply respectively. As an example, a ROUT of 1 ohm would result in a 10V increment in VCL for a peak IESD of 10A. In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: To mitigate these effects, a high frequency bypass capacitor should be connected between the VP pin of the ESD Protection Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP. Typically a value in the 0.1µF to 0.2µF range is adequate for IEC-61000-42 level 4 contact discharge protection (8kV). For higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dt where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be approximated by ∆IESD/∆t, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL! As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output imped- Additional Information See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection.” L2 VP POSITIVE SUPPLY RAIL PATH OF ESD CURRENT PULSE IESD D1 D2 L1 ONE CHANNEL OF CM1208 LINE BEING PROTECTED SYSTEM OR CIRCUITRY BEING PROTECTED CHANNEL INPUT 20A VCL 0A GROUND RAIL VN CHASSIS GROUND Figure 1. Application of Positive ESD Pulse between Input Channel and Ground © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM1208-07/08 Mechanical Details MSOP Mechanical Specifications: CM1208-07/08 devices are packaged in 10-pin MSOP packages. Dimensions are presented below. Mechanical Package Diagrams TOP VIEW For complete information on the MSOP-10 package, see the California Micro Devices MSOP Package Information document. D 10 9 8 6 7 PACKAGE DIMENSIONS Package MSOP Pins Dimensions Pin 1 Marking 10 Millimeters Inches Min Max Min Max A 0.75 0.95 0.028 0.038 A1 0.05 0.15 0.002 0.006 B 0.18 0.40 0.006 0.016 C 0.18 1 2 3 4 5 SIDE VIEW 0.007 D 2.90 3.10 0.114 0.122 E 2.90 3.10 0.114 0.122 e E H 0.50 BSC 0.0196 BSC H 4.76 5.00 0.187 0.197 L 0.40 0.70 0.0137 0.029 # per tube 80 pieces* # per tape and reel 4000 A SEATING PLANE A1 B e END VIEW C Controlling dimension: inches * This is an approximate number which may vary. L Package Dimensions for MSOP-10 © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04