74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 • • • • • • • • • D OR N PACKAGE (TOP VIEW) Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Noninverting Version of ′ACT11138 Incorporates 3 Enable Inputs to Simplify Cascading and/or Data Reception Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs Y1 Y2 Y3 GND Y4 Y5 Y6 Y7 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Y0 A B C VCC G1 G2A G2B t description The 74ACT11238 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The 74ACT11238 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X L L L L L L L L X X H X X X L L L L L L L L L X X X X X L L L L L L L L H L L L L L H L L L L L L L H L L L L H L H L L L L L L H L L L H L L L H L L L L L H L L L H H L L L H L L L L H L L H L L L L L L H L L L H L L H L H L L L L L H L L H L L H H L L L L L L L H L H L L H H H L L L L L L L H EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 logic symbols (alternatives)† A B C BIN/OCT 15 14 13 1 0 2 1 4 2 3 G1 G2A G2B & 11 4 5 10 EN 9 6 7 16 1 2 3 5 6 7 8 Y0 Y1 Y2 A B C 15 DMUX 14 13 G 2 0 7 1 1 2 2 Y3 3 3 & Y4 Y5 G1 Y6 G2A Y7 16 0 0 G2B 11 10 9 5 4 6 5 7 6 8 7 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 16 A 1 B C 14 2 3 13 5 6 G1 G2B 2–2 Y1 Y2 Y3 Y4 Y5 11 7 G2A Y0 15 Y6 10 8 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions NOM VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 NOM 4.5 High-level input voltage MAX 5.5 2 UNIT V V 0.8 V VCC VCC V High-level output current – 24 mA IOL Dt /Dv Low-level output current 24 mA 0 10 ns/ V TA Operating free-air temperature – 40 85 °C Input transition rise or fall rate V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 mA VOH VOL II ICC DICC§ IOH = – 24 mA VCC TA = 25°C MIN TYP MAX MIN 4.5 V 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 4.8 MAX V IOH = – 75 mA‡ 5.5 V IOL = 50 mA 4.5 V 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 IOL = 24 mA IOL = 75 mA‡ VI = VCC or GND VI = VCC or GND, VI = VCC or GND 3.85 5.5 V IO = 0 0.1 V 1.65 5.5 V ± 0.1 ± 0.1 mA 5.5 V 4 40 mA 5.5 V 0.9 1 mA Ci VI = VCC or GND 5V 3.5 ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC. POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 pF 2–3 74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 switching characteristics, VCC = 5 V ± 0.5 V (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A B or C A, Y tPLH tPHL G1 Y tPLH tPHL G2A G2B G2A, Y TA = 25°C TYP MAX MIN 1.5 5 8.6 1.5 9.6 1.5 5.7 9.7 1.5 10.8 1.5 6 8.4 1.5 9.4 1.5 6.9 10.2 1.5 11.4 1.5 5.9 9 1.5 10.1 1.5 7.8 10.7 1.5 12.1 MIN MAX UNIT ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz TYP UNIT 57 pF PARAMETER MEASUREMENT INFORMATION 3V Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 1.5 V 1.5 V 0V tPHL 500 Ω tPLH 50% VCC Output VOH 50% VCC VOL VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 TYPICAL APPLICATION DATA 74ACT11238 BIN/OCT 15 14 13 VCC 0 1 1 2 2 4 11 3 & 4 10 EN 9 5 6 7 16 1 2 3 5 6 7 8 0 1 2 3 4 5 6 7 74ACT11238 BIN/OCT 15 A0 14 A1 13 A2 1 2 2 4 11 A3 0 1 3 & 4 10 A4 EN 9 5 6 7 16 1 2 3 5 6 7 8 8 9 10 11 12 13 14 15 74ACT11238 BIN/OCT 15 14 13 11 0 1 1 2 2 4 3 & 4 10 9 EN 5 6 7 16 1 2 3 5 6 7 8 16 17 18 19 20 21 22 23 Figure 2. 24-Bit Decoding Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 74ACT11238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993 TYPICAL APPLICATION DATA 74ACT11238 BIN/OCT 15 A0 14 A1 13 A2 1 1 2 2 4 11 VCC 0 3 & 4 10 A3 EN 9 A4 5 6 7 16 1 2 3 5 6 7 8 0 1 2 3 4 5 6 7 74ACT11238 BIN/OCT 15 14 13 0 1 1 2 2 4 11 3 & 4 10 EN 9 5 6 7 16 1 2 3 5 6 7 8 8 9 10 11 12 13 14 15 74ACT11238 BIN/OCT 15 14 13 0 1 1 2 2 4 11 3 & 4 10 EN 9 5 6 7 16 1 2 3 5 6 7 8 16 17 18 19 20 21 22 23 74ACT11238 BIN/OCT 15 14 13 11 0 1 1 2 2 4 3 & 4 10 9 EN 5 6 7 Figure 3. 32-Bit Decoding Scheme 2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 1 2 3 5 6 7 8 24 25 26 27 28 29 30 31 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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