DS1244Y DS1244Y 256K NV SRAM with Phantom Clock FEATURES PIN ASSIGNMENT • Real time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years A14/RST 1 28 VCC A12 2 27 WE x 8 NV SRAM directly replaces volatile static RAM or EEPROM A7 3 26 A13 A6 4 25 A8 • Embedded lithium energy cell maintains calendar op- A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 • 32K eration and retains RAM data • Watch function is transparent to RAM operation • Month and year determine the number of days in each month; volid up to 1200 • Standard 28–pin JEDEC pinout • Full 10% operating range • Operating temperature range 0°C to 70°C 28–PIN ENCAPSULATED PACKAGE 740 MIL EXTENDED • Accuracy is better than ±1 minute/month @ 25°C • Over 10 years of data retention in the absence of power • Available in 120, 150 and 200 ns access time ORDERING INFORMATION DS1244Y–XXX –120 –150 DS1244Y 120 ns access 150 ns access 200 ns access PIN DESCRIPTION Ao–A14 CE GND DQ0-DQ7 VCC WE OE NC RST – – – – – – – – – Address Inputs Chip Enable Ground Data In/Data Out Power (+5V) Write Enable Output Enable No Connect Reset DESCRIPTION The DS1244Y 256K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 32,768 words by 8 bits) with a built–in real time clock. The DS1244Y has a self–contained lithium energy source and control circuitry which constantly monitors VCC for an out–of– tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real time clock. Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. The Phantom Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock operates in either 24–hour or 12–hour format with an AM/PM indicator. 032697 1/12 DS1244Y RAM READ MODE PHANTOM CLOCK OPERATION The DS1244Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) is active (low). The unique address specified by the 15 address inputs (A0-A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64–bit pattern are directed to memory. RAM WRITE MODE The DS1244Y is in the write mode whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1244Y provides full functional capability for VCC greater than 4.5 volts and write protects by approximately 4.0 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write protects itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power–up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. 032697 2/12 After recognition is established, the next 64 read or write cycles either extract or update data in the Phantom Clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of Chip Enable (CE), Output Enable (OE), and Write Enable (WE). Initially, a read cycle to any memory location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock. DS1244Y PHANTOM CLOCK REGISTER INFORMATION in a register could produce erroneous results. These read/write registers are defined in Figure 2. The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64–bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits with- Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. PHANTOM CLOCK REGISTER DEFINITION Figure 1 HEX VALUE 7 6 5 4 3 2 1 0 BYTE 0 1 1 0 0 0 1 0 1 C5 BYTE 1 0 0 1 1 1 0 1 0 3A BYTE 2 1 0 1 0 0 0 1 1 A3 BYTE 3 0 1 0 1 1 1 0 0 5C BYTE 4 1 1 0 0 0 1 0 1 C5 BYTE 5 0 0 1 1 1 0 1 0 3A BYTE 6 1 0 1 0 0 0 1 1 A3 BYTE 7 0 1 0 1 1 1 0 0 5C NOTE: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This pattern is sent to the Phantom Clock LSB to MSB. 032697 3/12 DS1244Y PHANTOM CLOCK REGISTER DEFINITION Figure 2 REGISTER RANGE (BCD) 7 6 0 5 4 3 0.1 SEC 2 1 0.01 SEC 0 00–99 1 0 10 SEC SECONDS 00–59 2 0 10 MIN MINUTES 00–59 3 12/24 0 HOUR 01–12 00–23 4 0 0 5 0 0 6 0 0 7 10 A/P OSC HR RST 10 DATE 0 10 MONTH 10 YEAR AM–PM/12/24 MODE Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10–hour bit (20–23 hours). 0 DAY 01–07 DATE 01–31 MONTH 01–12 YEAR 00–99 to logic 0, a low input on the RESET pin will cause the Phantom Clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1. OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit is set 032697 4/12 ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. DS1244Y ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –0.3V to +7.0V 0°C to 70°C –40°C to +70°C 260°C for 10 seconds (See Note 13) * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER (0°C to 70°C) SYMBOL MIN TYP MAX UNITS Power Supply Voltage VCC 4.5 5.0 5.5 V Input Logic 1 VIH 2.2 VCC+0.3 V Input Logic 0 VIL 0.3 0.8 V (0°C to 70°C; VCC = 5V ± 10%) DC ELECTRICAL CHARACTERISTICS PARAMETER NOTES SYMBOL MIN Input Leakage Current IIL I/O Leakage Current CE VIH VCC TYP MAX UNITS NOTES –1.0 +1.0 µA 12 IIO –1.0 +1.0 µA Output Current @ 2.4V IOH –1.0 mA Output Current @ 0.4V IOL 2.0 mA Standby Current CE = 2.2V ICCS1 5.0 10 mA Standby Current CE = VCC – 0.5V ICCS2 3.0 5.0 mA Operating Current tCYC = 200 ns ICC01 85 mA DC TEST CONDITIONS Outputs are open; all voltages are referenced to ground. CAPACITANCE PARAMETER (tA = 25°C) SYMBOL MIN TYP MAX UNITS Input Capacitance CIN 5 10 pF Input/Output Capacitance CI/O 5 10 pF NOTES 032697 5/12 DS1244Y (0°C to 70°C; VCC = 5.0V ± 10%) MEMORY AC ELECTRICAL CHARACTERISTICS PARAMETER DS1244Y-120 DS1244Y-150 DS1244Y-200 MIN MIN MIN SYMBOL UNITS MAX 120 MAX 150 Read Cycle Time tRC Access Time tACC 120 150 200 ns OE to Output Valid tOE 60 70 100 ns CE to Output Valid tCO 120 150 200 ns OE or CE to Output Active tCOE Output High Z from Deselection tOD Output Hold from Address Change toH 5 5 5 ns Write Cycle Time tWC 120 150 200 ns Write Pulse Width tWP 90 100 150 ns Address Setup Time tAW 0 0 0 ns Write Recovery Time tWR 20 20 20 ns 5 40 tODW 40 Output Active from WE tOEW 5 5 Data Setup Time tDS 50 Data Hold Time from WE tDH 20 Output Load: Input Pulse Levels: 50 pF + 1TTL Gate 0-3V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 032697 6/12 5 ns ns 5 70 Output High Z from WE AC TEST CONDITIONS 200 5 100 70 NOTES MAX 80 ns 5 ns 5 3 ns 5 5 ns 5 60 80 ns 4 20 20 ns 4 DS1244Y PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS PARAMETER TYP (0°C to 70°C; VCC = 4.5 to 5.5V) SYMBOL MIN MAX UNITS NOTES Read Cycle Time tRC 120 CE Access Time tCO 100 ns OE Access Time tOE 100 ns CE to Output Low Z tCOE 10 ns OE to Output Low Z tOEE 10 ns CE to Output High Z tOD 40 ns 5 OE to Output High Z tODO 40 ns 5 ns Read Recovery tRR 20 ns Write Cycle Time tWC 120 ns Write Pulse Width tWP 100 ns Write Recovery tWR 20 ns 10 Data Setup Time tDS 40 ns 11 Data Hold Time tDH 10 ns 11 CE Pulse Width tCW 100 ns RESET Pulse Width tRST 200 ns CE High to Power–Fail tPF 0 ns MAX UNITS POWER-DOWN/POWER-UP TIMING PARAMETER SYMBOL MIN tPD 0 µs VCC Slew from 4.5V to 0V (CE at VIH) tF 300 µs VCC Slew from 0V to 4.5V (CE at VIH) tR 0 µs CE at VIH after Power–Up tREC CE at VIH before Power–Down TYP 2 NOTES ms (tA = 25°C) PARAMETER Expected Data Retention Time SYMBOL MIN tDR 10 TYP MAX UNITS NOTES years 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. 032697 7/12 DS1244Y MEMORY READ CYCLE (NOTE 1) tRC ADDRESSES VIH VIL VIH VIL VIH VIL ÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ tOH tACC VIH CE VIH tCO VIL tOD VIH tOE VIH OE VIL tCOE tOD tCOE VOH VOL DOUT VOH VOL OUTPUT DATA VALID MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7) tWC ADDRESS VIH VIL VIH VIL ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ tAW CE WE VIL VIL tWP tWR VIH VIH tOEW tODW HIGH IMPEDANCE tDS DQ0–DQ7 VIH VIL 032697 8/12 VIH VIL DATA IN STABLE tDH VIH VIL DS1244Y MEMORY WRITE CYCLE 2 (NOTES 2 AND 8) WE = VIH tWC ADDRESSES VIH VIL VIH VIL ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ VIH VIL tAW CE tWR tWP VIH VIH VIL WE VIL ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ tOEW VIL VIL tODW tCOE tDS DQ0–DQ7 VIH VIL tDH DATA IN STABLE VIH VIL RESET FOR PHANTOM CLOCK tRST RST READ CYCLE TO PHANTOM CLOCK tRC tRR tCO CE tOD tOE OE tODO tOEE tCOE Q ÌÌÌ ÌÌÌ OUTPUT DATA VALID ÌÌÌ ÌÌÌ 032697 9/12 DS1244Y WRITE CYCLE TO PHANTOM CLOCK OE = VIH tWC tWR tWP WE tWR tCW CE ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ tDH tDS tDH D DATA IN STABLE ÌÌÌÌÌÌ ÌÌÌÌÌÌ POWER–DOWN/POWER–UP CONDITION VCC 4.50V 3.2V tF tR tPD tREC CE LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL 032697 10/12 DATA RETENTION TIME tDR DS1244Y NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 50 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. The expected tDR is defined as accumulative time in the absence of VCC with the clock oscillator running. 10. tWR is a function of the latter occurring edge of WE or CE. 11. tDH and tDS are a function of the first occurring edge of WE or CE. 12. RST (Pin1) has an internal pull–up resistor. 13. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. 032697 11/12 DS1244Y DS1244Y 256K NV SRAM WITH PHANTOM CLOCK PKG 1 A C F D K J E H B 032697 12/12 G 28–PIN DIM MIN MAX A IN. MM 1.520 38.61 1.540 39.12 B IN. MM 0.720 18.29 0.740 18.80 C IN. MM 0.395 10.03 0.415 10.54 D IN. MM 0.100 2.54 0.130 3.30 E IN. MM 0.017 0.43 0.030 0.76 F IN. MM 0.120 3.05 0.160 4.06 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.590 14.99 0.630 16.00 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.021 0.53