74HC164 Description The 74HC164 is identical in pinout to the LS/ALS164. The Device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALSTTL outputs. The 74HC164 is an 8-bit, serial-itnput oparallel-output shift register. Two serial data inputs, A1 and A2, are provided so that one input May be used as a data enab le. Data is entered on each rising Edge of the clock. The activelow asynchronous Reset overrides the Clock and Serial Data inputs. Features •Outputs Directly Interface to CMOS, NMOS, and TTL 14 1 •Operating Voltage Range: 2.0 to 6.0 V DIP - 14 •Low Input Current: 1.0 µA •High Noise Immunity Characteristic of CMOS Devices 14 1 Logic Diagram SOP –14 Package Pin Assignment Function Table Inputs RESET L H H H CLOCK X Outputs A1 X X X XH D QA QB… QH L L D = data input L… X = don' t care no change Q An - Q Gn = data shifted from the previous stage on a D QAn… QGn rising edge at the clock input. D BEIJING ESTEK ELECTRONICS CO.,LTD 1 74HC164 Absolute Maximum Ratings Symbol VCC VIN VOUT IIN mA IOUT mA ICC mA PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 Unit V V V 750 500 mW -65 to +150 ° C 260 ° C DIP+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/ ° C from 65 ° to 125° C SOIC Package: : - 7 mW/ ° C from 65 ° to 125° C Recommended Operating Conditions Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Min 2.0 0 Max 6.0 VCC Unit V V TA Operating Temperature, All Package Types -55 +125 ° C tr, tf Input Rise and Fall Time 0 0 0 1000 500 400 ns (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must betaken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or V OUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). BEIJING ESTEK ELECTRONICS CO.,LTD 2 74HC164 DC Electrical Characteristics VCC Symbol Parameter Test Conditions (Voltages Referenced to GND) Guaranteed Limit V 25 ° C to -55° C ≤ 85 ° C ≤ 125 ° C Unit VIH Minimum HighLevel Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH VIN= VIH or VIL Minimum HighLevel Output Voltage IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 6.0 ±0.1 ±1.0 ±1.0 µA 6.0 8.0 80 160 µA VOL IIN VIN= VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VIN=VIH or Maximum LowVIL Level Output Voltage IOUT ≤ 20 µA Maximum Input Leakage Current ICC Maximum Quiescent Supply Current VIN=VIH or VIL IOUT ≤ 4.0 mA I ≤ 5.2 mA VIN=VCC or GND VIN=VCC or GND IOUT=0µA V BEIJING ESTEK ELECTRONICS CO.,LTD 3 74HC164 AC Electrical Characteristics (C L =50pF,Input tr Guaranteed Limit VCC Symbol fmax tPLH, tPHL (Figures tPHL tTLH, tTHL Parameter =t f ≤85° C ≤125° C Unit V 25 ° C to -55° C Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz Maximum Propagation Delay,Clock to Q 175 35 30 220 44 37 265 53 45 ns 1 and 4) 2.0 4.5 6.0 2.0 4.5 6.0 205 41 35 255 51 43 310 62 53 ns Maximum Propagation Delay,Reset to Q (Figures 2 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Output Transition Time, Any Output - 10 10 10 pF CIN Maximum Input Capacitance tSU Minimum Setup Time,A1 or A2 to Clock (Figure 3) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to A1 or A2 (Figure 3) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns CPD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power consumption: 2 f+I CCVCCPD=CPDV Typical @25° C,VCC=5.0 V 140 pF BEIJING ESTEK ELECTRONICS CO.,LTD 4 74HC164 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit Timing Diagram BEIJING ESTEK ELECTRONICS CO.,LTD 5 74HC164 Expanded Logic Diagram Ordering Information O RDERING NU MB ER 74HC164 Address : P ACK AGE M AR KING DIP - 14 / SOP - 14 ESTEK74HC164 6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793 Http://www.estek.com.cn Email:[email protected] REV No:01-060826 BEIJING ESTEK ELECTRONICS CO.,LTD 6