TM TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 125 W STEREO DIGITAL AMPLIFIER POWER STAGE FEATURES 1 DESCRIPTION The TAS5352 is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4-Ω bridge-tied load (BTL) at up to 125 W per channel with low harmonic distortion, low integrated noise, and low idle current. The TAS5352 has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of PWM signal (PWM activity detector). A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs. BTL OUTPUT POWER vs SUPPLY VOLTAGE 150 TC = 75°C THD+N at 10% 140 130 120 110 PO – Output Power – W • Total Power Output (Bridge Tied Load) – 2 × 125 W at 10% THD+N Into 4 Ω – 2 × 100 W at 10% THD+N Into 6 Ω • Total Power Output (Single Ended) – 4 × 45 W at 10% THD+N Into 3 Ω – 4 × 35 W at 10% THD+N Into 4 Ω • Total Power Output (Parallel Mode) – 1 × 250 W at 10% THD+N Into 2 Ω – 1 × 195 W at 10% THD+N Into 3 Ω • >110 dB SNR (A-Weighted With TAS5518 Modulator) • <0.1% THD+N (1 W, 1 kHz) • Supports PWM Frame Rates of 192 kHz to 432 kHz • Resistor-Programmable Current Limit • Integrated Self-Protection Circuitry, Including: – Under Voltage Protection – Overtemperature Warning and Error – Overload Protection – Short-Circuit Protection – PWM Activity Detector • Standalone Protection Recovery • Power-On Reset (POR) to Eliminate System Power-Supply Sequencing • High-Efficiency Power Stage (>90%) With 80-mΩ Output MOSFETs • Thermally Enhanced 44-Pin HTSSOP Package (DDV) • Error Reporting, 3.3-V and 5.0-V Compliant • EMI Compliant When Used With Recommended System Design 23 4Ω 100 90 80 6Ω 70 60 50 40 30 8Ω 20 10 0 0 APPLICATIONS • • • Mini/Micro Audio System DVD Receiver Home Theater 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 PVDD – Supply Voltage – V PurePath Digital™ 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital, PowerPad are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION Terminal Assignment The TAS5352 is available in a thermally enhanced 44-pin HTSSOP PowerPad™ package (DDV) This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling to the heatsink. DDV PACKAGE (TOP VIEW) GVDD_B OTW NC NC SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D NC NC VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D P0016-02 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 Protection MODE Selection Pins Protection modes are selected by shorting M1, M2, and M3 to VREG or GND. MODE PINS (1) (2) (3) Mode Name PWM Input (1) 0 BTL mode 1 2N All protection systems enabled 1 BTL mode 2 2N Latching shudown on, PWM activity detector and OLP disabled 0 BTL mode 3 1N M3 M2 M1 0 0 0 0 0 1 1N / 2N Description All protection systems enabled (2) 0 1 1 PBTL mode 1 0 0 SE mode 1 1N All protection systems enabled All protection systems enabled (3) 1 0 1 SE mode 2 1N Latching shudown on, PWM activity detector and OLP disabled (3) 1 1 0 1 1 Reserved 1 The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode. PPSC detection system disabled. Package Heat Dissipation Ratings (1) PARAMETER TAS5352DDV RθJC (°C/W)—2 BTL or 4 SE channels 1.3 RθJC (°C/W)—1 BTL or 2 SE channel(s) 2.6 RθJC (°C/W)—1 SE channel 5.0 Power Pad area (1) (2) (2) 36 mm2 JC is junction-to-case, CH is case-to-heatsink. RθCH is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K between the pad area and the heat sink. The RθCH with this condition is 0.6°C/W for the DDV package. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 3 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5352 VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V (2) PVDD_X to GND_X –0.3 V to 53 V OUT_X to GND_X (2) –0.3 V to 53 V BST_X to GND_X (2) –0.3 V to 66.2 V BST_X to GVDD_X (2) –0.3 V to 53 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V RESET_X, SD, OTW to AGND –0.3 V to 7 V Maximum continuous sink current (SD, OTW) 9 mA Maximum operating junction temperature range, TJ 0°C to 125°C Storage temperature –40°C to 125°C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260°C Minimum pulse duration, low 30 ns (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. ORDERING INFORMATION TA PACKAGE DESCRIPTION 0°C to 70°C TAS5352DDV 44-pin HTSSOP For the most current specification and package information, see the TI Web site at www.ti.com. 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 Terminal Functions TERMINAL NAME DDV NO. FUNCTION (1) DESCRIPTION AGND 11 P Analog ground BST_A 43 P Bootstrap pin, A-Side BST_B 34 P Bootstrap pin, B-Side BST_C 33 P Bootstrap pin, C-Side BST_D 24 P Bootstrap pin, D-Side GND 10 P Ground GND_A 38 P Power ground for half-bridge A GND_B 37 P Power ground for half-bridge B GND_C 30 P Power ground for half-bridge C GND_D 29 P Power ground for half-bridge D GVDD_A 44 P Gate-drive voltage supply; A-Side GVDD_B 1 P Gate-drive voltage supply; B-Side GVDD_C 22 P Gate-drive voltage supply; C-Side GVDD_D 23 P Gate-drive voltage supply; D-Side M1 15 I Mode selection pin (LSB) M2 14 I Mode selection pin M3 13 I Mode selection pin (MSB) NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded. OC_ADJ 9 O Analog overcurrent programming pin OTW 2 O Overtemperature warning signal, open-drain, active-low OUT_A 39 O Output, half-bridge A OUT_B 36 O Output, half-bridge B OUT_C 31 O Output, half-bridge C OUT_D 28 O Output, half-bridge D PVDD_A 40, 41 P Power supply input for half-bridge A PVDD_B 35 P Power supply input for half-bridge B PVDD_C 32 P Power supply input for half-bridge C PVDD_D 26, 27 P Power supply input for half-bridge D PWM_A 6 I PWM Input signal for half-bridge A PWM_B 8 I PWM Input signal for half-bridge B PWM_C 16 I PWM Input signal for half-bridge C PWM_D 18 I PWM Input signal for half-bridge D RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active-low SD 5 O Shutdown signal, open-drain, active-low VDD 21 P Input power supply VREG 12 P Internal voltage regulator (1) I = input, O = output, P = power Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 5 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 TYPICAL SYSTEM BLOCK DIAGRAM OTW System Microcontroller SD SD TAS5518 OTW I2C BST_A BST_B RESET_AB RESET_CD VALID PWM_A LeftChannel Output OUT_A Output H-Bridge 1 Input H-Bridge 1 PWM_B OUT_B Bootstrap Capacitors 2nd-Order L-C Output Filter for Each Half-Bridge 2-Channel H-Bridge BTL Mode OUT_C PWM_C 4 34.5 V PVDD System Power Supply GND 12 V 4 PVDD Power Supply Decoupling OC_ADJ AGND VREG GND M3 2nd-Order L-C Output Filter for Each Half-Bridge BST_C VDD M2 OUT_D GVDD_A, B, C, D M1 GND_A, B, C, D PWM_D Hardwire Mode Control Output H-Bridge 2 Input H-Bridge 2 PVDD_A, B, C, D RightChannel Output BST_D Bootstrap Capacitors 4 GVDD VDD VREG Power Supply Decoupling Hardwire OC Limit GND GVDD (12 V)/VDD (12 V) VAC B0047-02 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 FUNCTIONAL BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD OC_ADJ Isense GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl. Timing Gate Drive OUT_C BTL/PBTL−Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv. Ctrl. Timing Gate Drive OUT_B BTL/PBTL−Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv. Ctrl. Timing Gate Drive OUT_A BTL/PBTL−Configuration Pulldown Resistor GND_A B0034-03 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 7 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply voltage 0 34.5 37 V GVDD_X Supply voltage for logic regulators and gate-drive circuitry 10.8 12 13.2 V VDD Digital regulator supply voltage 10.8 12 13.2 V 3 4 2.25 3 RL (BTL) RL (SE) RL (PBTL) Resistive load impedance (no Cycle-by_Cycle current control), recommended demodulation filter 1.5 2 5 10 5 10 5 10 LOutput (BTL) LOutput (SE) Minimum output inductance under short-circuit condition Output-filter inductance LOutput (PBTL) μH fS PWM frame rate 192 tLOW Minimum low-state pulse duration per PWM Frame, noise shaper enabled 30 CPVDD PVDD close decoupling capacitors 0.1 μF CBST Bootstrap capacitor, selected value supports PWM frame rates from 192 kHz to 432 kHz 33 nF ROC Over-current programming resistor REXT-PULLUP External pull-up resistor to +3.3V to +5.0V for SD or OTW TJ Junction temperature Resistor tolerance = 5% 384 Ω 432 kHz nS 22 22 3.3 4.7 47 kΩ kΩ 0 125 °C AUDIO SPECIFICATIONS (BTL) Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5352 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 470 nF, unless otherwise noted. PARAMETER POMAX Maximum Power Output PO TAS5352 TEST CONDITIONS Unclipped Power Output MIN TYP RL = 4 Ω, 10% THD+N, clipped input signal 125 RL = 6 Ω, 10% THD+N, clipped input signal 100 RL = 8 Ω, 10% THD+N, clipped input signal 76 RL = 4 Ω, 0 dBFS, unclipped input signal 96 RL = 6 Ω, 0 dBFS, unclipped input signal 72 RL = 8 Ω, 0 dBFS, unclipped input signal 57 0 dBFS; AES17 filter MAX UNIT W 0.2% THD+N Total harmonic distortion + noise Vn Output integrated noise A-weighted, AES17 filter, Auto mute disabled 50 SNR Signal-to-noise ratio (1) A-weighted, AES17 filter, Auto mute disabled 110 dB DNR Dynamic range A-weighted, input level = –60 dBFS, AES17 filter 110 dB DC Offset Output offset voltage +/- 15 mV Pidle Power dissipation due to idle losses (IPVDD_X) 2 W (1) (2) 8 1 W; AES17 filter 0.09% PO = 0 W, all halfbridges switching (2) μV SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 AUDIO SPECIFICATIONS (Single-Ended Output) Audio performance is recorded as a chipset consisting of a TAS5086 pwm processor (modulation index limited to 97.7%) and a TAS5352 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 20 μH, CDEM = 1.0 μF, unless otherwise noted. PARAMETER POMAX PO Maximum Power Output Unclipped Power Output THD+N TAS5352 TEST CONDITIONS Total harmonic distortion + noise MIN TYP RL = 3 Ω, 10% THD+N, clipped input signal 45 RL = 4 Ω, 10% THD+N, clipped input signal 35 RL = 3 Ω, 0 dBFS, unclipped input signal 35 RL = 4 Ω, 0 dBFS, unclipped input signal 25 MAX UNIT W 0 dBFS; AES17 filter 0.2% 1 W; AES17 filter 0.09% Vn Output integrated noise A-weighted, AES17 filter, Auto mute disabled 40 μV SNR Signal-to-noise ratio (1) A-weighted, AES17 filter, Auto mute disabled 109 dB DNR Dynamic range A-weighted, input level = –60 dBFS AES17 filter 109 dB 2 W Pidle (1) (2) Power dissipation due to idle losses (IPVDD_X) PO = 0 W, all halfbridges switching (2) SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. AUDIO SPECIFICATIONS (PBTL) Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5352 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 3Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 uF, unless otherwise noted. PARAMETER POMAX PO Maximum Power Output Unclipped Power Output THD+N TAS5352 TEST CONDITIONS Total harmonic distortion + noise MIN TYP RL = 3 Ω, 10% THD+N, clipped input signal 195 RL = 2 Ω, 10% THD+N, clipped input signal 250 RL = 3 Ω, 0 dBFS, unclipped input signal 145 RL = 2 Ω, 0 dBFS, unclipped input signal 190 0 dBFS; AES17 filter MAX UNIT W 0.2% 1 W; AES17 filter 0.09% Vn Output integrated noise A-weighted, AES17 filter, Auto mute disabled 50 μV SNR Signal-to-noise ratio (1) A-weighted, AES17 filter, Auto mute disabled 110 dB DNR Dynamic range A-weighted, input level = –60 dBFS AES17 filter 110 dB +/- 15 mV 2 W DC Offset Pidle (1) (2) Output offset voltage Power dissipation due to idle losses (IPVDD_X) PO = 0 W, all halfbridges switching (2) SNR is calculated relative to 0-dBFS input level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 9 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER TAS5352 TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 Operating, 50% duty cycle 7.2 17 Idle, reset mode 5.5 11 UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node IVDD VDD supply current IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge idle current VDD = 12 V V mA 50% duty cycle 8 16 Reset mode 1 1.8 13.6 25 mA 7 25 μA 50% duty cycle, without output filter or load Reset mode, no switching mA Output Stage MOSFETs RDSon,LS Drain-to-source resistance, Low Side TJ = 25°C, excludes metallization resistance, 80 89 mΩ RDSon,HS Drain-to-source resistance, High Side TJ = 25°C, excludes metallization resistance, 80 89 mΩ I/O Protection Undervoltage protection limit, GVDD_X Vuvp,G 9.5 V Vuvp,hyst (1) Undervoltage protection limit, GVDD_X 250 mV BSTuvpF Puts device into RESET when BST voltage falls below limit 5.9 V BSTuvpR Brings device out of RESET when BST voltage rises above limit 7 V OTW (1) Overtemperature warning OTWHYST (1) Temperature drop needed below OTW temp. for OTW to be inactive after the OTW event OTE (1) Overtemperature error threshold OTEOTWdifferential (1) OTE - OTW differential, temperature delta between OTW and OTE OLPC Overload protection counter IOC Overcurrent limit protection IOCT Overcurrent response time tACTIVITY Time for PWM activity detector to activite when no PWM is present Lack of transistion of any PWM input Output pulldown current of each half-bridge Connected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode. DETECTOR IPD 115 125 135 °C 25 145 155 °C 165 °C 30 °C fS = 384 kHz 1.25 ms Resistor—programmable, high-end, ROC = 22 kΩ with 1 mS pulse 10.9 A 150 ns 13.2 μS 3 mA Static Digital Specifications VIH High-level input voltage VIL Low-level input voltage ILeakage Input leakage current PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 2 V 0.8 V 100 μA kΩ OTW/SHUTDOWN (SD) RINT_PU Internal pullup resistance, OTW to VREG, SD to VREG VOH High-level output voltage VOL Low-level output voltage (1) 10 Internal pullup resistor External pullup of 4.7 kΩ to 5 V IO = 4 mA 20 26 32 3 3.3 3.6 4.5 5 0.2 0.4 V V Specified by design Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER FANOUT TAS5352 TEST CONDITIONS Device fanout OTW, SD MIN TYP No external pullup UNIT MAX 30 Devices TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 150 10 TC = 75°C THD+N at 10% TC = 75°C THD+N at 10% 140 130 120 2 110 1 PO – Output Power – W THD+N – Total Hamonic Distortion – % 5 0.5 4Ω 0.2 0.1 6Ω 0.05 4Ω 100 90 80 6Ω 70 60 50 40 30 0.02 8Ω 20 0.01 10 8Ω 0.005 20m 50m 100m 200m 500m 1 5 2 10 20 0 50 100 200 0 2 4 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 PVDD – Supply Voltage – V Figure 1. Figure 2. UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs OUTPUT POWER 100 95 TC = 75°C 90 85 80 75 8Ω 6 70 4Ω 6Ω 8Ω 8Ω 4 65 Efficiency – % PO – Output Power – W PO – Output Power – W 60 55 50 45 40 35 30 25 20 8Ω TC = 25°C THD+N at 10% 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 0 0 PVDD – Supply Voltage – V 40 80 120 160 200 240 280 2 Channels Output Power – W Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 11 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) SYSTEM POWER LOSS vs OUTPUT POWER SYSTEM OUTPUT POWER vs CASE TEMPERATURE 160 34 TC = 25°C THD+N at 10% 32 30 150 140 130 28 26 PO – Output Power – W 24 22 Power Loss – W 4Ω 6 120 4Ω 20 18 16 14 12 4 8Ω 110 100 90 80 70 60 8Ω 50 10 40 8Ω 6 8 30 6 20 4 8Ω 2 0 0 20 40 60 80 THD+N at 10% 10 0 10 100 120 140 160 180 200 220 240 260 280 2 Channels Output Power – W 20 30 40 50 60 70 80 90 100 110 120 TC – Case Temperature – °C Figure 5. Figure 6. NOISE AMPLITUDE vs FREQUENCY +0 –10 –20 –30 –40 TC = 75°C VREF = 20.60 V Sample Rate = 48 kHz FFT Size = 16384 Noise Amplitude – V –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k 22k f – Frequency – kHz Figure 7. 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 TYPICAL CHARACTERISTICS, SE CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 TC = 75°C THD+N at 10% 2 PO – Output Power – W THD+N – Total Hamonic Distortion – % 10 1 0.5 0.2 3Ω 0.1 0.05 4Ω 0.02 0.01 0.005 20m 50m 100m 200m 500m 1 5 2 10 20 60 57.5 55 52.5 50 47.5 45 42.5 40 37.5 35 32.5 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 5 2.5 0 50 80 TC = 75°C THD+N at 10% 3Ω 4Ω 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 PVDD – Supply Voltage – V PO – Output Power – W Figure 8. Figure 9. PO – Output Power – W OUTPUT POWER vs CASE TEMPERATURE 60 57.5 55 52.5 50 47.5 45 42.5 40 37.5 35 32.5 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 5 2.5 3Ω 4Ω THD+N at 10% 0 10 20 30 40 50 60 70 80 90 100 110 120 TC – Case Temperature – °C Figure 10. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 13 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 300 5 TC = 75°C THD+N at 10% TC = 75°C THD+N at 10% 280 4Ω 260 240 2 220 PO – Output Power – W THD+N – Total Hamonic Distortion – % 10 1 0.5 2Ω 0.2 0.1 0.05 3Ω 4Ω 2 200 180 160 3Ω 4 140 120 4Ω 100 80 60 0.02 40 8Ω 0.01 0.005 20m 8Ω 20 0 50m 100m 200m 500m 1 2 5 10 20 50 0 100 200 400 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 PVDD – Supply Voltage – V PO – Output Power – W Figure 11. Figure 12. SYSTEM OUTPUT POWER vs CASE TEMPERATURE 300 280 260 4Ω 3 240 220 8Ω 2 PO – Output Power – W 200 180 160 140 120 8Ω 4 100 80 60 40 8Ω THD+N at 10% 20 0 10 20 30 40 50 60 70 80 90 100 110 120 TC – Case Temperature – °C Figure 13. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 APPLICATION INFORMATION PCB Material Recommendation FR-4 Glass Epoxy material with 2 oz. (70 μm) is recommended for use with the TAS5352. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance. PVDD Capacitor Recommendation The large capacitors used in conjunction with each full-birdge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000 μF, 50-V will support more applications. The PVDD capacitors should be low ESR type because they are used in a circuit associtated with high-speed switching. Decoupling Capacitor Recommendations In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this application. The voltage of the decoupling capactors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 0.1μF that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power power output. A minimum voltage rating of 50-V is required for use with a 34.5 V power supply. System Design Recommendations The following schematics and PCB layouts illustrate "best practices" in the use of the TAS5352. GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5342DDV GND GND GVDD_B Microcontroller OTW I2C GND PWM1_P VALID PWM1_M 22 k NC NC PVDD_A SD PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND VREG 100 nF PWM2_P TAS5508/18 0Ω GND BST_C M2 OUT_C M1 GND_C PWM_C GND_D PVDD_D NC PVDD_D 100 nF GVDD_C GND 10 nF 50 V 470 nF 100 nF 50 V GND 1 nF 50 V GND 10 nF 50 V 3.3 Ω 10 µH 10 µH 33 nF 25V GND NC 3.3 Ω 1 nF 50 V 100 nF 50 V 10 nF 50 V 100 nF 50 V 470 nF 100 nF 50 V 100 nF 50 V GND 1 nF 50 V GND GND 10 nF 50 V 3.3 Ω 10 µH BST_D GVDD_D 33 nF 25 V PVDD 3.3 Ω GND 470 µF 50 V 10 nF 50 V 100 nF 100 nF 10 Ω VDD (+12 V) 100 nF 50 V 100 nF 50 V 33 nF 25 V OUT_D PWM_D VDD 100 nF 50 V 3.3 Ω 1 nF 50 V BST_B PVDD_C NC 33 nF 25 V GND PVDD_B M3 RESET_CD PWM2_M GND 10 µH BST_A NC GND GND GVDD_A GND 10 Ω GND GND GVDD (+12 V) Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 15 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5352DDV GND GND GVDD_B Microcontroller OTW I2C GND PWM1_P VALID 22 k NC NC PVDD_A SD PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND VREG 100 nF PWM2_P TAS5508/18 0Ω OUT_C M1 GND_C PWM_C GND_D GND 10 nF 50 V 100 nF 50 V GND 1 nF 50 V GND 10 nF 50 V 3.3 Ω 10 µH 10 µH 33 nF 25V PVDD_D NC PVDD_D GND NC 3.3 Ω 1 nF 50 V 100 nF 50 V 10 nF 50 V 100 nF 50 V 470 nF 100 nF 50 V 100 nF 50 V GND 1 nF 50 V GND GND 10 nF 50 V 3.3 Ω 10 µH BST_D GVDD_D 33 nF 25 V PVDD 3.3 Ω GND 470 µF 50 V 10 nF 50 V 100 nF 100 nF 10 Ω VDD (+12 V) 100 nF 50 V 470 nF 100 nF 50 V 33 nF 25 V OUT_D PWM_D GVDD_C 100 nF BST_C PVDD_C VDD 100 nF 50 V 3.3 Ω 1 nF 50 V BST_B M2 NC GND 33 nF 25 V GND PVDD_B M3 RESET_CD GND 10 µH BST_A NC GND GND GVDD_A GND 10 Ω GND GND GVDD (+12 V) Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5352DDV GND GND GVDD_A GVDD_B Microcontroller I2C GND PWM1_P VALID PWM2_P 22 k 100 nF PWM3_P NC NC PVDD_A SD PVDD_A TAS5508/18 0Ω OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B PVDD_B 100 nF 50 V 20 µH 33 nF 25 V BST_B B VREG BST_C C M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D 20 µH 33 nF 25V PVDD_D NC PVDD_D NC 100 nF 50 V GND OUT_D PWM_D 100 nF 50 V GND 20 µH D BST_D VDD 100 nF GND AGND NC GND 33 nF 25 V GND 100 nF 50 V PWM_A RESET_CD PWM4_P A NC GND GND 20 µH BST_A OTW GVDD_D GVDD_C 33 nF 25 V PVDD 3.3 Ω GND 470 µF 50 V 10 Ω 10 Ω GND GND VDD (+12 V) 10 nF 50 V 100 nF 100 nF GND 10 nF 50 V 10 nF 50 V 3.3 Ω GVDD (+12 V) GND 3.3 Ω GND B A 100nF 50V PVDD 10 k 470 µF 50 V 100nF 50 V 470 µF 50 V 10 k 470 µF 50V 1 µF 100 nF 50 V GND 470 µF 50 V 3.3 Ω GND 100 nF 50 V PVDD 1 µF 50 V 10 nF 3.3 Ω GND 50 V 10 nF GND GND 10 nF 50 V 10 nF 50 V 3.3 Ω GND GND 3.3 Ω GND D C PVDD 10 k 470 µF 50 V 1 µF 100 nF 50 V 100 nF 50 V 470 µF 50 V GND 50 V 10 nF 10 k 470 µF 50 V GND 1 µF 100 nF 50 V 470 µF 50 V 3. 3 Ω GND 100 nF 50 V PVDD GND 3.3 Ω GND 50 V 10 nF GND Figure 16. Typical SE Application Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 17 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5352DDV GND GND GVDD_B Microcontroller I2C GND PWM1_P VALID PWM1_M 22 k 1R NC NC NC PVDD_A SD PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND VREG 100 nF 0Ω BST_C PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD TAS5508/18 PVDD_D NC PVDD_D 100 nF 50 V 100 nF 50 V 10 µH 33 nF 25 V 10 nF 50 V 1 µF 100 nF 50 V 10 µH 33 nF 25V GND 1 nF 50 V 100 nF 50 V GND 10 nF 50 V 3.3 Ω 100 nF 50 V GND NC 10 µH GVDD_C 33 nF 25 V GVDD_D PVDD 3.3 Ω GND 470 µF 50 V 10 nF 50 V 100 nF 100 nF 10 Ω 10 Ω GND GND VDD (+12 V) 3.3 Ω 1 nF 50 V BST_D VDD 100 nF GND OUT_D PWM_D NC GND 100 nF BST_B M3 GND 10 µH 33 nF 25 V GND PVDD_B GND GND GVDD_A BST_A OTW GND GVDD (+12 V) Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5352DDV GND GND GVDD_B Microcontroller OTW I2C GND PWM1_P VALID PWM1_M 22 k 1R NC NC PVDD_A SD PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND VREG 100 nF TAS5508/18 0Ω GND OUT_C M1 GND_C PWM_C GND_D PVDD_D NC PVDD_D GVDD_C GND 100 nF 50 V 3.3 Ω 1 nF 50 V 10 nF 50 V 1 µF 10 µH 33 nF 25V GND NC 100 nF 50 V 1 nF 50 V 100 nF 50 V GND 10 nF 50 V 3.3 Ω 100 nF 50 V GND 10 µH BST_D GVDD_D 33 nF 25 V PVDD 3.3 Ω GND 470 µF 50 V 10 nF 50 V 100 nF 100 nF 10 Ω VDD (+12 V) 100 nF 50 V 10 µH 33 nF 25 V OUT_D PWM_D VDD 100 nF BST_C M2 NC 100 nF 50 V BST_B PVDD_C RESET_CD 33 nF 25 V GND PVDD_B M3 GND 10 µH BST_A NC GND GND GVDD_A GND 10 Ω GND GND GVDD (+12 V) Figure 18. Typical Non-Differential (1N) PBTL Application 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5352 needs only a 12 V supply in addition to the (typical) 34.5 V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge. In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5352 reference design. For additional information on recommended power supply and required components, see the application diagrams given previously in this data sheet. The 12 V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 34.5 V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5352 is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions section of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5352 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET_AB and RESET_CD in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. When the TAS5352 is being used with TI PWM modulators such as the TAS5518, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. Powering Down The TAS5352 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 19 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). When the TAS5352 is being used with TI PWM modulators such as the TAS5518, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended. To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). Mid Z Sequence Compatability The TAS5352 is compatable with the Mid Z sequence of the TAS5086 Modulator. The Mid Z Sequence is a series of pulses that is generated by the modulator. This sequence causes the power stage to slowly enable its outputs as it begins to switch. By slowly starting the PWM switching, the impulse response created by the onset of switching is reduced. This impulse response is the acoustic artifact that is heard in the output transducers (loudspeakers) and is commonly termed "click" or "pop". The low acoustic artifact noise of the TAS5352 will be further decreased when used in conjunction with the TAS5086 modulator with the Mid Z Sequence enabled. The Mid Z sequence is primarily used for the single-ended output configuration. It facilitates a "softer" PWM output start after the split cap output configuration is charged. The TAS5352 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5352 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and over-temperature error (OTE), the device automatically recovers when the fault condition has been removed, i.e., the supply voltage has increased. The device will function on errors, as shown in the following table BTL MODE Local Error In A B ERROR REPORTING C The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see the following table). SD OTW 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Junction temperature higher than 125°C (overtemperature warning) 1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation) DESCRIPTION Note that asserting either RESET_AB or RESET_CD low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW 20 DEVICE PROTECTION SYSTEM D Turns Off A+B C+D PBTL MODE Local Error In Turns Off A B C D SE MODE Local Error In Turns Off A A+B+C +D B C D A+B C+D Bootstrap UVP does not shutdown according to the table, it shutsdown the respective halfbridge. Use of TAS5352 in High-Modulation-Index Capable Systems This device requires at least 30 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5508, this setting allows PWM pulse durations down to 10 ns. This signal, which does not meet the 30-ns requirement, is sent to the PWM_X pin and this low-state pulse time does not allow the bootstrap capacitor to stay charged. The TAS5352 device requires limiting the TAS5508 modulation index to 97.7% to keep the bootstrap capacitor charged under all signals and loads. The TAS5352 contains a bootstrap capacitor under voltage protection circuit (BST_UVP) that monitors the voltage on the bootstrap capacitors. When the Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 voltage on the bootstrap capacitors is less than required for proper control of the High-Side MOSFETs, the device will initiate bootstrap capacitor recharge sequences until the bootstrap capacitors are properly charged for robust operation. This function may be activated with PWM pulses less than 30 nS. Therefore, TI strongly recommends using a TI PWM processor, such as TAS5518, TAS5086 or TAS5508, with the modulation index set at 97.7% to interface with TAS5352. Overcurrent (OC) Protection With Current Limiting and Overload Detection The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting and overload protection are independent for half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overload fault, only half-bridges A and B are shut down. • For the lowest-cost bill of materials in terms of component selection, the OC threshold measure should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold. • The demodulation-filter inductor must retain at least 5 μH of inductance at twice the OC threshold setting. Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to core losses and the dc resistance of the inductor's copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended. Setting the OC threshold too low might cause issues such as lack of enough output power and/or unexpected shutdowns due to too-sensitive overload detection. In general, it is recommended to follow closely the external component selection and PCB layout as given in the Application section. For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. (See the Electrical Characteristics section of this data sheet for information on the correlation between programming-resistor value and the OC threshold.) It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. It is required to follow certain guidelines when selecting the OC threshold and an appropriate demodulation inductor: OC-Adjust Resistor Values (kΩ) Max. Current Before OC Occurs (A), TC = 75°C 22 10.9 33 9.1 47 7.1 The reported max peak current in the table above is measured with continuous current in 1 Ω, one channel active and the other one muted. Pin-To-Pin Short Circuit Protection (PPSC) The PPSC detection system protects the device from permanent damage in the case that a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison the OC protection system detects an over current after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended not to insert resistive load to GND_X or PVDD_X. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 21 TAS5352 www.ti.com SLES204 – SEPTEMBER 2007 Overtemperature Protection DEVICE RESET The TAS5352 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, either RESET_AB or RESET_CD must be asserted. Thereafter, the device resumes normal operation. Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high-impedance state. Thus, both reset pins are well suited for hard-muting the power stage if needed. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5352 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics Table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. 22 In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. In the SE mode, the weak pulldowns are not enabled, and it is therefore recommended to ensure bootstrap capacitor charging by providing a low pulse on the PWM inputs when reset is asserted high. Asserting either reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high. A rising-edge transition on either reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of /SD. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TAS5352 PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2007 TAPE AND REEL BOX INFORMATION Device TAS5352DDVR Package Pins DDV 44 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SITE 60 330 24 8.6 15.6 1.8 12 Pack Materials-Page 1 W Pin1 (mm) Quadrant 24 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) TAS5352DDVR DDV 44 SITE 60 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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