TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 300-W STEREO / 400-W MONO PurePath™ HD ANALOG-INPUT POWER STAGE Check for Samples: TAS5630B FEATURES APPLICATIONS • • • • • 1 23 • • • • • • PurePath™ HD Enabled Integrated Feedback Provides: – Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources – Ultralow 0.03% THD at 1 W into 4 Ω – Flat THD at all Frequencies for Natural Sound – 80-dB PSRR (BTL, No Input Signal) – >100-dB (A-weighted) SNR – Click- and Pop-Free Start-Up Multiple Configurations Possible on the Same PCB With Stuffing Options: – Mono Parallel Bridge-Tied Load (PBTL) – Stereo Bridge-Tied Load (BTL) – 2.1 Single-Ended Stereo Pair and BridgeTied Load Subwoofer – Quad Single-Ended Outputs Total Output Power at 10% THD+N – 400 W in Mono PBTL Configuration – 300 W per Channel in Stereo BTL Configuration – 145 W per Channel in Quad Single-Ended Configuration High-Efficiency Power Stage (>88%) With 60mΩ Output MOSFETs Two Thermally Enhanced Package Options: – PHD (64-Pin QFP) – DKD (44-Pin PSOP3) Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short-Circuit Protection) With Error Reporting EMI Compliant When Used With Recommended System Design Mini Combo System AV Receivers DVD Receivers Active Speakers DESCRIPTION The TAS5630B is a high-performance analog-input class-D amplifier with integrated closed-loop feedback technology (known as PurePath HD technology) with the ability to drive up to 300 W (1) stereo into 4-Ω to 8-Ω speakers from a single 50-V supply. PurePath HD technology enables traditional ABamplifier performance (<0.03% THD) levels while providing the power efficiency of traditional class-D amplifiers. Unlike traditional class-D amplifiers, the distortion curve does not increase until the output levels move into clipping. PurePath HD™ PurePath HD technology enables lower idle losses, making the device even more efficient. Coupled with TI’s class-G power-supply reference design for TAS563x, industry-leading levels of efficiency can be achieved. 3 ´ OPA1632 ♫♪ TM ANALOG AUDIO INPUT PurePath HD TAS5630B (2.1 Configuration) ♫♪ ♫♪ ±15 V 12 V 25 V–50 V TM PurePath HD Class-G Power Supply Ref. Design 110 VAC ® 240 VAC (1) 1 2 3 Achievable output power levels are dependent on the thermal configuration of the target application. A high-performance thermal interface material between the exposed package heat slug and the heat sink should be used to achieve high output power levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath HD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION Terminal Assignment The TAS5630B is available in two thermally enhanced packages: • 64-Pin QFP (PHD) power package • 44-Pin PSOP3 package (DKD) The package types contain heat slugs that are located on the top side of the device for convenient thermal coupling to the heat sink. DKD PACKAGE (TOP VIEW) 64-pins QFP package 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND_A GND_B GND_B OUT_B OUT_B PVDD_B PVDD_B BST_B BST_C PVDD_C PVDD_C OUT_C OUT_C GND_C GND_C GND_D OTW2 CLIP READY M1 M2 M3 GND GND GVDD_C GVDD_D BST_D OUT_D OUT_D PVDD_D PVDD_D GND_D 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PSU_REF VDD OC_ADJ RESET C_STARTUP INPUT_A INPUT_B VI_CM GND AGND VREG INPUT_C INPUT_D FREQ_ADJ OSC_IO+ OSC_IOSD OTW READY M1 M2 M3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 pins PACKAGE (TOP VIEW) OC_ADJ RESET C_STARTUP INPUT_A INPUT_B VI_CM GND AGND VREG INPUT_C INPUT_D FREQ_ADJ OSC_IO+ OSC_IOSD OTW1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD PSU_REF NC NC NC NC GND GND GVDD_B GVDD_A BST_A OUT_A OUT_A PVDD_A PVDD_A GND_A PHD PACKAGE (TOP VIEW) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GVDD_AB BST_A PVDD_A PVDD_A OUT_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D OUT_D PVDD_D PVDD_D BST_D GVDD_CD PIN ONE LOCATION PHD PACKAGE Electrical Pin 1 Pin 1 Marker White Dot 2 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 MODE SELECTION PINS MODE PINS ANALOG INPUT OUTPUT CONFIGURATION Differential 2 × BTL AD mode — — Reserved Differential 2 × BTL BD mode M3 M2 M1 0 0 0 0 0 1 0 1 0 1 × BTL +2 ×SE 4 × SE 0 1 1 Differential singleended 1 0 0 Single-ended DESCRIPTION BD mode, BTL differential AD mode INPUT_C 1 0 1 1 1 0 1 1 1 (1) Differential 1 × PBTL (1) INPUT_D (1) 0 0 AD mode 1 0 BD mode Reserved INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND). THERMAL INFORMATION THERMAL METRIC (1) (2) TAS5630B PHD (64 Pins) DKD (44 Pins) θJA Junction-to-ambient thermal resistance 8.5 9.3 θJCtop Junction-to-case (top) thermal resistance 0.2 0.6 θJB Junction-to-board thermal resistance 20.6 3.7 ψJT Junction-to-top characterization parameter 0.2 1.3 ψJB Junction-to-board characterization parameter 0.73 3.5 θJCbot Junction-to-case (bottom) thermal resistance 8.2 19.1 (1) (2) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Thermal model data was performed using a 40 x 40 x 90mm heat-sink Table 1. ORDERING INFORMATION (1) (1) TA PACKAGE DESCRIPTION 0°C–70°C TAS5630BPHD 64-pin HTQFP 0°C–70°C TAS5630BDKD 44-pin PSOP3 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 3 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) VALUE UNIT VDD to AGND –0.3 to 13.2 V GVDD to AGND –0.3 to 13.2 V PVDD_X to GND_X (2) –0.3 to 69 V OUT_X to GND_X (2) –0.3 to 69 V BST_X to GND_X (2) –0.3 to 82.2 V BST_X to GVDD_X (2) –0.3 to 69 V VREG to AGND –0.3 to 4.2 V GND_X to GND –0.3 to 0.3 V GND_X to AGND –0.3 to 0.3 V OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND –0.3 to 4.2 V INPUT_X –0.3 to 7 V RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 to 7 V 9 mA 0 to 150 °C Continuous sink current (SD, OTW1, OTW2, CLIP, READY) Operating junction temperature range, TJ Storage temperature, Tstg Human-body model (3) (all pins) Electrostatic discharge (1) (2) (3) Charged-device model (3) (all pins) –40 to 150 °C ±2 kV ±500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Ensure operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V 3.5 4 1.8 2 2.4 3 7 10 7 15 7 10 Nominal 385 400 415 AM1 315 333 350 AM2 260 300 335 RL(BTL) RL(SE) (2) RL(PBTL) Load impedance Output filter according to schematics in the application information section (1) (2) LOUTPUT(BTL) LOUTPUT(SE) (2) LOUTPUT(PBTL) Output filter inductance (1) Minimum output inductance at IOC (2) PWM frame rate selectable for AM interference avoidance; 1% resistor tolerance. fPWM Nominal; master mode RFREQ_ADJ VFREQ_ADJ ROCP PWM frame-rate-programming resistor Voltage on FREQ_ADJ pin for slave mode operation Overcurrent-protection-programming resistor, cycle-by-cycle mode Overcurrent-protection-programming resistor, latching mode TJ (1) (2) 4 Ω μH 9.9 10 10.1 AM1; master mode 19.8 20 20.2 AM2; master mode 29.7 30 30.3 Slave mode 3.3 kΩ V 64-pin QFP package (PHD) 22 33 44-Pin PSOP3 package (DKD) 24 33 PHD or DKD 47 68 0 125 Junction temperature kHz kΩ °C Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component rating. See additional details for SE and PBTL in the System Design Considerations section. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 PIN FUNCTIONS PIN Function (1) DESCRIPTION 10 P Analog ground 43 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required. 41 34 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required. 40 33 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required. BST_D 27 24 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required. CLIP 18 — O Clipping warning; open drain; active-low NAME PHD NO. DKD NO. AGND 8 BST_A 54 BST_B BST_C C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode FREQ_ADJ 12 14 I PWM frame-rate-programming pin requires resistor to AGND 7, 23, 24, 57, 58 9 P Ground GND_A 48, 49 38 P Power ground for half-bridge A GND_B 46, 47 37 P Power ground for half-bridge B GND_C 34, 35 30 P Power ground for half-bridge C GND_D GND 32, 33 29 P Power ground for half-bridge D GVDD_A 55 — P Gate-drive voltage supply requires 0.1-μF capacitor to GND_A GVDD_B 56 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_B GVDD_C 25 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_C GVDD_D 26 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_D GVDD_AB — 44 P Gate drive voltage supply requires 0.22-μF capacitor to GND_A/GND_B GVDD_CD — 23 P Gate drive voltage supply requires 0.22-μF capacitor to GND_C/GND_D INPUT_A 4 6 I Input signal for half-bridge A INPUT_B 5 7 I Input signal for half-bridge B INPUT_C 10 12 I Input signal for half-bridge C INPUT_D 11 13 I Input signal for half-bridge D M1 20 20 I Mode selection M2 21 21 I Mode selection M3 22 22 I Mode selection NC 59–62 – — No connect; pins may be grounded. OC_ADJ 1 3 O Analog overcurrent-programming pin requires resistor to AGND. 64-pin package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ OSC_IO+ 13 15 I/O Oscillator master/slave output/input OSC_IO– 14 16 I/O Oscillator master/slave output/input OTW — 18 O Overtemperature warning signal, open-drain, active-low OTW1 16 — O Overtemperature warning signal, open-drain, active-low OTW2 17 — O Overtemperature warning signal, open-drain, active-low OUT_A 52, 53 39, 40 O Output, half-bridge A OUT_B 44, 45 36 O Output, half-bridge B OUT_C 36, 37 31 O Output, half-bridge C OUT_D 28, 29 27, 28 O Output, half-bridge D 63 1 P PSU reference requires close decoupling of 330 pF to AGND. PVDD_A 50, 51 41, 42 P Power-supply input for half-bridge A requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_A. PVDD_B 42, 43 35 P Power-supply input for half-bridge B requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_B. PVDD_C 38, 39 32 P Power-supply input for half-bridge C requires close decoupling of 0.0- μF capacitor in parallel with 2.2-μF capacitor to GND_C. PSU_REF (1) I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 5 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME PVDD_D READY Function (1) DESCRIPTION PHD NO. DKD NO. 30, 31 25, 26 P Power-supply input for half-bridge D requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_D. 19 19 O Normal operation; open-drain; active-high RESET 2 4 I Device reset input; active-low SD 15 17 O Shutdown signal, open-drain, active-low VDD 64 2 P Power supply for digital voltage regulator requires a 10-μF capacitor in parallel with a 0.1-μF capacitor to GND for decoupling. VI_CM 6 8 O Analog comparator reference node requires close decoupling of 1 nF to AGND. VREG 9 11 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND. 6 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL SYSTEM BLOCK DIAGRAM ANALOG_IN_B OSC_IO- BST_A VI_CM /CLIP READY BST_B OUT_A INPUT_A Input DC Blocking Caps ANALOG_IN_A OSC_IO+ C_STARTUP Oscillator Synchronization /OTW1, /OTW2, /OTW /SD /RESET (2) PSU_REF Caps for External Filtering & Startup/Stop System microcontroller or Analog circuitry Input H-Bridge 1 INPUT_B Output H-Bridge 1 2 OUT_B 2 Hardwire PWM Frame Rate Adjust & Master/Slave Mode ANALOG_IN_D nd OUT_C Output H-Bridge 2 Input H-Bridge 2 INPUT_D 2 OUT_D 8 50V PVDD 12V PVDD Power Supply Decoupling SYSTEM Power Supplies GND 8 BST_D OC_ADJ VREG AGND VDD M3 2 Order L-C Output Filter for each H-Bridge BST_C GND M2 GND_A, B, C, D PVDD_A, B, C, D M1 GVDD_A, B, C, D 2 Hardwire Mode Control nd 2 Order L-C Output Filter for each H-Bridge 2-CHANNEL H -BRIDGE BTL MODE INPUT_C Input DC Blocking Caps ANALOG_IN_C FREQ_ADJ Bootstrap Caps Bootstrap Caps 4 GVDD, VDD, & VREG Power Supply Decoupling Hardwire OverCurrent Limit GND GVDD (12V)/VDD (12V) VAC Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 7 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM /CLIP READY /OTW1 /OTW2 /SD PROTECTION & I/O LOGIC M1 M2 M3 /RESET C_STARTUP VDD POWER-UP RESET UVP VREG VREG AGND TEMP SENSE STARTUP CONTROL GVDD_A GVDD _C GVDD_B OVER-LOAD PROTECTION GND GVDD_D CURRENT SENSE CB3C OC_ADJ OSC_SYNC_IO+ OSC_SYNC_IO- 4 OSCILLATOR PPSC FREQ_ADJ 4 4 PVDD_X OUT_X GND_X GVDD_A PWM ACTIVITY DETECTOR 4 PSU_REF BST_A PVDD_A PVDD_X PSU_FF VI_CM GND PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_A GND_A GVDD_B INPUT_A ANALOG LOOP FILTER BST_B + PVDD_B + INPUT_D ANALOG LOOP FILTER - + ANALOG COMPARATOR MUX INPUT_C ANALOG LOOP FILTER ANALOG INPUT MUX INPUT_B PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE GND_B GVDD_C BST_C PVDD_C PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE + ANALOG LOOP FILTER OUT_B OUT_C GND_C - GVDD_D BST_D PVDD_D PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_D GND_D 8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 AUDIO CHARACTERISTICS (BTL) PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 680 nF, MODE = 010, unless otherwise noted. PARAMETER PO TEST CONDITIONS Power output per channel MIN TYP MAX RL = 4 Ω, 10% THD+N, clipped output signal 300 RL = 6 Ω, 10% THD+N, clipped output signal 210 RL = 8 Ω, 10% THD+N, clipped output signal 160 RL = 4 Ω, 1% THD+N, unclipped output signal 240 RL = 6 Ω, 1% THD+N, unclipped output signal 160 RL = 8 Ω, 1% THD+N, unclipped output signal UNIT W 125 THD+N Total harmonic distortion + noise 1W Vn Output integrated noise A-weighted, AES17 filter, input capacitor grounded |VOS| Output offset voltage Inputs ac-coupled to AGND SNR Signal-to-noise ratio (1) A-weighted, AES17 filter 100 dB DNR Dynamic range A-weighted, AES17 filter 100 dB 2.7 W Pidle (1) (2) Power dissipation due to idle losses (IPVDD_X) 0.03% PO = 0, four channels switching μV 270 20 (2) 50 mV SNR is calculated relative to 1% THD+N output level. Actual system idle losses also are affected by core losses of output inductors. AUDIO SPECIFICATION (Single-Ended Output) PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 15 μH, CDEM = 470 μF, MODE = 100, unless otherwise noted. PARAMETER PO TEST CONDITIONS Power output per channel MIN TYP MAX RL = 2 Ω, 10% THD+N, clipped output signal 145 RL = 3 Ω, 10% THD+N, clipped output signal 100 RL = 4 Ω, 10% THD+N, clipped output signal 75 RL = 2 Ω, 1% THD+N, unclipped output signal 110 RL = 3 Ω, 1% THD+N, unclipped output signal 75 RL = 4 Ω, 1% THD+N, unclipped output signal UNIT W 55 THD+N Total harmonic distortion + noise 1W Vn Output integrated noise A-weighted, AES17 filter, input capacitor grounded 340 μV SNR Signal-to-noise ratio (1) A-weighted, AES17 filter 93 dB DNR Dynamic range A-weighted, AES17 filter 93 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2) 2 W (1) (2) 0.07% SNR is calculated relative to 1% THD+N output level. Actual system idle losses are affected by core losses of output inductors. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 9 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com AUDIO SPECIFICATION (PBTL) PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 3 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 1.5 μF, MODE = 101-10, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX RL = 3 Ω, 10% THD+N, clipped output signal 400 RL = 4 Ω, 10% THD+N, clipped output signal 300 RL = 3 Ω, 1% THD+N, unclipped output signal 310 UNIT PO Power output per channel THD+N Total harmonic distortion + noise 1W Vn Output integrated noise A-weighted 260 μV SNR Signal to noise ratio (1) A-weighted 100 dB DNR Dynamic range A-weighted 100 dB Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, four channels switching (2) 2.7 W RL = 4 Ω, 1% THD+N, unclipped output signal (1) (2) W 230 0.05% SNR is calculated relative to 1% THD-N output level. Actual system idle losses are affected by core losses of output inductors. ELECTRICAL CHARACTERISTICS PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION VREG Voltage regulator, only used as reference node, VREG VI_CM Analog comparator reference node, VI_CM IVDD VDD supply current IGVDD_X GVDD_x gate-supply current per half-bridge IPVDD_X Half-bridge supply current VDD = 12 V 3 1.75 3.3 3.6 V 2 2.15 V Operating, 50% duty cycle 22.5 Idle, reset mode 22.5 50% duty cycle 12.5 Reset mode mA mA 1.5 50% duty cycle with recommended output filter 13.3 mA Reset mode, No switching 870 μA 33 kΩ 5 VPP ANALOG INPUTS RIN Input resistance READY = HIGH VIN Maximum input voltage with symmetrical output swing IIN Maximum input current 342 μA G Voltage gain (VOUT/VIN) 23 dB OSCILLATOR Nominal, master mode fOSC_IO+ AM1, master mode FPWM × 10 AM2, master mode VIH High level input voltage VIL Low level input voltage 3.85 4 4.15 3.15 3.33 3.5 2.6 3 3.35 1.86 MHz V 1.45 V 60 100 mΩ 60 100 mΩ OUTPUT-STAGE MOSFETs RDS(on) 10 Drain-to-source resistance, low side (LS) Drain-to-source resistance, high side (HS) TJ = 25°C, excludes metallization resistance, GVDD = 12 V Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I/O PROTECTION Undervoltage protection limit, GVDD_x and VDD Vuvp,G Vuvp,hyst (1) 9.5 V 0.6 V (1) Overtemperature warning 1 95 100 105 °C OTW2 (1) Overtemperature warning 2 115 125 135 °C OTWhyst Temperature drop needed below OTW temperature for OTW to be inactive after OTW event OTW1 (1) 25 Overtemperature error OTE (1) 145 155 °C 165 °C OTE-OTW differential 30 °C A reset must occur for SD to be released following an OTE event. 25 °C fPWM = 400 kHz 2.6 ms Resistor – programmable, nominal peak current in 1-Ω load, 64-pin QFP package (PHD) ROCP = 22 kΩ 15 A Resistor – programmable, nominal peak current in 1-Ω load, 44-Pin PSOP3 package (DKD), ROCP = 24 kΩ 15 A Overcurrent limit protection, latched Resistor – programmable, nominal peak current in 1-Ω load, ROCP = 47 kΩ 15 A IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent 150 ns IPD Internal pulldown resistor at output of each half-bridge Connected when RESET is active to provide bootstrap charge. Not used in SE mode 3 mA OTEhyst (1) OLPC Overload protection counter Overcurrent limit protection IOC STATIC DIGITAL SPECIFICATIONS VIH High-level input voltage VIL Low-level input voltage Ilkg Input leakage current M1, M2, M3, RESET 2 V 0.8 V 100 μA kΩ OTW/SHUTDOWN (SD) RINT_PU Internal pullup resistance, OTW, OTW1, OTW2, CLIP, READY, SD to VREG VOH High-level output voltage VOL Low-level output voltage IO = 4 mA FANOUT Device fanout OTW, OTW1, OTW2, SD, CLIP, READY No external pullup (1) Internal pullup resistor External pullup of 4.7 kΩ to 5 V 20 26 32 3 3.3 3.6 4.5 V 5 200 30 500 mV devices Specified by design. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 11 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC+NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 340 10 THD+N − Total Harmonic Distortion + Noise − % 4Ω 6Ω 8Ω 4Ω 6Ω 8Ω 320 300 280 260 PO − Output Power − W 1 0.1 240 220 200 180 160 140 120 100 80 60 40 0.01 0.005 20m 100m 1 10 100 0 400 PO − Output Power − W UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE SYSTEM EFFICIENCY vs OUTPUT POWER Efficiency − % PO − Output Power − W 200 180 160 140 120 100 80 60 40 20 TC = 75°C 30 35 40 PVDD − Supply Voltage − V 45 50 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 4Ω 6Ω 8Ω 0 50 100 TC = 25°C THD+N at 10% 200 300 400 500 2 Channel Output Power − W G001 Figure 3. 12 45 G001 220 25 35 40 PVDD − Supply Voltage − V Figure 2. 240 0 30 G001 4Ω 6Ω 8Ω 260 25 Figure 1. 300 280 TC = 75°C THD+N at 10% 20 TC = 75°C 600 700 G001 Figure 4. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 OUTPUT POWER vs CASE TEMPERATURE 340 4Ω 6Ω 8Ω 320 300 280 260 PO − Output Power − W Power Loss − W SYSTEM POWER LOSS vs OUTPUT POWER 240 220 200 180 160 140 120 100 80 60 0 100 200 300 400 500 2 Channel Output Power − W 600 4Ω 6Ω 8Ω 40 TC = 25°C THD+N at 10% 20 0 −10 700 0 10 THD+N at 10% 20 30 40 50 60 70 80 90 100 110 TC − Case Temperature − °C G001 Figure 5. G001 Figure 6. NOISE AMPLITUDE vs FREQUENCY 0 TC = 75°C VREF = 35.36 V Sample Rate = 48kHz FFT Size = 16384 −10 −20 −30 4Ω Noise Amplitude − dB −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k f − Frequency − Hz G001 Figure 7. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 13 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION 1 Channel Driven TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 170 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 160 150 140 130 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 120 110 100 90 80 70 60 50 40 30 20 0.01 0.005 20m 100m 1 10 0 100 200 PO − Output Power − W TC = 75°C THD+N at 10% 10 TC = 75°C 25 30 35 40 PVDD − Supply Voltage − V G001 45 50 G001 Figure 8. Figure 9. OUTPUT POWER vs CASE TEMPERATURE 180 170 160 150 140 PO − Output Power − W 130 120 110 100 90 80 70 60 50 40 30 2Ω 3Ω 4Ω 20 10 0 −10 0 10 THD+N at 10% 20 30 40 50 60 70 80 TC − Case Temperature − °C 90 100 110 G001 Figure 10. 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 500 3Ω 4Ω 6Ω 8Ω 3Ω 4Ω 6Ω 8Ω 450 400 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 350 300 250 200 150 100 50 0.01 TC = 75°C THD+N at 10% TC = 75°C 0.005 20m 100m 1 10 100 0 700 PO − Output Power − W 25 30 35 40 PVDD − Supply Voltage − V 45 G001 50 G001 Figure 11. Figure 12. OUTPUT POWER vs CASE TEMPERATURE 500 450 PO − Output Power − W 400 350 300 250 200 150 100 3Ω 4Ω 6Ω 8Ω 50 0 −10 0 10 THD+N at 10% 20 30 40 50 60 70 80 TC − Case Temperature − °C 90 100 110 G001 Figure 13. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 15 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 2-oz. (70-μm) glass epoxy material is recommended for use with the TAS5630B. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace resistance). PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed system power supply, 1000 μF, 63-V supports more applications. The PVDD capacitors should be the low-ESR type, because they are used in a circuit associated with high-speed switching. DECOUPLING CAPACITOR RECOMMENDATIONS To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, quality decoupling capacitors should be used. In practice, X7R should be used in this application. The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 2.2-μF capacitor that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V power supply. SYSTEM DESIGN RECOMMENDATIONS The following schematics and PCB layouts illustrate best practices used for the TAS5630B. 16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B R_RIGHT_N IN_RIGHT_P IN_LEFT_N IN_LEFT_P /RESET 10uF C16 10uF C14 10uF C12 10uF C10 C17 100pF C15 100pF C13 100pF C11 100pF C18 100pF READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ 100R R13 100R R12 100R R11 100R R10 100R R18 GND VREG GND R19 47k GND GND GND GND GND 10k R21 100nF C22 VREG 1nF C21 4.7nF 22.0k C20 R20 330pF GND 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ GND C26 100nF 63 PSU_REF 61 GND 59 C31 100nF U10 C33 100nF GND GND GND C32 100nF 3.3R 3.3R R33 R32 C43 33nF TAS5630BPHD VREG C30 100nF GND 3.3R 60 NC READY C23 C25 10uF GND 64 VDD /OTW2 17 /CLIP 18 GVDD_C 62 NC M1 19 NC 20 M3 22 M2 21 NC 57 GND C40 33nF C63 2.2uF GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND C60 2.2uF GVDD_D 26 R31 27 3.3R BST_D 53 28 52 OUT_A OUT_D 56 GVDD_B 55 GVDD_A 54 BST_A OUT_A OUT_D 29 51 PVDD_A PVDD_D 30 50 PVDD_A PVDD_D 49 GND_A GND_D 31 58 GND GND 23 Product Folder Links: TAS5630B 24 Copyright © 2010–2012, Texas Instruments Incorporated 25 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 GND C62 2.2uF C61 2.2uF GND L13 7uH 7uH L12 C42 33nF C41 33nF L11 7uH L10 7uH 1000uF C65 C53 680nF C52 680nF GND C51 680nF C50 680nF C72 1nF GND C73 1nF GND 1000uF C66 C71 1nF GND C70 1nF R73 3.3R C77 10nF C76 10nF R72 3.3R GND GND C68 47uF 63V R71 3.3R C75 10nF C74 10nF R70 3.3R GND C67 1000uF GND GND C69 2.2uF GND C64 1000uF GND PVDD GND PVDD GVDD/VDD (+12V) OUT_RIGHT_P + - GND OUT_RIGHT_M C78 10nF R74 3.3R OUT_LEFT_P + - OUT_LEFT_M PVDD GVDD/VDD (+12V) www.ti.com 32 R30 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Figure 14. Typical Differential-Input BTL Application With BD Modulation Filters Submit Documentation Feedback 17 READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_N IN_P /RESET 10uF 10uF 100R 100R 100R GND GND GND 100pF 100pF 100pF GND VREG 47k VREG GND GND GND GND GND 10k 100nF 1nF 4.7nF 22.0k VREG GND GND 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 GND GND 100nF /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ 330pF 10uF 64 VDD /OTW2 17 63 PSU_REF /CLIP 18 100nF 60 GND GND GND 100nF 33nF GND 100nF VREG GND GND GND 100nF 3.3R 33nF 3.3R TAS5630BPHD GVDD_C 61 62 NC READY 19 NC M2 21 M3 22 NC 59 NC 3.3R 26 56 GVDD_B 3.3R GVDD_D 53 27 58 GND GND 23 M1 55 GVDD_A BST_D 52 OUT_A OUT_D 28 57 GND GND 24 Product Folder Links: TAS5630B 25 Submit Documentation Feedback 20 54 BST_A OUT_A OUT_D 29 51 PVDD_A PVDD_D 30 49 GND_A GND_D 50 PVDD_A PVDD_D 31 18 32 VDD (+12V) 2.2uF 100V GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND 2.2uF 100V 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 GND 2.2uF 100V 2.2uF 100V GND 33nF 33nF 7uH 7uH 7uH 7uH 1000uF 63V 1000uF 63V 1uF 250V GND 1uF 250V 1000uF 63V 1000uF 63V GND GND 1nF 100V 1nF 100V GND GND 47uF 63V GND 3.3R 10nF 100V 10nF 100V 3.3R GND 10nF 100V + GVDD (+12V) PVDD OUT_LEFT_P GND OUT_LEFT_M GND 2.2uF 100V 3.3R PVDD GVDD (+12V) TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Figure 15. Typical Differential (2N) PBTL Application With BD Modulation Filters Copyright © 2010–2012, Texas Instruments Incorporated READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_D IN_C IN_B IN_A /RESET Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 147kW 165kW 187kW 191kW 50V 49V 48V <48V GND GND GND GND R_COMP 100R 100R 100R GND 100pF 100pF 100pF 100pF 100pF PVDD PVDD C A Submit Documentation Feedback 470uF 50V 470uF 50V 470uF 50V 470uF 50V GND GND GND GND GND GND GND R_COMP R_COMP 10k 1% 10k 1% 10k 1% 10k 1% 10k 100nF 1nF 10nF 22.0k VREG GND 10k 10k GND 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 470nF 250V 470nF 250V /OTW1 /SD OSC_IO- OSC_IO+ 64 100nF 100V 100nF 100V 100nF 100V 100nF 100V FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ 330pF 100nF GND GND 10nF 100V 100V 10nF 3.3R 3.3R 10nF 100V 100V 10nF 3.3R GND GND OUT_C_P + - OUT_C_M GND GND OUT_A_P + - OUT_A_M 100nF VREG GND PVDD PVDD D B GND GND 100nF 52 3.3R 33nF TAS5630BPHD 3.3R GND GND GND GND 100nF 470uF 50V 470uF 50V 470uF 50V 470uF 50V 3.3R 3.3R 33nF 50 51 GND GND 1% 10k 1% 10k R_COMP 1% 10k 1% 10k R_COMP 2.2uF GND_D GND_C GND_C 10k 10k OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND 2.2uF 48 47 33 34 35 36 37 38 39 40 41 42 43 44 45 46 470nF 250V 470nF 250V 100nF 100V 100nF 100V 100nF 100V 100nF 100V GND 2.2uF 2.2uF GND 33nF 33nF GND GND 10nF 100V 47uF 63V 100V 10nF 3.3R 3.3R 10nF 100V 100V 10nF 3.3R 3.3R 15uH 15uH 15uH 15uH GND GND OUT_D_P + - OUT_D_M GND GND OUT_B_P + - OUT_B_M GND GND 2.2uF GND 10nF 3.3R GVDD (+12V) D PVDD C PVDD B PVDD A GVDD (+12V) www.ti.com PVDD 10uF 10uF 10uF 10uF 100R 100R 47k 62 NC GND GND 61 NC VREG 100nF 54 BST_A 3.3R 49 GND_A 10uF 60 NC M2 21 VDD 17 59 NC M3 22 /OTW2 58 GND GND 23 63 PSU_REF 18 57 GND GND 24 /CLIP 56 GVDD_B GVDD_C 25 READY 19 55 GVDD_A GVDD_D 26 M1 20 53 OUT_A OUT_D 28 BST_D 27 OUT_A OUT_D 29 PVDD_A PVDD_D 30 PVDD_A PVDD_D 31 GND_D 32 VDD (+12V) TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Figure 16. Typical SE Application 19 READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_RIGHT IN_LEFT IN_CENTER_N IN_CENTER_P /RESET 10uF 10uF 10uF 10uF 100R 100R 100R 100R 100R GND GND GND GND GND 100pF 100pF 100pF 100pF 100pF 47k VREG GND GND GND GND GND 10k 100nF VREG 1nF 10nF 22.0k GND GND 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND GND 100nF /OTW1 /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ 330pF 10uF 64 VDD /OTW2 17 63 PSU_REF /CLIP 18 62 19 61 100nF NC VDD (+12V) GND GND GND 100nF 33nF 3.3R 3.3R VREG GND 100nF GND GND GND 100nF 3.3R 3.3R 33nF TAS5630BPHD GVDD_D 26 60 NC M2 21 READY 55 GVDD_A BST_D 59 NC M3 22 NC 54 BST_A 28 27 51 OUT_D 58 GND GND 23 M1 53 OUT_A OUT_D 29 50 PVDD_A PVDD_D 57 GND GND 24 Product Folder Links: TAS5630B 25 Submit Documentation Feedback 20 52 OUT_A PVDD_A PVDD_D 30 56 GVDD_B GVDD_C 49 GND_A GND_D 31 20 32 2.2uF 100V GND_D GND_C GND_C OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND_B GND_B GND_A GND 2.2uF 100V 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 GND 2.2uF 100V 2.2uF 100V GND 15uH PVDD 15uH PVDD 33nF 33nF GND 10k 1% 10k 1% 10k 1% 470uF 50V 470uF 50V GND R_COMP 10k 1% 470uF 50V GND R_COMP GND 47uF 63V 470uF 50V 1000uF 63V GND 10k 10k 10nF 100V 3.3R GND 2.2uF 100V 7uH 680nF 250V GND 680nF 250V 7uH GND 470nF 250V GND GND 470nF 250V GND 100V 10nF 100nF 100V 100nF 100V 10nF 100V 100V 10nF 100nF 100V 100nF 100V 10nF 100V 1nF 100V 1nF 100V 1000uF 63V 3.3R GND 3.3R 3.3R GND 3.3R 3.3R 10nF 100V 10nF 100V 3.3R GND GVDD (+12V) PVDD OUT_RIGHT_P + - OUT_RIGHT_M OUT_LEFT_P + - OUT_LEFT_M PVDD OUT_CENTER_P GND + - OUT_CENTER_M PVDD GVDD (+12V) TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Figure 17. Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application Copyright © 2010–2012, Texas Instruments Incorporated Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B READY /OTW /SD OSC_IO- 10uF 10uF 10uF 10uF 100R R60 100R R53 100R R54 100R R45 100R R13 C81 100pF C80 100pF C79 100pF C82 100pF GND C78 100pF VREG R44 47k GND GND GND GND GND GND R20 10k C86 100nF GND GND VREG 22 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 10 VREG GND 1nF GND C35 100nF C42 C85 4.7nF 24k C45 R14 330pF C44 10uF M3 M2 M1 READY /OTW /SD OSC_IO- OSC_IO+ FREQ_ADJ INPUT_D GVDD_CD BST_D PVDD_D PVDD_D OUT_D OUT_D GND_D GND_C OUT_C PVDD_C BST_C BST_B PVDD_B OUT_B GND_B GND_A OUT_A OUT_A PVDD_A PVDD_A BST_A GVDD_AB TAS5630BDKD INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP /RESET OC_ADJ VDD PSU_REF U12 100nF C89 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 R31 GND 100nF C84 33nF C88 1.5R 33nF 33nF GND C37 C41 GND 33nF C33 GND C87 100nF C34 2.2uF C91 2.2uF C90 2.2uF C83 2.2uF GND 7uH 680nF 250V GND GND 63V 1000uF 680nF 250V 7uH GND 63V 1000uF 7uH 680nF 250V GND 680nF 250V 7uH 1nF 100V 1nF 100V GND 1000uF 63V 47uF 63V 1nF 100V 1nF 100V 1000uF 63V GND 3.3R 10nF 100V 10nF 100V 3.3R GND GND + OUT_RIGHT_P GND OUT_RIGHT_M 10nF 100V 3.3R OUT_LEFT_P + - OUT_LEFT_M GND 2.2uF 100V 3.3R 10nF 100V 10nF 100V 3.3R GND GVDD (+12V) PVDD PVDD PVDD GVDD (+12V) www.ti.com OSC_IO+ IN_RIGHT_N IN_RIGHT_P IN_LEFT_N IN_LEFT_P /RESET VDD (+12V) C38 100nF R34 1.5R TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Figure 18. Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package Submit Documentation Feedback 21 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge. To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300 kHz to 400 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 2.2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5630B reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5630B is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The TAS5630B does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. Powering Down The TAS5630B does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks. 22 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 ERROR REPORTING The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds 100°C (see the following table). SD OTW1 OTW2, OTW 0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) 0 0 1 Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature warning) 0 1 1 Overload (OLP) or undervoltage (UVP) 1 0 0 Junction temperature higher than 125°C (overtemperature warning) 1 0 1 Junction temperature higher than 100°C (overtemperature warning) 1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation) DESCRIPTION Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics table of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The TAS5630B contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5630B responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, i.e., the supply voltage has increased. The device functions on errors, as shown in the following table. BTL Mode Local error in A B C D PBTL Mode Turns Off or in A+B C+D Local error in Turns Off or in A B C SE Mode Local error in Turns Off or in A A+B+C+D D B C D A+B C+D Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge. PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC) The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence and starts switching. The detection is controlled globally by a two-step sequence. The first step ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 23 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure the PPSC detection system is not tripped, it is recommended not to insert resistive load between OUT_X and GND_X or PVDD_X. OVERTEMPERATURE PROTECTION The two different package options have individual overtemperature protection schemes. PHD Package: The TAS5630B PHD package option has a three-level temperature-protection system that asserts an active-low warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. For highest reliability, the RESET should not be asserted until OTW1 has cleared. DKD Package: The TAS5630B DKD package option has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. It is recommended to wait until OTW has cleared before asserting RESET. Thereafter, the device resumes normal operation. UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR) The UVP and POR circuits of the TAS5630B fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach the levels stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the highimpedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. DEVICE RESET When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance (Hi-Z) state. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD output; i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD. SYSTEM DESIGN CONSIDERATIONS A rising-edge transition on the reset input allows the device to execute the startup sequence and starts switching. Apply audio only when the state of READY is high; that starts and stops the amplifier without having audible artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller systems. The CLIP signal indicates that the output is approaching clipping. The signal can be used either to activate a volume decrease or to signal an intelligent power supply to increase the rail voltage from low to high for optimum efficiency. The device inverts the audio signal from input to output. 24 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 The VREG pin is not recommended to be used as a voltage source for external circuitry. Click and Pop in SE-Mode The BTL startup has low click and pop due to the trimmed output dc offset, see the AUDIO CHARACTERISTICS (BTL) table. The startup of the BTL+2 x SE system (Figure 17) or 4xSE (Figure 16) is more difficult to get click and pop free, than the pure BTL solution; therefore, evaluating the resulting click and pop before designing in the device is recommended. PBTL Overload and Short Circuit The TAS5630B has extensive overload and short circuit protection. In BTL and SE mode, it is fully protected against speaker terminal overloads, terminal-to-terminal short circuit, and short circuit to GND or PVDD. The protection works by limiting the current, by flipping the state of the output MOSFET’s; thereby, ramping currents down in the inductor. This only works when the inductor is NOT saturated, the recommended minimum inductor values are listed in RECOMMENDED OPERATING CONDITIONS table. In BTL mode, the short circuit currents can reach more than 15A, so when connecting the device in PBTL mode (Mono), the currents double – that is more than 30A, and with these high currents, the protection system will limit PBTL speaker overloads, terminalto-terminal shorts, and terminal-to-GND shorts. PBTL mode short circuit to PVDD is not recommended. OSCILLATOR The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin. To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency can be changed from nominal to lower values. These values should be chosen such that the nominal and the lower-value switching frequencies together result in the fewest cases of interference throughout the AM band, and can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode. For slave-mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the OSC_I/O pins as inputs, which must be slaved from an external clock. PRINTED CIRCUIT BOARD RECOMMENDATION Use an unbroken ground plane to have a good low-impedance and -inductance return path to the power supply for power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing of the audio input should be kept short and together with the accompanying audio-source ground. A local ground area underneath the device is important to keep solid to minimize ground bounce. It is always good practice to follow the EVM layout as a guideline. Netlist for this printed circuit board is generated from the schematic in Figure 14. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 25 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and close to the pins. This is valid for C60, C61, C62, and C63. Note T3: Heat sink must have a good connection to PCB ground. Note T4: Output filter capacitors must be linear in the applied voltage range, preferably metal film types. Figure 19. Printed Circuit Board – Top Layer 26 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep impedance low from top to bottom side of PCB through a lot of ground vias. Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance current loop. Note B3: Return currents from bulk capacitors and output filter capacitors Figure 20. Printed Circuit Board – Bottom Layer Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 27 TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A Page • Changed Title From: 600-W MONO To 400-W MONO ........................................................................................................ 1 • Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL Configuration ......................................................................................................................................................................... 1 • Changed the Pin One Location Package image ................................................................................................................... 2 • Replaced the PACKAGE HEAT DISSIPATION RATINGS table with the THERMAL INFORMATION table ....................... 3 • Changed RL(PBTL) Load Impedance Min value From: 1.6 Ω To: 2.4 Ω, and Typ value From 2 To: 3 Ω ............................ 4 • Added footnotes • Added ROCP information to the ROC Table ........................................................................................................................... 4 • Deleted - RL = 2 Ω, 10%, THD+N, clipped input signal From PO in the Audio Specification (PBTL) table ........................ 10 • Changed the IOC Typical Value From: 19 A To: 15 A ......................................................................................................... 11 • Replaced the TYPICAL CHARACTERISTICS, PBTL CONFIGURATION graphs ............................................................. 15 • Added section - Click and Pop in SE-Mode ....................................................................................................................... 25 • Added section - PBTL Overload and Short Circuit ............................................................................................................. 25 (1) (2) (1) and (2) to the ROC table ........................................................................................................................ 4 See additional details for SE and PBTL in the System Design Considerations section. Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component rating. Changes from Revision A (November 2011) to Revision B Page • Changed the RINT_PU parameters From: OTW1 to VREG, OTW2 to VREG, SD to VREG To: OTW, OTW1, OTW2, CLIP, READY, SD to VRE .................................................................................................................................................. 11 • Added text to the PHD Package section. ........................................................................................................................... 24 • Added text to the DKD Package section ............................................................................................................................ 24 Changes from Revision B (November 2011) to Revision C Page • Deleted - RL = 2 Ω, 1% THD+N, unclipped output signal From PO in the Audio Specification (PBTL) table ..................... 10 • Changed Analog comparator reference node, VI_CM Vlaues From: MIN = 1.5 TYP = 1.75 MAX = 1.9 To: MIN = 1.75 TYP = 2 MAX = 2.15 ................................................................................................................................................... 10 • Changed ANALOG INPUTS - VIN TYP value From 3.5 to 5 VPP ........................................................................................ 10 • Changed the VIH and VIL Test Conditions From: INPUT_X, M1, M2, M3, RESET To: M1, M2, M3, RESET .................... 11 28 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5630BDKDR HSSOP DKD 44 500 330.0 24.4 TAS5630BPHDR HTQFP PHD 64 1000 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.0 Q1 17.0 17.0 1.5 20.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5630BDKDR HSSOP DKD TAS5630BPHDR HTQFP PHD 44 500 367.0 367.0 45.0 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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