Low Voltage Bias Stabilizer with Enable MDC5001T1 SILICON SMALLBLOCKTM • Maintains Stable Bias Current in N–Type Discrete Bipolar Junction and Field Effect Transistors INTEGRATED CIRCUIT • Provides Stable Bias Using a Single Component Without Use of Emitter Ballast and Bypass Components • Operates Over a Wide Range of Supply Voltages Down to 1.8 Vdc • Reduces Bias Current Variation Due to Temperature and Unit–to–Unit Parametric Changes • Consumes <0.5 mW at V CC = 2.75 V • Active High Enable is CMOS Compatible This device provides a reference voltage and acts as a DC feedback ele- 6 5 4 1 2 3 SOT-363 CASE 419B–01 STYLE 19 ment around an external discrete, NPN BJT or N–Channel FET. It allows the external transistor to have its emitter/source directly grounded and still operate with a stable collector/drain DC current. It is primarily intended to stabilize the bias of discrete RF stages operating from a low voltage regulated supply, INTERNAL CIRCUIT DIAGRAM but can also be used to stabilize the bias current of any linear stage in order to eliminate emitter/source bypassing and achieve tighter bias regulation over temperature and unit variations. The “ENABLE” polarity nulls internal current, Enable current, and RF transistor current in “STANDBY.” This device is intended to replace a circuit of three to six discrete components. The combination of low supply voltage, low quiescent current drain, and small package make the MDC5001T1 ideal for portable communications applications such as: • Cellular Telephones • Pagers • PCN/PCS Portables • GPS Receivers • PCMCIA RF Modems • Cordless Phones • Broadband and Multiband Transceivers and Other Portable Wireless Products. MDC5001T–1/10 MDC5001T1 MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage Ambient Operating Temperature Range V CC TA 15 –40 to +85 V dc °C Storage Temperature Range Junction Temperature T stg TJ –65 to +150 150 °C °C V CEO V ENBL –15 V CC V V Symbol PD Max Unit mW Collector Emitter Voltage (Q2) Enable Voltage (Pin 5) THERMAL CHARACTERISTICS Characteristic Total Device Power Dissipation (FR–5 PCB of 1, × 0.75, × 0.062,, T A = 25°C) Derate above 25°C Thermal Resistance, Junction to Ambient R θJA ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted) Characteristic Symbol Recommended Operating Supply Voltage Power Supply Current (V CC = 2.75 V) 150 1.2 mW/°C 833 °C/W Min Typ Max Unit V CC I CC 1.8 — 2.75 130 10 200 Volts mA V (BR)CEO2 15 V ref , I out are unterminated See Figure 8 Q2 Collector Emitter Breakdown Voltage (I C2 = 10 µA, I B2 = 0) Reference Voltage (V ENBL = V CC = 2.75 V, V out = 0.7 V) (I out = 30 µA) V ref (I out = 150 µA) See Figure 1 Reference Voltage (V ENBL = V –40°C < T A <+85°C) CC Volts 2.050 2.075 2.100 2.110 2.135 2.160 ±5.0 ±10 ±15 ±25 ±30 ±50 = 2.75 V, V out = 0.7 V, V CC Pulse Width = 10 mS, Duty Cycle = 1% (I out = 10 µA) (I out = 30 µA) (I out = 100 µA) Volts ∆Vref mV See Figures 2 and 11 MDC5001T–2/10 MDC5001T1 The following SPICE models are provided as a convenience to the user and every effort has been ade to insure their accuracy. However, no responsibility for their accuracy is assumed by ON Semiconductor. .MODEL Q4 NPN .MODEL Q1, Q2 PNP RESISTOR VALUES BF = 136 BR = 0.2 NE = 1.6 NF = 1.005 BF = 87 BR = 0.6 NK = 0.5 NR = 1.0 R 1 = 12 K R 2= 6 K CJC = 318.6 f CJE = 569.2 f RB = 140 RBM = 70 CJC = 800E–15 CJE = 46E–15 RB = 720 RBM = 470 R 3 = 3.4 K R 4 = 12 K CJS = 1.9 p EG = 1.215 RC = 180 RE = 1.6 EG = 1.215 FC = 0.5 RC = 180 RE = 26 R 5 = 20 K R 6 = 40 K FC = 0.5 IKF = 24.41 m TF = 553.6 p TR = 10 n IKF = 3.8E–04 IKR = 2.0 TF = 15E–9 TR = 50E–09 IKR = 0.25 IRB = 0.0004 VAF = 267.6 VAR = 12 IRB = 0.9E–3 IS = 1.027E–15 VAF = 54.93 VAR = 20 IS = 256E–18 ISC = 1 f VJC = 0.4172 VJE = 0.7245 ISC = 10E–18 ISE = 1.8E–15 VAR = 20 VJC = 0.4172 ISE = 500E–18 ITF = 0.9018 VJS = 0.39 VTF = 10 ITF = 2E–3 MJC = 0.2161 VJE = 0.4172 VTF = 10 MJC = 0.2161 MJE = 0.3373 XTB = 1.5 XTF = 2.077 MJE = 0.2161 NC = 0.8 XTB = 1.5 XTF = 2.0 MJS = 0.13 NC = 1.09 XTI = 3 NE = 1.38 NF = 1.015 XTI = 3 These models can be retrieved electronically by accessing the ON Semiconductor Web page at http://design–net.sps.mot.com/models and searching the section on SMALLBLOCKE models MDC5001T–3/10 MDC5001T1 TYPICAL OPEN LOOP CHARACTERISTICS 8 7 6 V ref( V dc) 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 V CC, SUPPLY VOLTAGE (V dc) Figure 1. V ref versus V CC @ I out MDC5001T–4/10 MDC5001T1 TYPICAL OPEN LOOP CHARACTERISTICS (Refer to Circuits of Figures 10 through 15) 900 40 800 I CC, SUPPLY CURRENT (µAdc) 50 ∆V ref (mA) 30 20 10 0 -10 -20 -30 -40 700 600 500 400 300 200 100 0 -50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 0 85 1 2 4 5 6 7 8 9 10 V CC , SUPPLY VOLTAGE (V dc) Figure 3. I CC versus V CC @ T J T J , JUNCTION TEMPERATURE (°C) Figure 2. ∆V ref versus T J @ I out 1000 160 500 140 300 120 200 I ENABLE(µAdc) H FE , Q2 DC CURRENT GAIN 3 100 50 30 100 80 60 40 20 20 10 0 10 20 30 50 100 200 300 500 1000 0 0.5 1.0 1.5 2.0 2.5 I out , DC OUTPUT CURRENT (µAdc) V ENABLE (V dc) Figure 4. Q2 Current Gain versus Output Current @ T J Figure 5. I enable versus V enable 3.0 6.0 5.0 V ref (Vdc) 4.0 3.0 2.0 1.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V ENABLE (V dc) Figure 6. V ref versus V enable @ V CC and I out MDC5001T–5/10 MDC5001T1 4.0 1.0 3.0 0.5 2.0 ∆V ref (%) 1.5 0 -0.5 1.0 0 -1.0 -1.0 -1.5 -2.0 -3.0 -2.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 0 T A , AMBIENT TEMPERATURE (°C) Figure 7. ∆I C3 versus T A @ I C3 50 100 150 200 250 300 EXTERNAL TRANSISTOR DC BETA @ I C3 Figure 8. ∆V ref versus External Transistor DC Beta @ I C3 10 5.0 0 ∆I C3 (%) ∆I C3 (%) TYPICAL CLOSED LOOP PERFORMANCE (Refer to Circuits of Figures 16 & 17) -5.0 -10 -15 0 50 100 150 200 250 300 H FE , EXTERNAL TRANSISTOR DC BETA Figure 9. ∆I C3 versus External Transistor DC Beta @ I C3 MDC5001T–6/10 MDC5001T1 OPEN LOOP TEST CIRCUITS Figure 10. I CC versus V CC Test Circuit Figure 12. V ref versus T J Test Circuit Figure 14. I ENBL versus V ENBL Test Circuit Figure 11. V ref versus V CC Test Circuit Figure 13. H FE versus I out Test Circuit Figure 15. V ref versus V ENBL Test Circuit NOTE 1: V BE3 is used to simulate actual operating conditions that reduce V CE2 & H FE2 , and increase I B2 & V ref . MDC5001T–7/10 MDC5001T1 CLOSED LOOP TEST CIRCUITS Figure 17. RF Stage I C3 versus T A Test Circuit MDC5001T–8/10 MDC5001T1 APPLICATION CIRCUITS RF OUT Step 1: Choose V CC (1.8 V Min to 10 V Max) Step 2: Insure that Min V ENBL is . minimum indicated in Figures 5 and 6. Step 3: Choose bias current, I C3 , and calculate needed I out from typ H FE3 Step 4: From Figure 1, read V ref for V CC and I out calculated. • (I C3 + I out ). Tweak as desired. Step 5: Calculate Nominal R5 = (V CC – V ref ) – • Figure 18. Class A Biasing of a Typical 900 MHz BJT Amplifier Application MDC5001T–9/10 MDC5001T1 APPLICATION CIRCUITS RF OUT Step 1: Choose V CC (1.8 V Min to 10 V Max) Step 2: Insure that Min V ENBL is > minimum indicated in Figures 5 and 6. Step 3: Choose bias current, I D , and determine needed gate–source voltage, V GS . Step 4: Choose I out keeping in mind that too large an I out can impair MDC5000 ∆V ref /∆T J performance (Figure 2) but too large an R6 can cause I DGO & I GSO to bias on the FET. • I out Step 5: Calculate R6 = (V GS + E GS ) – • Step 6: From Figure 1, read V ref for V CC & I out chosen • (I D + I out) . Tweak as desired. Step 7: Calculate Nominal R5 = (V CC – V ref ) – • Figure 19. Class A Biasing of a Typical 890 MHz Depletion Mode GaAs FET Amplifier MDC5001T–10/10