Genesys Logic, Inc. GL811S USB 2.0 to ATA/ATAPI Bridge Controller Datasheet Revision 1.02 Apr. 13, 2007 GL811S USB2.0 to ATA/ATAPI Bridge Controller Copyright: Copyright © 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2007 Genesys Logic Inc. - All rights reserved. Page 2 GL811S USB2.0 to ATA/ATAPI Bridge Controller Revision History Revision Date Description 1.00 03/09/2006 First release 1.01 05/25/2006 Modify GL811S 48 Pin TQFP Package, Figure 7.2, p.37 1.02 04/13/2007 Remove 48Pin TQFP Pinout, p.9 and 48Pin TQFP Dimension, p.35 ©2007 Genesys Logic Inc. - All rights reserved. Page 3 GL811S USB2.0 to ATA/ATAPI Bridge Controller TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 7 CHAPTER 2 FEATURES .............................................................................. 8 CHAPTER 3 PIN ASSIGNMENT ................................................................ 9 3.1 PINOUTS...................................................................................................... 9 3.2 PIN LIST.................................................................................................... 11 3.3 PIN DESCRIPTIONS ................................................................................... 12 CHAPTER 4 BLOCK DIAGRAM.............................................................. 16 CHAPTER 5 FUNCTION DESCRIPTION ............................................... 17 5.1 UTM......................................................................................................... 17 5.2 SIE............................................................................................................ 17 5.3 EP0/EP3 FIFO ........................................................................................ 17 5.4 BULK FIFO .............................................................................................. 17 5.5 IDE INTERFACE ....................................................................................... 17 5.6 OPERATION REGISTER............................................................................. 17 5.7 SPI INTERFACE ........................................................................................ 17 CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 18 6.1 ABSOLUTE MAXIMUM RATINGS .............................................................. 18 6.2 TEMPERATURE CONDITIONS ................................................................... 18 6.3 DC CHARACTERISTICS ............................................................................ 18 6.3.1 I/O Type digital pins ....................................................................... 18 6.3.2 D+/ D- ............................................................................................... 19 6.3.3 Switching Characteristics............................................................... 19 6.4 AC CHARACTERISTICS- ATA/ ATAPI ................................................... 19 6.4.1 Register Transfers / PIO Data Transfers ..................................... 21 6.4.2 Multiword DMA data transfer ...................................................... 23 6.4.3 Ultra DMA data transfer................................................................ 27 6.5 AC CHARACTERISTICS - USB 2.0............................................................ 34 CHAPTER 7 PACKAGE DIMENSION..................................................... 35 CHAPTER 8 ORDERING INFORMATION ............................................ 37 ©2007 Genesys Logic Inc. - All rights reserved. Page 4 GL811S USB2.0 to ATA/ATAPI Bridge Controller LIST OF FIGURES FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM.................................................................... 9 FIGURE 3.2 - 64 PIN LQFP PINOUT DIAGRAM.................................................................. 10 FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................... 16 FIGURE 6.1 - INITIATING A MULTIWORD DMA DATA BURST.......................................... 24 FIGURE 6.2 - SUSTAINING A MULTIWORD DMA DATA BURST ........................................ 25 FIGURE 6.3 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST ....................... 25 FIGURE 6.4 - HOST TERMINATING A MULTIWORD DMA DATA BURST ........................... 26 FIGURE 6.5 - INITIATING AN ULTRA DMA DATA-IN BURST ............................................ 28 FIGURE 6.6 - SUSTAINED ULTRA DMA DATA-IN BURST .................................................. 28 FIGURE 6.7 - HOST PAUSING AN ULTRA DMA DATA-IN BURST ...................................... 29 FIGURE 6.8 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST ......................... 29 FIGURE 6.9 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST ............................. 30 FIGURE 6.10 - INITIATING AN ULTRA DMA DATA-OUT BURST ...................................... 31 FIGURE 6.11 - SUSTAINED ULTRA DMA DATA-OUT BURST ............................................ 31 FIGURE 6.12 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST ............................. 32 FIGURE 6.13 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST ......................... 33 FIGURE 6.14 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST.................... 34 FIGURE 7.1 – GL811S 48 PIN LQFP PACKAGE ................................................................ 35 FIGURE 7.2 – GL811S 64 PIN LQFP PACKAGE ................................................................ 36 ©2007 Genesys Logic Inc. - All rights reserved. Page 5 GL811S USB2.0 to ATA/ATAPI Bridge Controller LIST OF TABLES TABLE 3.1 - 48 PIN LIST ..................................................................................................... 11 TABLE 3.2 - 64 PIN LIST ..................................................................................................... 11 TABLE 3.3 – 48 PIN DESCRIPTIONS.................................................................................... 12 TABLE 3.4 - 64 PIN DESCRIPTIONS .................................................................................... 13 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 18 TABLE 6.2 - TEMPERATURE CONDITIONS ......................................................................... 18 TABLE 6.3 - I/O TYPE DIGITAL PINS .................................................................................. 18 TABLE 6.4 - D+/ D-............................................................................................................. 19 TABLE 6.5 - SWITCHING CHARACTERISTICS .................................................................... 19 TABLE 6.5 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ..................................... 27 TABLE 8.1 - ORDERING INFORMATION ............................................................................. 37 ©2007 Genesys Logic Inc. - All rights reserved. Page 6 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 1 GENERAL DESCRIPTION The GL811S is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811S can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811S controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811S can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811S uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (7mmX7mm) package, the GL811S is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM. ©2007 Genesys Logic Inc. - All rights reserved. Page 7 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 2 FEATURES · Complies with Universal Serial Bus specification rev. 2.0. · Complies with ATA/ATAPI-6 specification rev 1.0. · Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) · Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / 10.X. · Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). · Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). · 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. · Support 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66). · Embedded Turbo 8051. · ROM size: 12k words; RAM size: 1280 bytes. (Bulk Buffer: 512 words, MC RAM: 256 bytes) · Supports Power Down mode and USB suspend indicator. · Supports USB 2.0 TEST mode features. · Supports 4 GPIOs for programmable AP (48 pin package). · Supports 8 GPIOs for programmable AP (64 pin package). · Supports device power control for power on/off when running suspend mode. · Supports 32 bit and 48 bit LBA hard disk. · Provides LED indicator for Full Speed and High Speed (only for 64 pin package). · Using 12 MHz external clock to provide better EMI. · 3.3V I/Os (5V tolerant) 5V tolerance pad for IDE interface. · Operates at 5V voltage (built-in 5V to 3.3V & 3.3V to 1.8V regulator) · Supports Wakeup ability. · Available in 48-pin/64-pin LQFP package types. · Provides SPI interface (only for 64 pin package). · Provides UART interface (only for 64 pin package). ©2007 Genesys Logic Inc. - All rights reserved. Page 8 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 3 PIN ASSIGNMENT XI 12 DD7 25 TEST 11 DD8 26 CS1_ 10 DD6 27 D_PWR_CTL 9 DD9 28 5V_IN 8 DD5 29 3V3_OUT 7 DVDD1 30 CS0_ 6 DD10 31 DA2 5 DD4 32 DA0 4 DD11 33 DA1 3 PIO0 34 INTRQ 35 2 DD3 DD12 1 36 DMACK_ 3.1 Pinouts Figure 3.1 - 48 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 9 TEST NC DGND XI 34 33 3V3_OUT 40 35 CS0_ 41 CS1_ DA2 42 36 U_RX 43 37 U_TX 38 DA0 44 5V_IN DA1 45 D_PWR_CTL INTRQ 46 39 DMACK_ 48 47 GL811S USB2.0 to ATA/ATAPI Bridge Controller IORDY 49 32 XO NC 50 31 X_POWER DIOR_ 51 30 AVDD1 DIOW_ 52 29 RREF DMARQ 53 28 AGND1 DD15 54 27 DP DGND 55 26 DM DVDD 56 25 AVDD3 DD0 57 24 AGND DD14 58 23 DGND DD1 59 22 RESET# DD13 60 21 USB_PWR GL811S DD2 61 20 HD_RST# GPIO1 62 19 NC F_LED 63 18 NC H_LED 64 17 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DD12 DD3 PIO2 PIO0 PIO1 DD11 DD4 DD10 DVDD DGND DD5 DD9 DD6 DD8 DD7 NC LQFP - 64 Figure 3.2 - 64 Pin LQFP Pinout Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 10 GL811S USB2.0 to ATA/ATAPI Bridge Controller 3.2 Pin List Table 3.1 - 48 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 DD12 B 13 HD_RST# O 25 XI I 37 IORDY I 2 DD3 B 14 USB_PWR B 26 TEST I 38 DIOR_ O 3 PIO0 B 15 RESET# I 27 CS1_ O 39 DIOW_ O 4 DD11 B 16 AGND1 P 28 D_PWR_CTL B 40 DMARQ I 5 DD4 B 17 AVDD1 P 29 5V_IN P 41 DD15 B 6 DD10 B 18 DM B 30 3V3_OUT P 42 DVDD P 7 DVDD1 P 19 DP B 31 CS0_ O 43 DD0 B 8 DD5 B 20 AGND2 P 32 DA2 O 44 DD14 B 9 DD9 B 21 VREF A 33 DA0 O 45 DD1 B 10 DD6 B 22 AVCC2 P 34 DA1 O 46 DD13 B 11 DD8 B 23 X-POWER P 35 INTRQ I 47 DD2 B 12 DD7 B 24 B 36 DMACK_ O 48 GPIO1 B XO Table 3.2 - 64 Pin List Pin# Pin Name 1 DD12 Type Pin# B 17 Pin Name Type Pin# NC 33 Pin Name XI Type Pin# I Type 49 IORDY I 50 NC 51 DIOR_ O 2 DD3 B 18 NC 34 DGND 3 PIO2 B 19 NC 35 NC 4 PIO0 B 20 HD_RST# O 36 TEST I 52 DIOW_ O 5 PIO1 B 21 USB_PWR B 37 CS1_ O 53 DMARQ I 6 DD11 B 22 RESET# I 38 D_PWR_CTL B 54 DD15 B 7 DD4 B 23 DGND P 39 5V_IN P 55 DGND P 8 DD10 B 24 AGND P 40 DVDD P 56 DVDD P 9 DVDD P 25 AVDD3 P 41 CS0_ O 57 DD0 B 10 DGND P 26 DM B 42 DA2 O 58 DD14 B 11 DD5 B 27 DP B 43 U_RX B 59 DD1 B 12 DD9 B 28 AGND1 P 44 U_TX O 60 DD13 B 13 DD6 B 29 RREF A 45 DA0 O 61 DD2 B 14 DD8 B 30 AVDD1 P 46 DA1 O 62 GPIO 1 B ©2007 Genesys Logic Inc. - All rights reserved. P Pin Name Page 11 GL811S USB2.0 to ATA/ATAPI Bridge Controller 15 DD7 16 NC B 31 X_POWER P 47 INTRQ I 63 F_LED B 32 XO B 48 DMACK_ O 64 H_LED B 3.3 Pin Descriptions Table 3.3 – 48 Pin Descriptions USB Interface Pin Name Pin# Type VREF 21 A Reference Resistor DM 18 B HS D- DP 19 B HS D+ XO 24 B Crystal output XI 25 I Crystal input I (pu) I (pd) External reset RESET# 15 TEST 26 Description Test mode Input ATA/ATAPI Interface Pin Name Pin# Type 43,45,47, 2,5,8,10,1 2,11,9,6,4, 1,46,44, 41 B (pd) IDE Data Bus 13 O Device Reset 27,31 O Chip Select #1,#0 DA0~2 33,34,32 O IDE Address #2,#1,#0 INTRQ 35 I (pd) IDE interrupt input DMACK_ 36 O IDE Acknowledge IORDY 37 I (pu) DIOR_ 38 O IDE read signal DIOW_ 39 O IDE write signal DMARQ 40 I (pd) DD0~15 HD_RST# CS1_, CS0_ Description IDE Ready IDE request ©2007 Genesys Logic Inc. - All rights reserved. Page 12 GL811S USB2.0 to ATA/ATAPI Bridge Controller Miscellaneous Interface Pin Name Pin# GPIO 1 48 PIO0 3 Type B (pu) B (pd) Description GPIO GPIO Power / Ground Pin Name Pin# Type 29 P 5V input 7,23,30,42 P Digital VDD AGND1 16 P Analog GND AGND2 20 P Analog GND #1 AVCC1 17 P Analog VDD #3 AVCC2 22 P Analog VDD #1 5V_IN Description DVDD1,X-POW ER,3V3_OUT, DVDD2 Miscellaneous Pin Name Pin# USB_PWR 14 D_PWR_CTL 28 Type B (pu) B (pd) Description USB power detect HDD power control Table 3.4 - 64 Pin Descriptions USB Interface Pin Name Pin# Type Description RREF 29 A Reference Resistor DM 26 B HS D- DP 27 B HS D+ XO 32 B Crystal output XI 33 I Crystal input RESET# 22 External reset TEST 36 I (pu) I (pd) Test mode Input ©2007 Genesys Logic Inc. - All rights reserved. Page 13 GL811S USB2.0 to ATA/ATAPI Bridge Controller ATA/ATAPI Interface Pin Name Pin# Type 57,59,61, 2,7,11,13, 15,14,12, 8,6,1,60, 58,54 B (pd) IDE Data Bus 20 O Device Reset 37,41 O Chip Select #1,#0 DA0~2 45,46,42 O IDE Address #2,#1,#0 INTRQ 47 I (pd) IDE interrupt input DMACK_ 48 O IDE Acknowledge IORDY 49 I (pu) DIOR_ 51 O IDE read signal DIOW_ 52 O IDE write signal DMARQ 53 I (pd) DD0~15 HD_RST# CS1_, CS0_ Description IDE Ready IDE request Miscellaneous Interface Pin Name Pin# GOPI 1 62 PIO 0 4 PIO 1 5 PIO 2 3 U_RX 43 U_TX 44 Type B (pu) B (pd) B (pd) B (pd) B (pu) O Description General Purpose IO #1 Program IO #0 Program IO #1 becomes SPIDI when SPI interface is enabled (SPIDI : SPI Data Input) Program I/O #2 becomes SPIDO when SPI interface is enabled (SPIDO : SPI Data Output) UART RXD UART TXD Power / Ground Pin Name Pin# Type Description 5V_IN 39 P 5V input DGND 10,23,34,55 P Digital GND DVDD 9,31,40,56 P Digital VDD AGND 24 P Analog GND AGND1 28 P Analog GND #1 AVDD3 25 P Analog VDD #3 ©2007 Genesys Logic Inc. - All rights reserved. Page 14 GL811S USB2.0 to ATA/ATAPI Bridge Controller AVDD1 30 P Analog VDD #1 Miscellaneous Pin Name Pin# USB_PWR 21 F_LED 63 H_LED 64 D_PWR_CTL 38 Notation: Type O I B B/I B/O P A SO pu pd odpu Type B (pu) B (pu) B (pu) B (pd) Description USB power detect Operation mode indicator (Full-Speed) Operation mode indicator (High-Speed) HDD power control Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2007 Genesys Logic Inc. - All rights reserved. Page 15 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 4 BLOCK DIAGRAM GPIO Operation Register 8051 Core 2K ROM IDE Device IDE Interface Bulk FIFO SIE SPI Interface UTM SPI Device USB EP0, EP3 FIFO Figure 4.1 - Block Diagram ©2007 Genesys Logic Inc. - All rights reserved. Page 16 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 5 FUNCTION DESCRIPTION 5.1 UTM The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low level USB protocol and signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. 5.2 SIE The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions. 5.3 EP0/EP3 FIFO Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with 64-byte FIFO each, and it is used for endpoint 0/3 data transfer. 5.4 Bulk FIFO It is constructed in interleaved architecture and composed by two data buffers which is used to store data transferred between USB host and IDE device. 5.5 IDE Interface The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra DMA mode data transfers. 5.6 Operation Register It is a register space to store status information and to control the functions of GL811S by 8051. 5.7 SPI Interface The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with Motorola’s SPI specifications. ©2007 Genesys Logic Inc. - All rights reserved. Page 17 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Table 6.1 - Maximum Ratings Symbol Min. Max. Unit DC supply voltage +3.0 +3.6 V DC input voltage -0.3 VCC + 0.3 V VI/O DC input voltage range for I/O -0.3 VCC + 0.3 V VAI/O DC input voltage for USB D+/D- pins -0.3 VCC + 0.3 V VESD Static discharge voltage 4000 VCC VI TA Parameter Ambient Temperature V 0 o 100 C 6.2 Temperature Conditions Table 6.2 - Temperature Conditions Item Value o Storage Temperature -50 C ~ 150 oC Operating Temperature 0 oC ~ 70 oC 6.3 DC Characteristics 6.3.1 I/O Type digital pins Table 6.3 - I/O Type digital pins Parameter Min. Typ. Max. Unit Current sink @ VOL = 0.4V 10.58 14.21 16.87 mA Current output @ VOH = 2.4V (TTL high) 14.74 27.46 43.0 mA Falling slew rate at 30 pF loading capacitance 0.56 0.91 1.28 V/ns Rising slew rate at 30 pF loading capacitance 0.58 0.91 1.72 V/ns Schmitt trigger low to high threshold point 1.4 1.5 1.6 V Schmitt trigger low to high threshold point 1.4 1.5 1.6 V Pad internal pull up resister 37.87K 64.7K 108.11K Ohms Pad internal pull down resister 29.85K 59.45K 134.26K Ohms ©2007 Genesys Logic Inc. - All rights reserved. Page 18 GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.3.2 D+/ DTable 6.4 - D+/ DParameter Min. Typ. Max. Unit D+/D- static output LOW (RL of 1.5K to VCC ) 0 0.3 V D+/D- static output HIGH (RL of 15K to GND ) 2.8 3.6 V Differential input sensitivity 0.2 Single-ended receiver threshold 0.8 V Transceiver capacitance 2.0 V 20 pF Hi-Z state data line leakage -10 +10 µA Driver output resistance 28 43 Ohms 6.3.3 Switching Characteristics Table 6.5 - Switching Characteristics Parameter X1 crystal frequency Min. Typ. Max. Unit 11.97 12 12.03 MHz X1 cycle time 83.3 ns D+/D- rise time with 50pF loading 4 20 ns D+/D- fall time with 50pF loading 4 20 ns 6.4 AC Characteristics- ATA/ ATAPI The GL811S complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) Following listed the symbols and their respective definitions that are used in the timing diagram: ©2007 Genesys Logic Inc. - All rights reserved. Page 19 GL811S USB2.0 to ATA/ATAPI Bridge Controller - Signal transition (asserted or negated) - Data transition (asserted or negated) - Data valid - Undefined but not necessarily released - Asserted, negated or released - Released - The “other” condition if a signal is shown with no change All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal. ©2007 Genesys Logic Inc. - All rights reserved. Page 20 GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.1 Register Transfers / PIO Data Transfers Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following: 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer. ©2007 Genesys Logic Inc. - All rights reserved. Page 21 GL811S USB2.0 to ATA/ATAPI Bridge Controller ©2007 Genesys Logic Inc. - All rights reserved. Page 22 GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.2 Multiword DMA data transfer ©2007 Genesys Logic Inc. - All rights reserved. Page 23 GL811S USB2.0 to ATA/ATAPI Bridge Controller Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. Figure 6.1 - Initiating a Multiword DMA Data Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 24 GL811S USB2.0 to ATA/ATAPI Bridge Controller Figure 6.2 - Sustaining a Multiword DMA Data Burst Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. Figure 6.3 - Device Terminating a Multiword DMA Data Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 25 GL811S USB2.0 to ATA/ATAPI Bridge Controller Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst. 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated. Figure 6.4 - Host terminating a Multiword DMA Data Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 26 GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.3 Ultra DMA data transfer Table 6.5 - Ultra DMA data burst timing requirements Name Mode 0 (in ns) min max Mode 1 (in ns) min max Mode 2 (in ns) min max Mode 3 (in ns) min max Mode 4 (in ns) Min t2CYCTYP 240 160 120 90 60 tCYC 112 73 54 39 25 t2CYC 230 154 115 86 57 tDS 15 10 7 7 5 tDH 5 5 5 5 5 Comment max Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations Data setup time at recipient Data hold time at recipient Data valid setup time at sender Data valid hold time at sender tDVS 70 48 30 20 6 tDVH 6 6 6 6 6 tFS 0 230 0 200 0 170 0 130 0 120 First STORBE time tLI 0 150 0 150 0 150 0 100 0 100 Limited interlock time tMLI 20 20 20 20 20 Interlock time with minimum tUI 0 0 0 0 0 Unlimited interlock time tAZ 10 10 10 10 10 tZAH 20 20 20 20 20 tZAD 0 0 0 0 0 tENV 20 70 20 70 20 70 20 55 20 Drivers to assert or negate 55 tSR 50 30 20 NA NA tRFS 75 70 60 60 60 tRP 160 tIORDYZ 125 20 100 20 100 20 100 20 20 tZIORDY 0 0 0 0 0 tACK 20 20 20 20 20 tSS 50 50 50 50 50 ©2007 Genesys Logic Inc. - All rights reserved. Maximum time allowed for output drivers to release Minimum delay time required for output Envelope time STROBE to DMARDY_ time Ready to final STROBE time Minimum time to assert STOP or negate DMARQ Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to negation of DMARQ or assertion of STOP Page 27 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted. Figure 6.5 - Initiating an Ultra DMA Data-In Burst Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 6.6 - Sustained Ultra DMA Data-In Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 28 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated. 2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device. Figure 6.7 - Host Pausing an Ultra DMA Data-In Burst Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.8 - Device Terminating an Ultra DMA Data-In Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 29 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.9 - Host Terminating an Ultra DMA Data-In Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 30 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6.10 - Initiating an Ultra DMA Data-Out Burst Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. Figure 6.11 - Sustained Ultra DMA Data-Out Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 31 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host. Figure 6.12 - Device Pausing an Ultra DMA Data-Out Burst ©2007 Genesys Logic Inc. - All rights reserved. Page 32 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.13 - Host terminating an Ultra DMA data-out burst ©2007 Genesys Logic Inc. - All rights reserved. Page 33 GL811S USB2.0 to ATA/ATAPI Bridge Controller Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.14 - Device Terminating an Ultra DMA Data-Out Burst 6.5 AC Characteristics - USB 2.0 The GL811S conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. ©2007 Genesys Logic Inc. - All rights reserved. Page 34 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 7 PACKAGE DIMENSION D D1 A D2 A2 25 36 37 24 N : Normal package G : Green package GL811S B AAAAAAAGAA YWWXXXXXXXX E2 E E1 A Date Code Version No. Lot Code 48 13 12 4X 1 e 0- 1 4X b C ccc C 0- 2 R1 R2 GAGE PLANE 0.25mm L 0- 3 NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. c ddd M C A B s D s 0- S aaa C A B D bbb H A B D L1 Internal No. H A1 0.05 S D SEATING PLANE CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 A2 1.40 1.45 0.053 0.055 0.057 9.00 BASIC 0.354 BASIC D E 9.00 BASIC 0.354 BASIC 0.276 BASIC D1 7.00 BASIC E1 7.00 BASIC 0.276 BASIC 5.50 BASIC D2 0.217 BASIC E2 5.50 BASIC 0.217 BASIC R1 0.08 0.003 0.08 0.20 0.003 0.008 R2 00° 3.5° 7° 0° 3.5° 7° 0- 1 0° 0° 0- 2 11° 12° 13° 11° 12° 13° 0- 3 11° 12° 13° 11° 12° 13° 0.09 0.20 0.004 0.008 c L 0.45 0.60 0.75 0.018 0.024 0.030 1.00 REF 0.039 REF L1 0.20 0.008 S 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION 0.008 aaa 0.20 0.20 0.008 bbb 0.003 ccc 0.08 0.08 0.003 ddd Figure 7.1 – GL811S 48 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 35 GL811S USB2.0 to ATA/ATAPI Bridge Controller D D1 A A2 D 48 33 49 N : Normal package G : Green package B GL811S AAAAAAAGAA YWWXXXXXXXX Date Code Version No. Lot Code 17 64 16 4X 1 4X e 0- 1 b aaa C A B D bbb H A B D L1 E2 E E1 32 InternalNo . A A1 0.05 S D2 c ddd M C A B s D s 0- C SEATING PLANE ccc C 0- 2 R1 R2 H GAGE PLANE 0.25mm S L 0- 3 NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION b DOES NOT INCLUDE DAMBAR 2. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 12.00 BASIC 0.472 BASIC D 12.00 BASIC 0.472 BASIC E 10.00 BASIC 0.393 BASIC D1 10.00 BASIC 0.393 BASIC E1 7.50 BASIC D2 0.295 BASIC 7.50 BASIC 0.295 BASIC E2 0.08 0.003 R1 0.08 0.20 0.003 0.008 R2 00 3.5 7 0 3.5 7 0 0 0- 1 0- 2 11 12 13 11 12 13 0- 3 11 12 13 11 12 13 0.008 c 0.09 0.20 0.004 0.45 0.60 0.75 0.018 0.024 0.030 L 1.00 REF 0.039 REF L1 0.008 0.20 S 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION 0.20 0.008 aaa 0.20 0.008 bbb 0.08 0.003 ccc 0.08 0.003 ddd Figure 7.2 – GL811S 64 Pin LQFP Package ©2007 Genesys Logic Inc. - All rights reserved. Page 36 GL811S USB2.0 to ATA/ATAPI Bridge Controller CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number Package Green Version Status GL811S-MNGXX 48-pin LQFP Green Package XX Available GL811S-MSGXX 64-pin LQFP Green Package XX Available ©2007 Genesys Logic Inc. - All rights reserved. Page 37