CD4049UB, CD4050B Semiconductor August 1998 [ /Title (CD40 49UB, CD405 0B) /Subject (CMO S Hex Buffer/ Converters) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS CMOS Hex Buffer/Converters Features The Harris CD4049UB and CD4050B are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.) • CD4049UB Inverting The CD4049UB and CD4050B are designated as replacements for CD4009UB and CD4010B, respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink-current or voltage conversion, the CD4069UB Hex Inverter is recommended. File Number 926.2 • CD4050B Non-Inverting • High Sink Current for Driving 2 TTL Loads • High-To-Low Level Logic Conversion • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC • 5V, 10V and 15V Parametric Ratings Applications • CMOS to DTL/TTL Hex Converter • CMOS Current “Sink” or “Source” Driver • CMOS High-To-Low Logic Level Converter Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CD4049UBE -55 to 125 16 Ld PDIP E16.3 CD4050BE -55 to 125 16 Ld PDIP E16.3 CD4049UBF -55 to 125 16 Ld CERDIP F16.3 CD4050BF -55 to 125 16 Ld CERDIP F16.3 CD4050BM -55 to 125 16 Ld SOIC M16.3 NOTE: Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinouts CD4049UB (PDIP, CERDIP) TOP VIEW 16 NC VCC 1 15 L = F G=A 2 14 F A 3 13 NC H=B 4 B 5 12 K = E 11 E I=C 6 10 J = D C 7 9 D VSS 8 1 CD4050B (PDIP, CERDIP, SOIC) TOP VIEW VCC 1 G=A 2 A 3 H=B 4 B 5 I=C 6 C 7 VSS 8 16 NC 15 L = F 14 F 13 NC 12 K = E 11 E 10 J = D 9 D CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 CD4049UB, CD4050B Functional Block Diagrams CD4049UB A B C D E F 3 2 5 4 7 6 9 10 11 12 14 15 VCC VSS CD4050B G=A A H=B B I=C C J=D D K=E E L=F F 1 3 2 5 4 7 6 9 10 11 12 14 15 VCC 8 VSS NC = 13 NC = 16 G=A H=B I=C J=D K=E L=F 1 8 NC = 13 NC = 16 Schematic Diagrams VCC VCC P OUT R IN P P N N R IN N VSS FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 IDENTICAL UNITS 2 OUT VSS FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6 IDENTICAL UNITS CD4049UB, CD4050B Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package. . . . . . . . . . . . . . . . . 130 55 SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications LIMITS AT INDICATED TEMPERATURE (oC) TEST CONDITIONS PARAMETER Quiescent Device Current IDD (Max) Output Low (Sink) Current IOL (Min) Output High (Source) Current IOH (Min) Out Voltage Low Level VOL (Max) Output Voltage High Level VOH (Min) Input Low Voltage, VIL (Max) CD4049UB Input Low Voltage, VIL (Max) CD4050B Input High Voltage, VIH Min CD4049UB 3 25 VO (V) VIN (V) VCC (V) -55 -40 85 125 MIN TYP MAX UNITS - 0,5 5 1 1 30 30 - 0.02 1 µA - 0,10 10 2 2 60 60 - 0.02 2 µA - 0,15 15 4 4 120 120 - 0.02 4 µA - 0,20 20 20 20 600 600 - 0.04 20 µA 0.4 0,5 4.5 3.3 3.1 2.1 1.8 2.6 5.2 - mA 0.4 0,5 5 4 3.8 2.9 2.4 3.2 6.4 - mA 0.5 0,10 10 10 9.6 6.6 5.6 8 16 - mA 1.5 0,15 15 26 25 20 18 24 48 - mA 4.6 0,5 5 -0.81 -0.73 -0.58 -0.48 -0.65 -1.2 - mA 2.5 0,5 5 -2.6 -2.4 -1.9 -1.55 -2.1 -3.9 - mA 9.5 0,10 10 -2.0 -1.8 -1.35 -1.18 -1.65 -3.0 - mA 13.5 0,15 15 -5.2 -4.8 -3.5 -3.1 -4.3 -8.0 - mA - 0,5 5 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,10 10 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,15 5 0.05 0.05 0.05 0.05 - 0 0.05 V - 0,5 5 4.95 4.95 4.95 4.95 4.95 5 - V - 0,10 10 9.95 9.95 9.95 9.95 9.95 10 - V - 0,15 15 14.95 14.95 14.95 14.95 14.95 15 - V 4.5 - 5 1 1 1 1 - - 1 V 9 - 10 2 2 2 2 - - 2 V 13.5 - 15 2.5 2.5 2.5 2.5 - - 2.5 V 0.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V 1 - 10 3 3 3 3 - - 3 V 1.5 - 15 4 4 4 4 - - 4 V 0.5 - 5 4 4 4 4 4 - - V 1 - 10 8 8 8 8 8 - - V 1.5 - 15 12.5 12.5 12.5 12.5 12.5 - - V CD4049UB, CD4050B DC Electrical Specifications (Continued) LIMITS AT INDICATED TEMPERATURE (oC) 25 TEST CONDITIONS PARAMETER Input High Voltage, VIH Min CD4050B Input Current, IIN Max VO (V) VIN (V) VCC (V) -55 -40 85 125 MIN TYP MAX UNITS 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V 9 - 10 7 7 7 7 7 - - V 13.5 - 15 11 11 11 11 11 - - V - ±10-5 ±0.1 µA - AC Electrical Specifications 0,18 18 ±0.1 ±0.1 ±1 ±1 TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS LIMITS (ALL PACKAGES) VIN VCC TYP MAX UNITS 5 5 60 120 ns 10 10 32 65 ns 10 5 45 90 ns 15 15 25 50 ns 15 5 45 90 ns 5 5 70 140 ns 10 10 40 80 ns 10 5 45 90 ns 15 15 30 60 ns 15 5 40 80 ns 5 5 32 65 ns 10 10 20 40 ns 10 5 15 30 ns 15 15 15 30 ns 15 5 10 20 ns 5 5 55 110 ns 10 10 22 55 ns 10 5 50 100 ns 15 15 15 30 ns 15 5 50 100 ns 5 5 80 160 ns 10 10 40 80 ns 15 15 30 60 ns 5 5 30 60 ns 10 10 20 40 ns 15 15 15 30 ns Input Capacitance, CIN CD4049UB - - 15 22.5 pF Input Capacitance, CIN CD4050B - - 5 7.5 pF PARAMETER Propagation Delay Time Low to High, tPLH CD4049UB Propagation Delay Time Low to High, tPLH CD4050B Propagation Delay Time High to Low, tPHL CD4049UB Propagation Delay Time High to Low, tPHL CD4050B Transition Time, Low to High, tTLH Transition Time, High to Low, tTHL 4 CD4049UB, CD4050B TA = 25oC TA = 25oC SUPPLY VOLTAGE (VCC) = 5V SUPPLY VOLTAGE (VCC) = 5V VO , OUTPUT VOLTAGE (V) VO , OUTPUT VOLTAGE (V) Typical Performance Curves 5 4 MINIMUM MAXIMUM 3 2 5 MINIMUM 4 MAXIMUM 3 2 1 1 0 1 2 3 0 4 1 2 VI , INPUT VOLTAGE (V) 3 4 FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4049UB FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4050B IOL, OUTPUT LOW (SINK) CURRENT (mA) IOL, OUTPUT LOW (SINK) CURRENT (mA) VI , INPUT VOLTAGE (V) TA = 25oC 70 15V 10V 50 40 30 GATE TO SOURCE VOLTAGE (VGS) = 5V 20 10 1 2 3 4 5 6 7 50 40 30 20 GATE TO SOURCE VOLTAGE (VGS) = 5V 10 0 8 1 FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -6 -5 -4 -3 -2 -1 3 4 5 6 7 8 FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS VDS, DRAIN TO SOURCE VOLTAGE (V) -7 2 VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) -8 10V VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 0 -1 0 TA = 25oC TA = 25oC -10 GATE TO SOURCE VOLTAGE VGS = -5V -15 -20 -25 -10V -30 -15V -5 OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 -35 FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 5 GATE TO SOURCE VOLTAGE VGS = -5V -10V -10 -15 -20 -15V -25 -30 OUTPUT HIGH (SOURCE) 0 15V 60 -35 FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS CURRENT CHARACTERISTICS 60 TA = 25oC 70 CD4049UB, CD4050B Typical Performance Curves (Continued) 10 9 VO, OUTPUT VOLTAGE (V) VO, OUTPUT VOLTAGE (V) 10 SUPPLY VOLTAGE 8 VCC = 10V 125oC 7 6 TA = -55oC VCC = 5V 5 4 -55oC 3 125oC 2 SUPPLY VOLTAGE 125oC 8 VCC = 10V 7 6 VCC = 5V 5 TA = -55oC 4 3 125oC 2 -55oC 1 1 0 0 0 1 2 3 4 0 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) 105 TA = 25oC V C 104 Y PL GE TA L VO 5 =1 VC V 10 V 10 5V P SU 103 LOAD CAPACITANCE CL = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + 4pF EXT) 102 10 10 102 103 104 f, INPUT FREQUENCY (kHz) 105 POWER DISSIPATION PER INVERTER (µW) FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS 106 1 2 3 4 TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 1 10 102 108 FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4049UB 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) 108 FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTERFOR CD4050B 6 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4050B POWER DISSIPATION PER INVERTER (µW) FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4049UB POWER DISSIPATION PER INVERTER (µW) 9 CD4049UB, CD4050B Test Circuits VCC VCC VCC INPUTS INPUTS OUTPUTS VIH VSS + DVM VIL IDD VSS VSS NOTE: Test any one input with other inputs at VCC or VSS. FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT FIGURE 14. INPUT VOLTAGE TEST CIRCUIT CMOS 10V LEVEL TO DTL/TTL 5V LEVEL VCC = 5V VCC INPUTS COS/MOS IN OUTPUTS VCC OUTPUT TO DTL/TTL CD4049 INPUTS I 5V = VOH 10V = VIH 0 = VIL VSS VSS 0 = VOL In Terminal - 3, 5, 7, 9, 11, or 14 Out Terminal - 2, 4, 6, 10, 12 or 15 VCC Terminal - 1 VSS Terminal - 8 NOTE: Measure inputs sequentially, to both VCC and VSS connect all unused inputs to either VCC or VSS. FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION FIGURE 15. INPUT CURRENT TEST CIRCUIT VDD 0.1µF CL 10kHz, 100kHz, 1MHz I 1 2 3 4 5 6 7 8 CD4049UB 500µF 16 15 14 13 12 11 10 9 CL INCLUDES FIXTURE CAPACITANCE FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS 7 VSS CD4049UB, CD4050B Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 18.66 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 8 MILLIMETERS 0.204 0.355 - 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 16 6 7 4 9 Rev. 0 12/93 CD4049UB, CD4050B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) LEAD FINISH c1 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 9 NOTES - b2 b MAX 0.014 α A A MIN b A L MAX A Q SEATING PLANE MILLIMETERS MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 16 16 8 Rev. 0 4/94 CD4049UB, CD4050B Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 10 SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e α MILLIMETERS 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93