P1/12 HIGH-VOLTAGE MONOLITHIC IC ECN2102/2112 ECN2102 / 2112 is a single chip row driver IC for electroluminescent (EL) display panel. Functions * Low-voltage serial to high-voltage parallel converter * 34 outputs of totem pole type Features * Output terminal voltage up to 250V * Source / Sink current 500mA ECN2102 ECN2112 Fig. 1. OUTLINE OF FP-48 PACKAGE Vcc STB Vcc OE D R1 Q1 34 bit static shift register R2 Q2 CLK Q34 R34 D-FF SO Function Block Diagram (Positive Logic) PDE-2102/12-0.1 P2/12 ECN2102/2112 1. GENERAL (1) TYPE ECN2102/ECN2112 (2) APPLICATION Row line driver for Electroluminecent (EL) (3) STRUCTURE Monolithic IC, processed Dielectric Isolation. (4) PACKAGE FP-48 (Fig.1) 2. MAXIMUM ALLOWABLE RATING No ITEMS display panel (Ta=25°C) SYMBOLS RATINGS UNITS CONDITIONS 1 Supply Voltage (logic) Vcc -0.5 ~ +7.0 V to GND terminal 2 Input Voltage Vin -0.5 ~ Vcc+0.5 V to GND terminal 3 Vs - GND Voltage VSG Vcc V to GND terminal 4 Output Terminal Voltage VQ ±250 V Between Vs,Vcc,GND, (logic) Input and Q output 5 Allowable Power Dissipation PT 800 mW 6 Operating Temperature TOP -40 ~ +85 °C 7 Storage Temperature Tstg -55 ~ +150 °C 3. RECOMMENDED OPERATING CONDITIONS No ITEMS SYMBOLS Min. Typ. Max. UNITS CONDITIONS 1 Supply Voltage (logic) Vcc 5.0 5.5 6.0 V 2 Clock Frequency fCLK - - 250 kHz 3 Clock Pulse Width twCLK 80 - - ns 4 Data Setup Time tsu 80 - - ns 5 Data Hold Time th 80 - - ns 6 Output Terminal Voltage VQ - ±230 - V 7 Peak Output Source Current HIOH - - -500 mA Note 1 8 Peak Output Sink Current HIOL - - +500 mA Note 1 Vcc= 5.5V Vin= 0V/5.5V Vcc= 5.5V Note1 : Conduction period £ 5 ms per 1 IC PDE-2102/12-0.1 P3/12 ECN2102/2112 4. ELECTRICAL CHARACTERISTICS No ITEMS 1 2 3 4 5 Output Voltage (logic) Output Current (logic) Input Voltage Input Current (logic) (logic) Dissipation Current(logic) (Unless otherwise specified, Ta= 25°C, Vcc= 5.5V, HVCC=230V) SYMBOLS Min. Typ. VOL - - 0.1 V IOL= 20mA VOH 5.4 - - V IOH=-20mA IOL 1.0 - - mA VOL= 0.8V IOH -1.0 - - mA VOLH 4.7V VIL - - 1.0 V VIH 3.5 - - V VTHL - - 0.4 V VTLH 4.5 - - V IIH - - 10 mA Vin=5.5V all input/1 input IIL - - -10 mA Vin=0V D,CLK/1 input - - -100 mA Vin=0V STB/1 input - - 10 mA No signal all input 5.5V, Istb Max. UNITS C O N D I T I O N S D input CLK,STB input all output Off 6 Output Voltage - - 25 mA No signal, 1ch source output On - - 5 mA No signal, 1ch sink output On - - 3.0 V HIOL=1mA Q out-GND - - 6.0 V HIOL=200mA Q out-GND - - 4.0 V HIOH=-1mA Vs-Q out - - 8.0 V HIOH=-200mA Vs-Q out dv/dt1 200 - - V/ms Vs~Q out,+dv/dt apply.Fig.6 dv/dt2 200 - - V/ms Q out~GND,-dv/dt apply.Fig.7 toff - - 6.0 ms Source side - - 7.0 ms Sink side HVOL HVOH 7 8 Output SCR dv/dt capability Output SCR Off Period Fig.8 5. SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta= 25°C, Vcc= 5.5V, Fig.5) No ITEMS 1 2 Output Delay Time (logic) Output Delay Time SYMBOLS Min. Typ. Max. UNITS C O N D I T I O N S tPLH - - 300 ns tPHL - - 300 ns tQLH - - 3 ms RLQ=1kW tQHL - - 3 ms CLQ=2000pF CL=15pF PDE-2102/12-0.1 P4/12 ECN2102/2112 Vcc (*) : Q outputs are "OFF" at "H" level. STB Vcc (*) OE R1 Q1 34 bit static shift register R2 Q2 D CLK Q34 R34 SO D-FF Fig. 2. Function Block Diagram (Positive Logic) 6. FUNCTION TABLE CONTROL INPUT SHIFT OPERATION OUTPUT SHIFT REGISTER CLK D OE(*4) STB Rn - * H * shift no- * H * keep H H L * H OPERATION * H SO(*1) L L H OUTPUT * Q H (*2) R34 OFF H L (*3) L OFF * ALL OFF (*1) 34th data is pushed out as output at the state of down edge¯ of clock signal. (*2) When shift register is "H", source SCR of Q output is driven to ON. (*3) When shift register is "H", sink SCR of Q output is driven to ON. (*4) OE must be kept "H". PDE-2102/12-0.1 P5/12 ECN2102/2112 7. INPUT / OUTPUT CIRCUIT Equivalent of each input Typical of serial output Pull up Vcc Vcc Typical of all Q output Vcc Vs source SCR () Input Output Q output sink SCR GND GND GND Fig. 3. Input / Output Circuit PDE-2102/12-0.1 P6/12 ECN2102/2112 8. EXAMPLE OF OPERATING TIMING CHART D ECN2102 CLK ECN2112 CLK H fix. OE STB +HV Vs GND -HV ( means floating condition.) ECN2102 Qn ECN2112 Qn ECN2102 Qn+1 ECN2112 Qn+1 HV : High Voltage Fig. 4. Example of Operating Timing Chart PDE-2102/12-0.1 P7/12 ECN2102/2112 9. MEASUREMENT AND MEASUREMENT CIRCUIT 1/f CLK t WCLK CLK Tn : Figure n means n th pulse T1 T2 T34 50% 50% 50% INPUT CONDITION t ILH, t IHL =10ns typ. tsu th t ILH 50% D t PLH SO t PHL 50% 50% t IHL 5.5V 90% 0V 10% (a) Shift function (SW1®OFF, SW2,3®ON) SW1 OFF ON OFF OFF SW2 ON ON OFF OFF ON OFF D 50% CLK OE 50% H fix. 50% STB 50% t QHL t QLH 90% Q1 t QLH t QHL 10% 90% Q2 10% Other Q output (b) Output Function (SW3®OFF) 250V SW1 5.5V Vcc CLK Vs Q1 D RLQ CLQ Q2 OE STB RLQ=1kW CLQ=2000pF CL=15pF Q34 GND SO SW3 CL SW2 Measurement point Fig. 5. Switching Characteristics Measurement Circuit PDE-2102/12-0.1 P8/12 ECN2102/2112 1000pF 5.5V Vcc CLK 1kW Vs Q1 D +dV/dt pulser (to reach 150V) Q2 OE STB Q34 GND SO Fig. 6. Output SCR dV/dt capability (dV/dt1) Measurement Circuit 5.5V Vcc CLK Vs D Q1 Q2 OE Q34 STB GND SO 1000pF -dV/dt pulser (to reach -150V) 1kW Fig. 7. Output SCR dV/dt capability (dV/dt2) Measurement Circuit PDE-2102/12-0.1 P9/12 ECN2102/2112 Io ¬ 5.5V Vcc CLK Vs D Qn OE STB GND 1 2 SO 34 CLK D OE STB H fix. H fix. dV/dt @ 100V/ms MIN 150V Vs 100mA Io SCR OFF SCR ON by mistake tOFF (a) Source SCR 5.5V Vcc CLK Vs D Io Qn ¬ OE STB GND 1 2 SO 34 CLK D OE STB H fix. L fix. MIN 150V dV/dt@100V/ms Vs Io 100mA tOFF SCR OFF SCR ON by mistake (b) Sink SCR Fig. 8. Output SCR tOFF Measurement PDE-2102/12-0.1 P10/12 ECN2102/2112 10. PIN LOCATION Q34 Q1 Q33 Q2 Q32 Q3 Q31 Q4 Q30 Q5 Q29 Q6 Q28 Q7 Q27 Q8 Q26 Q9 Q25 Q10 Q24 Q11 Q23 Q12 Q22 Q13 Q21 Q14 Q20 Q15 Q19 Q16 Q18 Q17 Vs Vs GND GND Vcc (NC) (NC) OE STB (NC) (NC) CLK SO D (a) ECN2102 Q1 Q34 Q2 Q33 Q3 Q32 Q4 Q31 Q5 Q30 Q6 Q29 Q7 Q28 Q8 Q27 Q9 Q26 Q10 Q25 Q11 Q24 Q12 Q23 Q13 Q22 Q14 Q21 Q15 Q20 Q16 Q19 Q17 Q18 Vs Vs GND GND (NC) Vcc OE (NC) (NC) STB CLK (NC) D SO (b) ECN2112 Fig. 9. Pin Location (Top view) PDE-2102/12-0.1 P11/12 ECN2102/2112 11. PACKAGE OUTLINE (1) ECN2102 (Unit : mm) 18.8±0.4 NOTE 2 3.05 MAX. 14.0 ±0.2 0.35±0.1 NOTE 1 20.0 TYP. 9.2±0.3 NOTE 3 NOTE 1 0.8±0.15 0.15±0.05 1.25 TYP. 9.2±0.3 NOTE 1 SURFACE 2.40 TYP. NOTE 5 0 - 10° 1.20±0.20 Notes. 1. THIS DIMENSION IS MEASURED AT ROOT OF LEAD. SPACING AT TIP OF LEAD IS MIN 0.2. 2. THIS DIMENSION INCLUDES A WARPAGE OF PACKAGE. 3. MARKING IS ON THE SURFACE OF PACKAGE, INCLUDING HITACHI MARK, TYPE NAME, LOT NUMBER, AND JAPAN MARK. 4. LEADS ARE SOLDER PLATED. 5. THIS IS THE BENDING ANGLE WITH HORIZONTAL PLANE. Fig. 10. Package outline (ECN2102) PDE-2102/12-0.1 P12/12 ECN2102/2112 (Unit : mm) (2) ECN2112 18.8±0.4 NOTE 2 3.05 MAX. 14.0 ±0.2 0.35±0.1 NOTE 1 20.0 TYP. 9.2±0.3 NOTE 3 NOTE 1 1.25 TYP. 0.8±0.15 9.2±0.3 NOTE 1 SURFACE 2.40 TYP. NOTE 5 0.15±0.05 0 - 10° 1.20±0.20 Notes. 1. THIS DIMENSION IS MEASURED AT ROOT OF LEAD. SPACING AT TIP OF LEAD IS MIN 0.2. 2. THIS DIMENSION INCLUDES A WARPAGE OF PACKAGE. 3. MARKING IS ON THE SURFACE OF PACKAGE, INCLUDING HITACHI MARK, TYPE NAME, LOT NUMBER, AND JAPAN MARK. 4. LEADS ARE SOLDER PLATED. 5. THIS IS THE BENDING ANGLE WITH HORIZONTAL PLANE. Fig. 11. Package outline (ECN2112) PDE-2102/12-0.1 HITACHI POWER SEMICONDUCTORS Notices 1.The information given herein, including the specifications and dimensions, is subject to change without prior notice to improve product characteristics. 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