R I Q U I N T S E M I C O N D U C T O R, I N C . The TQ8103 is a monolithic clock and data recovery (CDR) IC that receives NRZ data, extracts the high-speed clock, and presents the separated data and clock as its outputs. This device is designed specifically for SONET OC-12 and SDH STM-4 applications at 622 Mb/s. Its on-chip phase-locked loop (PLL) generates a stable 622.08 Mb/s reference based upon an external 38.88 MHz TTL reference. The PLL is based on a VCO constructed from integrated reactive components, which form a low-jitter, high-Q differential tank circuit. Both frequency- and phase-detect circuits reliably acquire and hold lock in worst-case SONET jitter conditions and scrambling patterns. The lock-detect circuitry signals when the CDR acquires frequency lock. • Switch and cross-connect line cards • ATM physical layer interfaces • Add/drop multiplexers • Provides complete high-speed OC-12/STM-4 solution when used with TQ8101 or TQ8105 Mux/Demux/Framer/PLL Figure 1. Typical Application 10KΩ • External loop filter requires simple passive network SELCK XTCKI LOCK SEL ECL data in (single-ended) • Single-chip CDR circuit for 622 Mb/s data • Clock and data outputs are differential ECL • Test equipment 50Ω Features • Single-ended ECL input has loopthrough path for external 50 ohm termination to minimize stubs and reflections • Transmission system transport cards VTT 622 Mb/s Clock & Data Recovery • Exceeds Bellcore and ITU jitter tolerance maps Typical SONET/SDH system applications for the TQ8103 include: 1000 pF TQ8103 TELECOM PRODUCTS T • Maintains clock in absence of data SINO DOUTP SINI DOUTN • 28-pin leaded chip carrier 50Ω • Can be used with a high-speed external clock VREF VTT 38.88-MHz TTL clock oscillator CKOUTP CKREF CKOUTN V CTL OUCHP 20KΩ 50Ω 62Ω VTT 1 mF 1000 pF For additional information and latest specifications, see our website: www.triquint.com 1 TQ8103 Figure 2. TQ8103 Block Diagram SELCK XTCKI SEL SINO +16 SINI DOUTP D Q DOUTN Loc k Detect VDD LOCK Phase Detect VREF CKOUTP VEE CKREF Mux Charge Pump VCO CKOUTN Frequency Detect V CTL OUCHP Functional Description The TQ8103 CDR integrates separate detectors for acquiring frequency lock and maintaining precise phase lock. When the CDR is locked onto an incoming NRZ data stream, its phase-detect circuitry compares the phase of the incoming NRZ data and the phase of the generated 622.08 MHz clock. When they differ, the resulting error signal nulls the phase difference and puts the generated 622.08 MHz clock back in phase with the incoming data. In this mode, the LOCK output is high. The phase-detect circuit operates only when the incoming NRZ data transitions between states. SONET and SDH employ scrambling, which provides an average transition density of 50 percent; however, some data patterns can generate legitimate scrambled signals with a significant number of consecutive ones or zeros. The TQ8103 maintains lock over bit sequences of over 100 consecutive zeros or ones. When the input data is lost or too many bit times occur without a transition, the PLL (which generates the 622.08 MHz clock) eventually drifts. The lock-detect circuit constantly compares the generated 622.08 MHz clock (divided by 16) and the external 38.88 MHz 2 reference. When the PLL drifts more than 2000 PPM from the reference, the LOCK output goes low. The SEL input selects between the phase-detect and frequency-detect circuits. When the PLL drifts out of lock, taking SEL low reverses the drift by switching in the frequency-detect circuit. Connecting the LOCK output directly to the SEL input should ensure that frequency lock is maintained in the absence of data. It is recommended, however, that a low-pass filter be added between LOCK and SEL to allow for orderly transitions between these circuits. Once the PLL frequency is within 500 PPM of the reference, the LOCK output returns high. As the SEL input goes high, the phase-detect circuit again maintains lock to the incoming NRZ data. The TQ8103 can also be used as a standalone 622.08 MHz frequency reference. When SEL is held low, the PLL utilizes only the frequency-detect circuit. The PLL locks onto the external 38.88 MHz reference to generate the desired 622.08 MHz output. For additional information and latest specifications, see our website: www.triquint.com TQ8103 Application Information Figure 3. External Loop Filter The TQ8103 requires an external loop filter. Care should be taken in the implementation of the filter. Good highfrequency design techniques should be used, with the loop filter being connected into the analog ground. The analog supply should be well filtered. 20 KΩ 62 Ω TELECOM PRODUCTS Loop Filter Design OUCHP VCTL Data Input Considerations 1 mF 1000 pF The serial data input line is a high-frequency ECL signal, and should be kept in a 50 ohm controlled impedance environment. Reflections on the serial input are minimized through the use of a separate loopback termination pin, SINO. A 50 ohm chip resistor between SINO and VTT minimizes stub length for the best signal quality. Another physical design consideration is to place the TQ8103 and its companion high-speed ICs as close as possible to the optics while observing good analog design practice on supply filtering and grounding. External Frequency Reference The externally supplied 38.88 MHz CKREF input needs to have low jitter with fast rise and fall times. Typical applications will use a telecom crystal oscillator such as the Connor-Winfield S14R6-38.88. SONET requires frequency sources to be accurate to ±20␣ ppm over temperature, voltage, and aging. The CKREF input is a reference frequency for initial frequency lock and for the lock-detect circuit, so it can tolerate accuracies of up to ±100␣ ppm. Jitter Tolerance Jitter tolerance describes the ability of the CDR circuit to track timing variations (jitter) in the received signal. The Bellcore and ITU specifications allow the received optical signal to contain jitter. The amount of jitter that must be tolerated is a function of the frequency content of the jitter. The CDR must tolerate many unit intervals (bit times) of low-frequency jitter, but is not asked to tolerate large amounts of jitter at higher frequency. The performance shown in the “Typical Performance Data” section shows that the TQ8103 offers a wide margin over the specification limits. Jitter tolerance is a system-level issue that is directly affected by the quality of the optics, the quality of the layout (and decoupling), and the specific implementation of the loop filter. The recommended loop filter, described above, has been chosen to provide a robust margin on jitter tolerance. For additional information and latest specifications, see our website: www.triquint.com 3 TQ8103 26 VDD 27 VCC 28 VEE 1 VDDA 2 VEEA 3 VCTL 4 OUCHP Figure 4. TQ8103 Pinout VDD 5 2 5 VCC VDD 6 2 4 SEL SINI 7 SINO 8 VEE 9 2 3 LOCK TQ8103 CDR 2 2 SELCK 2 1 XTCKI V D D 18 CKRE F 17 V D D 16 CK OUTP 15 1 9 VCC CK OUTN 14 V E E 11 D OUTP 13 2 0 VEE D OUTN 12 V REF 10 Table 1. Signal Descriptions Pin Signal Type Description 1 VDDA Supply Analog ground for VCO 2 3 4 5 6 7 8 9 10 11 12 13 14 VEEA VCTL OUCHP VDD VDD SINI SINO VEE VREF VEE DOUTN DOUTP CKOUTN Supply Analog In Analog Out Supply Supply ECL In ECL Term Supply Analog Supply ECL Out ECL Out ECL Out Analog –5V supply for VCO VCO control voltage input; connect to loop filter Charge pump output; connect to loop filter Ground (0V) Ground (0V) Serial data input Loopback of SINI for termination of serial data input; connect with 50 Ω to VTT –5V supply Optional reference voltage for single-ended ECL input –5V supply Differential data output, complement Differential data output, true Differential clock output, complement (Continued on next page) 2 For additional information and latest specifications, see our website: www.triquint.com TQ8103 Table 1. Signal Descriptions (continued) Signal CKOUTP VDD CKREF VDD VCC VEE XTCKI SELCK LOCK SEL VCC VDD VCC VEE Type ECL Out Supply TTL In Supply Supply Supply ECL In TTL In TTL Out TTL In Supply Supply Supply Supply Description Differential clock output, true Ground (0V) Reference clock input for frequency detect and lock detect Ground (0V) +5V supply –5V supply External clock input; selected using SELCK External clock select: low = internal VCO, high = XTCLK Lock-detect output Detection circuit select; low = frequency-detect, high = phase-detect +5V supply Ground (0V) +5V supply –5V supply TELECOM PRODUCTS Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Specifications Table 2. Recommended Operating Conditions Parameter Positive supply Negative supply Termination voltage Operating ambient temperature Symbol Minimum Nominal Maximum Unit VCC VEE VTT TA 4.5 –5.5 –1.9 0 5 –5 –2.0 5.5 –4.75 –2.1 85 V V V ˚C Symbol Minimum Nominal Maximum Unit 5 210 mA mA ˚C/W Table 3. Power Consumption Parameter Positive supply current Negative supply current Thermal impedance Note: ICC IEE θJA 40 These values supersede the recommended operating conditions (Table 2) unless otherwise noted. For additional information and latest specifications, see our website: www.triquint.com 5 TQ8103 Table 4. DC Characteristics—ECL I/O (1) Parameter Internal ECL reference Input HIGH voltage Input LOW voltage Condition Symbol Minimum (2) (3) VREF VIH –1100 Nominal Maximum Unit –700 mV mV –1500 mV –700 –1600 mV mV –1300 (3, 4) VIL VTT Output HIGH voltage Output LOW voltage (5) (5) VOH VOL –1000 VTT Input HIGH current (6) IIH 0 µA 10 Table 5. DC Characteristics—TTL I/O (1) Parameter Condition Symbol Minimum Input HIGH voltage VIH Input LOW voltage VIL Input HIGH current Input LOW current VIH(MAX) Nominal Maximum Unit 2.0 VCC V 0 0.8 V 100 µA IIH µA VIL(MIN) IIL –100 Output HIGH voltage IOH = 3 mA VOH 2.4 VCC V Output LOW voltage IOL = –1 mA VOL 0 0.4 V Input capacitance (6) CIN 8 pF Output capacitance (6) COUT 10 pF Condition Symbol Minimum Figure 5 (7) (7) (8) (9) tO t R , tF t R , tF t R , tF 100 Table 6. AC Characteristics (1) Parameter Clock to data time Data output rise/fall times Clock output rise/fall times TTL output rise/fall times Acquire time Notes (Tables 4, 5, and 6): 1. Applies over recommended operating range 2. Single-ended inputs, VEE = –5V 3. VREF = –1300 mV 4. VTT = –2.0V 5. RLOAD = 50 ohms to VTT = –2.0V 6. Not tested; consistent with VOH and VOL tests 7. 50 ohm load, 20% to 80% levels 8. 20 pF load, 0.8V to 2.0V 9. With recommended loop filter 2 Nominal Maximum Unit 350 350 300 ps ps ps ns ms 5 3 Figure 5. Clock-to-Data Timing CKOUT DOUT For additional information and latest specifications, see our website: www.triquint.com tO TQ8103 Table 7. Absolute Maximum Ratings Symbol Minimum Nominal Maximum Unit Positive supply VCC 0 7 V Negative supply Output voltage VEE VO ECL –7 VEE – 0.5 0 +0.5 V V Output current IO ECL — 40 mA Input voltage Input current VI II ECL ECL VEE – 0.5 –1 +0.5 1 V mA Output voltage Output current Input voltage Input current Junction temperature VO IO VI II TJ TTL TTL TTL TTL –0.5 VCC + 0.5 20 VCC + 0.5 1 +150 V mA V mA °C Storage temperature Power dissipation TS PD +175 2 °C W –0.5 –1 –55 –65 TELECOM PRODUCTS Parameter Notes: • If the device is subjected to the listed conditions, its reliability may be impaired. • Beyond the listed conditions, the safety of the device cannot be guaranteed. For additional information and latest specifications, see our website: www.triquint.com 7 TQ8103 Typical Performance Data Figure 6. Jitter Tolerance 4 TQ8103 Jitter Tolerance Bellcore Limit Jitter Tolerance, unit intervals 3.5 3 2.5 2 1.5 1 0.5 0 10 100 1000 10000 Frequency (KHz) Figure 7. Output Eye Diagram with extracted clock Table 8. Typical Performance Data Waveforms PRBS data pattern RMS jitter Peak-to-peak jitter 2 For additional information and latest specifications, see our website: www.triquint.com 2012 2–23 7.855 ps 55 ps TQ8103 Mechanical Specifications Figure 8. TQ8103 Package Dimensions .490 ± .005 .040 MIN. .445 ± .005 .172 ± .005 TELECOM PRODUCTS .045 X 45 1 .410 ± .015 22 8 .445 ± .005 .490 ± .005 .028 .018 15 .015 X 45 (3 PLCS) .125 VENT PLUG .050 TYP . NON-A CCUM. .104 ± .005 .060 Ordering Information TQ8103-Q ETF-8103 622 Mb/s Clock & Data Recovery IC in 28-pin MQuad Package Evaluation Board Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997 For additional information and latest specifications, see our website: www.triquint.com 9