SSM4500GM N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY N-CH BVDSS D2 RDS(ON) D2 Simple Drive Requirement Low On-resistance Fast Switching 20V D1 D1 30mΩ ID G2 S2 SO-8 S1 6A P-CH BVDSS G1 -20V RDS(ON) DESCRIPTION 50mΩ ID -5A The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters. D2 D1 G2 G1 S2 S1 Pb-free; RoHS-compliant ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating N-channel VDS Drain-Source Voltage VGS Gate-Source Voltage ID@TA=25℃ ID@TA=70℃ Units P-channel 20 -20 V ±12 ±12 V 3 6 -5 A 3 4.8 -4 A 20 -20 A Continuous Drain Current Continuous Drain Current 1 IDM Pulsed Drain Current PD@TA=25℃ Total Power Dissipation 2.0 Linear Derating Factor 0.016 W W/℃ TSTG Storage Temperature Range -55 to 150 ℃ TJ Operating Junction Temperature Range -55 to 150 ℃ THERMAL DATA Symbol Rthj-a 02/13/2008 Rev.1.00 Parameter Thermal Resistance Junction-ambient 3 www.SiliconStandard.com Max. Value Unit 62.5 ℃/W 1 SSM4500GM N-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol Parameter Test Conditions BVDSS Drain-Source Breakdown Voltage ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA RDS(ON) 20 - - V - 0.037 - V/℃ VGS=4.5V, ID=6A - - 30 mΩ VGS=2.5V, ID=5.2A - - 45 mΩ VDS=VGS, ID=250uA 0.5 - 1.2 V VDS=10V, ID=6A - 18.5 - S Drain-Source Leakage Current (Tj=25 C) VDS=20V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=16V, VGS=0V - - 25 uA Gate-Source Leakage VGS=±12V - - ID=6A - 9 15 nC Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance o IDSS IGSS 2 VGS=0V, ID=250uA Min. Typ. Max. Units 2 ±100 nA Qg Total Gate Charge Qgs Gate-Source Charge VDS=10V - 1.8 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 4.2 - nC VDS=10V - 29 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=1A - 65 - ns td(off) Turn-off Delay Time RG=6Ω,VGS=4.5V - 60 - ns tf Fall Time RD=10Ω - 50 - ns Ciss Input Capacitance VGS=0V - 300 480 pF Coss Output Capacitance VDS=8V - 255 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 115 - pF SOURCE-DRAIN DIODE Symbol Parameter 2 Test Conditions Min. Typ. Max. Units VSD Forward On Voltage IS=1.7A, VGS=0V - - 1.2 V trr Reverse Recovery Time IS=6A, VGS=0V, - 26 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 17 - nC 02/13/2008 Rev.1.00 www.SiliconStandard.com 2 SSM4500GM o P-CH Electrical Characteristics@Tj=25 C(unless otherwise specified) Symbol Parameter Test Conditions BVDSS Drain-Source Breakdown Voltage ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=-1mA RDS(ON) 2 Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS IGSS VGS=0V, ID=250uA Min. Typ. Max. Units -20 - - V - -0.037 - V/℃ VGS=-4.5V, ID=-2.2A - - 50 mΩ VGS=-2.5V, ID=-1.8A - - 90 mΩ VDS=VGS, ID=-250uA -0.5 - -1 V VDS=-10V, ID=-2.2A - 2.5 - S o VDS=-20V, VGS=0V - - -1 uA o Drain-Source Leakage Current (Tj=70 C) VDS=-16V, VGS=0V - - -25 uA Gate-Source Leakage VGS= ± 12V - - Drain-Source Leakage Current (Tj=25 C) 2 ±100 nA Qg Total Gate Charge ID=-5A - 14 20 nC Qgs Gate-Source Charge VDS=-16V - 2 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 5.6 - nC VDS=-10V - 10 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=-2.2A - 11 - ns td(off) Turn-off Delay Time RG=6Ω,VGS=-10V - 58 - ns tf Fall Time RD=4.5Ω - 38 - ns Ciss Input Capacitance VGS=0V - 940 1500 pF Coss Output Capacitance VDS=-20V - 400 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 160 - pF SOURCE-DRAIN DIODE Symbol Parameter Test Conditions 2 Min. Typ. Max. Units VSD Forward On Voltage IS=-1.8A, VGS=0V - - -1.2 V trr Reverse Recovery Time IS=-2.2A, VGS=0V, - 25 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 21 - nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Surface mounted on 1 in copper pad of FR4 board ; 135℃/W when mounted on Min. copper pad. 02/13/2008 Rev.1.00 www.SiliconStandard.com 3 SSM4500GM N-Channel 25 25 20 15 10 V GS =2.0V 15 10 V GS =2.0V 5 5 0 0 0 1 2 3 4 0 5 V DS , Drain-to-Source Voltage (V) 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.8 45 I D =6A 40 I D =6A V GS =4.5V 1.6 o Normalized RDS(ON) T A =25 C RDS(ON) (mΩ ) 4.5V 3.5V 3.0V 2.5V T A =150 o C 4.5V 3.5V 3.0V 2.5V ID , Drain Current (A) ID , Drain Current (A) T A =25 o C 20 35 30 1.4 1.2 1.0 25 0.8 20 0.6 2 3 4 5 -50 0 50 100 150 T j , Junction Temperature ( o C) V GS (V) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 100.00 1.5 10.00 T j =150 o C 1.00 VGS(th) (V) IS(A) 1 T j =25 o C 0.5 0.10 0 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -50 Fig 5. Forward Characteristic of Reverse Diode 02/13/2008 Rev.1.00 0 50 100 150 T j ,Junction Temperature ( o C) V SD (V) Fig 6. Gate Threshold Voltage v.s. Junction Temperature www.SiliconStandard.com 4 SSM4500GM N-Channel f=1.0MHz 6 1000 I D =6A V DS =10V Ciss 4 C (pF) VGS , Gate to Source Voltage (V) 5 3 Coss 100 Crss 2 1 0 10 0 2 4 6 8 10 12 1 5 9 Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics 17 21 25 29 Fig 8. Typical Capacitance Characteristics 100 Normalized Thermal Response (Rthja) 1 10 1ms ID (A) 13 V DS (V) 10ms 1 100ms 1s 10s DC T A =25 o C Single Pulse 0.1 Duty Factor = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t T Single Pulse Duty factor = t/T Peak T j = P DM x R thja + Ta Rthja =135o C/W 0.001 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) V DS (V) Fig9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Fig 11. Switching Time Waveform 02/13/2008 Rev.1.00 Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 5 SSM4500GM P-Channel 25 25 4.5V 4.0V 3.5V 3.0V -ID , Drain Current (A) T A =150 o C 15 10 4.5V 4.0V 3.5V 3.0V 20 -ID , Drain Current (A) T A =25 o C 20 V GS =2. 5 V 15 V GS =2. 5 V 10 5 5 0 0 0 1 2 3 4 0 5 1 2 3 4 5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 1.8 I D =-2.2A T A =25 ℃ 90 I D =-2.2A V GS = -4.5V 1.6 Normalized RDS(ON) RDS(ON) (mΩ ) 80 70 60 50 1.4 1.2 1 0.8 40 0.6 30 2 3 4 -50 5 -V GS (V) 0 50 100 150 T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 100.00 1 0.8 o o T j =150 C 1.00 -VGS(th) (V) -IS(A) 10.00 T j =25 C 0.6 0.4 0.10 0.2 0 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 -50 Fig 5. Forward Characteristic of Reverse Diode 02/13/2008 Rev.1.00 0 50 T j ,Junction Temperature ( -V SD (V) 100 o 150 C) Fig 6. Gate Threshold Voltage v.s. Junction Temperature www.SiliconStandard.com 6 SSM4500GM P-Channel f=1.0MHz 10000 I D =-5A V DS =-16V 5 1000 4 Ciss C (pF) -VGS , Gate to Source Voltage (V) 6 3 Coss Crss 100 2 1 10 0 0 4 8 12 16 1 20 5 9 13 17 21 25 29 -V DS (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1 100 10 Normalized Thermal Response (R thja) Duty Factor = 0.5 1ms -ID (A) 10ms 1 100ms 1s 0.1 T A =25 o C Single Pulse 10s DC 0.01 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t T Single Pulse Duty factor = t/T Peak Tj = PDM x Rthja + T a Rthja=135 oC/W 0.001 0.1 1 10 100 0.0001 0.001 -V DS (V) 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Fig9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Waveform 02/13/2008 Rev.1.00 Charge Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 SSM4500GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/13/2008 Rev.1.00 www.SiliconStandard.com 8