UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION The UT62L25616(I) is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. Fast access time : 55/70/100 ns CMOS Low operating power Operating current: 45/35/25mA (Icc max) Standby current: 20 uA(TYP.) L-version 3 uA(TYP.) LL-version Single 2.7V~3.6V power supply Operating temperature: Industrial : -40℃~85℃ All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage: 1.5V (min) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOPⅡ 48-pin 6mm × 8mm TFBGA The UT62L25616(I) operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L25616(I) is designed for low power system applications. It is particularly suited for use in high-density high-speed system applications. PIN DESCRIPTION SYMBOL A0 - A17 I/O1 - I/O16 CE FUNCTIONAL BLOCK DIAGRAM WE OE A0 LB UB VCC VSS NC A1 A2 . A3 A4 ROW A8 A13 DECODER MEMORY ARRAY . 2048 Rows x 128 Columns x 16 bits Write Enable Input Output Enable Input Lower-Byte Control High-Byte Control Power Supply Ground No Connection VSS . A14 VCC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input A15 A16 A17 I/O1 ... I/O16 CE WE OE LB UB . ... I/O CONTROL LOGIC .. . . . COLUMN I/O COLUMN DECODER CONTROL A9 A10 A11 A12 A5 A6 A7 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION 44 A5 43 42 A6 A2 2 3 A1 4 41 OE A0 40 UB CE 5 6 I/O1 7 I/O2 8 I/O3 9 I/O4 10 11 Vcc Vss I/O5 12 UT62L25616(I) 1 A4 A3 13 A7 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vcc I/O13 NC A16 I/O5 Vss 39 LB 38 37 I/O16 I/O15 36 I/O14 35 I/O13 34 Vss 33 32 Vcc I/O12 F I/O15 I/O14 A14 A15 I/O6 I/O7 31 I/O11 G I/O16 NC A12 A13 WE I/O8 30 I/O10 29 I/O9 H NC A8 A9 A10 A11 NC 28 27 NC A8 1 2 3 4 5 6 I/O6 14 I/O7 15 I/O8 WE 16 17 A17 18 A16 A15 19 20 26 A9 25 A10 A14 21 A13 22 24 23 A12 A11 TFBGA TSOP II TRUTH TABLE MODE Standby Output Disable Read Write Note: CE OE WE LB UB H X L L L L L L L L X X H X L L L X X X X X H X H H H L L L X H X H L H L L H L X H X H H L L H L L I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB, ISB1 ISB, ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to +150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = -40℃ to 85℃(I)) PARAMETER SYMBOL TEST CONDITION Power Voltage VCC Input High Voltage VIH Input Low Voltage VIL Input Leakage Current ILI VSS ≦VIN ≦VCC Output Leakage Current ILO VSS ≦VI/O ≦VCC; Output Disabled Output High Voltage VOH IOH= -1mA Output Low Voltage VOL IOL= 2.1mA Operating Power ICC Cycle time=min, 100%duty, Supply Current I/O=0mA, CE =VIL ; Average Operation Current Icc1 Icc2 Standby Current (TTL) ISB Standby Current (CMOS) ISB1 MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V 2.0 VCC+0.3 V -0.2 0.6 V -1 1 µA -1 1 µA 2.2 V 0.4 V 55 30 45 mA 70 25 35 mA 100 20 25 mA 4 5 mA Cycle time=1µs,100%duty,I/O=0mA, CE ≦0.2V,other pins at 0.2V or Vcc-0.2V, Cycle time=500ns,100%duty,I/O=0mA, 8 10 mA CE ≦0.2V,other pins at 0.2V or Vcc-0.2V, 0.3 0.5 mA CE =VIH, other pins =VIL or VIH, CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V, UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 -L -LL - 20 3 80 25 µA µA P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA / 2.1mA AC ELECTRICAL CHARACTERISTICS (VCC =2.7V~3.6V, TA = -40℃ to 85℃(I)) (1) READ CYCLE PARAMETER SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 55 70 100 ns Address Access Time tAA 55 70 100 ns Chip Enable Access Time tACE 55 70 100 ns Output Enable Access Time tOE 30 35 50 ns Chip Enable to Output in Low Z tCLZ* 10 10 10 ns Output Enable to Output in Low Z tOLZ* 5 5 5 ns Chip Disable to Output in High Z tCHZ* 20 25 30 ns Output Disable to Output in High Z tOHZ* 20 25 30 ns Output Hold from Address Change tOH 5 5 5 ns t 55 70 100 ns BA , Access Time LB UB tHZB 25 30 40 ns LB , UB to High-Z Output t 0 0 0 ns LZB LB , UB to Low-Z Output (2) WRITE CYCLE PARAMETER SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Write Cycle Time tWC 55 70 100 ns Address Valid to End of Write tAW 50 60 80 ns Chip Enable to End of Write tCW 50 60 80 ns Address Set-up Time tAS 0 0 0 ns Write Pulse Width tWP 45 55 70 ns Write Recovery Time tWR 0 0 0 ns Data to Write Time Overlap tDW 25 30 40 ns Data Hold from End of Write Time tDH 0 0 0 ns Output Active from End of Write tOW* 5 5 5 ns Write to Output in High Z tWHZ* 30 30 40 ns t 45 60 80 ns BW , Valid to End of Write LB UB *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2,4) tRC Address tAA tOH tOH DOUT Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6) t RC t BA Address t AA t ACE CE LB , UB t BLZ OE t t Dout t OE CLZ HIGH-Z t t t CHZ OHZ OH OLZ HIGH-Z Data Valid t BHZ Notes : 1. WE is HIGH for read cycle. 2. Device is continuously selected CE =VIL. 3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5) t WC Address t AW CE t CW t AS t WR t WP WE t BW LB , UB t WHZ Dout t OW High-Z (4) (4) t DW t DH Din Data Valid WRITE CYCLE 2 ( CE Controlled) (1,2,5) t WC Address t AW CE t AS t CW t WR t WP WE t BW LB , UB t WHZ High-Z Dout t DH t DW Din Data Valid Notes : 1. WE or CE must be HIGH during all address transitions. 2. A write occurs during the overlap of a low CE and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after WE high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. LOW transition, the outputs remain in a Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃(I)) PARAMETER Vcc for Data Retention SYMBOL VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tCDR TEST CONDITION CE ≧ VCC-0.2V Vcc=1.5V CE ≧ VCC-0.2V See Data Retention Waveforms (below) MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 1 0.5 50 20 0 - - µA µA ms 5 - - ms -L - LL tR DATA RETENTION WAVEFORM Data Retention Mode VCC 2.7V 2.7V VDR ≧ 1.5V CE VSS tCDR tR CE ≧ VCC -0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION θ 44 pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L 2D y Θ DIMENSIONS IN MILLMETERS MIN NOM MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 0 5 DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 48 pin 6mm×8mm TFBGA Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80054 UTRON UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM Rev. 1.1 ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. UT62L25616MC-55LI UT62L25616MC-55LLI UT62L25616MC-70LI UT62L25616MC-70LLI UT62L25616BS-55LI UT62L25616BS-55LLI UT62L25616BS-70LI UT62L25616BS-70LLI ACCESS TIME (ns) 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) TYP. 20 3 20 3 20 3 20 3 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA P80054 UTRON Rev. 1.1 UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY REVISION Preliminary Rev. 0.5 Rev. 1.0 Rev. 1.1 DESCRIPTION Original. 1. The symbols CE# and OE# and WE# are revised as. CE and OE and WE . 2. Separate Industrial and Consumer SPEC. 3. Add access time 55ns range. 4. The power supply is revised: 3.3V 3.6V 1. Revised PIN CONFIGURATION : Rev 1.0 : No A17 pin typing error Rev 1.1 : add A17 pin. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 DATE Mar, 2001 Jul 4,2001 Oct 18,2001 P80054 UTRON Rev. 1.1 UT62L25616(I) 256K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80054