FS450, FS451
i-Net TV Interface
Video Processor
has a programmable down scaler to fit the
incoming resolution to the output display format.
The CCIR 656 ports allow external interface to
other video chips. The sync control block
generates frame reset for genlocking other video
components. Required external components are
minimal: a single 27 MHz oscillator or crystal
and passive parts.
Features
•
•
•
–
–
–
•
•
•
–
–
–
–
•
–
–
•
•
•
•
•
•
•
•
Flexible clock, data, and electrical interfaces
allows glue-less digital interface to Intel
82810, National Geode and most other
graphic controller chips ("GCC")
Capable of operating as clock master,
pseudo-master, and slave and supports both
single and differential master clocks
Programmable 2D scaling †
Variable horizontal up and down scale
Variable vertical downscale
Output format can be tuned to the exact
dimensions of the TV
Advanced 2-D flicker filter †
Supports Multiple Progressive Input
Resolutions
640x480 to 1024x768
Multiple Output Standards
NTSC, NTSC-EIAJ, PAL-B/D/G/H/I/M/N
Composite, S-Video, RGB SCART
Composite Y-Notch and C-Bandpass
Filters
Genlock the GCC and incoming Video
Provides the pixel clock to the GCC
generated from a single 27MHz clock
Provides frame synchronization output
signal for other video components
CCIR 656 outputs
CCIR 656 input to the encoder
10-bit output D/A converters
Macrovision 7 compliant (FS451 only)
I2C‡ compatible port controls
High level programming interface
100 pin PQFP package
3.3V operation
Digital progressive RGB inputs are downscaled or
upscaled to the CCIR-656 horizontal pixel count
and converted to the 656 format. Vertical scaling
and flicker filtering are done in 656 format.
The Flicker Filter is an advanced 2 dimensional
filter that enhances text quality. Flicker Filter and
Sharpness parameters are programmable.
A digital video encoder that generates analog Y/C
and Composite Video outputs is part of the
FS450. For the composite output in NTSC, YNotch and C-Bandpass filters are available. For
RGB and YUV outputs, the encoder may be
bypassed via a YUV to RGB transcoder for
SCART compatible video.
Scaling and clock parameters are automatically
programmed by the driver, so the system remains
genlocked with resolution changes. The input
parameters to the automatic scaling are TV
viewable area, PAL or NTSC, and the GCC CRT
Control Registers’ settings.
The FS451's encoder incorporates Macrovision 7
anti-copy protection technology.
All parameters can be read and written via the I2C
compatible serial port.
Power is derived from +3.3V digital and analog
supplies. The package is 100-lead Quad Flat
Pack (PQFP).
†Note: Covered under US Patent # 5,862,268 and/or
patents pending.
‡
Note: I2C is a registered trademark of Philips Corporation.
The FS450 SIO bus is similar but not identical to Philips I2C
bus.
Applications
•
•
•
•
•
•
Description
The i-Net TV FS450 is a fourth generation video
scan converter. It accepts many input
resolutions, rates and formats and converts them
to NTSC or PAL standards compliant with
SMPTE-170M and CCIR-656 standards. The chip
JUNE, 2000, VERSION 1.2
1
Internet Set Top Boxes
PC video out (TV Ready PCs)
Cable/DVD Player Set Top Boxes
Web Appliances
Information Appliances
Video Kiosks
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
Typical System Architectural Block Diagram
OSC
DVD
656
YUV to
RGB
Synch Control
VGA Synchs
GCC Chip
RGB
DACs
Color Space
Converter
Horz and Vertical
Down Scaler
Flicker
Filter
656
Encoder
Composite
and Y/C
VGA Pixel
Clock
PLL
FS450
Figure 1: Typical System Block Diagram
JUNE, 2000, VERSION 1.2
2
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
1. Table of Contents, Figures & Tables
1.
2.
3.
4.
5.
6.
Table of Contents, Figures & Tables
3
Architectural Overview
5
2.1 Oscillators and PLLs ........................... 5
2.2 Serial Control Port ............................... 6
2.3 Sync Control....................................... 6
2.4 Input and Output Frame Formats .......... 6
2.5 Color Space Converter and Scaler......... 7
2.6 Flicker Filter........................................ 7
2.7 Encoder.............................................. 7
2.8 YUV to RGB Converter......................... 7
Typical System Configurations
8
3.1 GCC ⇒ TV Output Only....................... 8
3.2 GCC or DVD Output Switched ⇒ TV..... 9
3.3 Multiple Digital Video Sources Blended
⇒ TV ............................................... 10
Pin Assignments
11
4.1 FS450 ⇔ GCC Pin Mapping............... 12
Pin Descriptions
13
Control Register Definitions
16
6.1 Control Register Map ......................... 16
6.2 Control Register Definitions ................ 20
6.2.1 IHO - Input Horizontal Offset ...... 20
6.2.2 IVO - Input Vertical Offset.......... 20
6.2.3 IHW - Input Horizontal Width ..... 21
6.2.4 VSC – Vertical Scaling Coefficient21
6.2.5 HDSC, HUSC – Horizontal
Down/Up Scaling Coefficients .... 22
6.2.6 CR - Command Register ........... 23
6.2.7 SP - Status Port....................... 25
6.2.8 NCON - Numerator of NCO Word26
6.2.9 NCOD - Denominator of NCO Word
............................................... 27
6.2.10 APO, ALO, AFO - Auxiliary Pixel,
Line, and Field Offsets .............. 28
6.2.11 HSOUTWID, HSOUTST,
HSOUTEND - HSync Out Width,
Starting and Ending Edge.......... 29
6.2.12 SHP, FLK - Sharpness and Flicker
Filter ....................................... 32
6.2.13 REV - Revision Number............. 33
6.2.14 MISC - Miscellaneous Bits 34, 35
Register................................... 34
6.2.15 FIFOL, FIFOH - FIFO Status Port
Full/Empty............................... 35
6.2.16 FFO_LAT - FIFO Latency.......... 35
6.2.17 VSOUTWID, VSOUTST,
VSOUTEND - VSync Out Width,
Starting and Ending Edge.......... 36
6.2.18 CHR_FREQ - Chroma Subcarrier
Frequency ............................... 37
JUNE, 2000, VERSION 1.2
6.2.19 Chroma Phase, Miscellaneous Bits
45 ........................................... 38
6.2.20 Miscellaneous Bits Registers 46
and 47..................................... 39
6.2.21 HSync Width (48), Burst Width
(49) ......................................... 40
6.2.22 Back Porch Width (4A), Cb Burst
Amplitude (4B)......................... 40
6.2.23 Cr Burst Amplitude (4C),
Miscellaneous Bits Register 4D . 41
6.2.24 Black Level (4E)....................... 41
6.2.25 Blank Level (50)........................ 42
6.2.26 Number of Lines (57-58) ............ 42
6.2.27 White Level (5E)....................... 43
6.2.28 Cb Color Saturation (60)............ 43
6.2.29 Cr Color Saturation (62)............. 43
6.2.30 Tint (65)................................... 44
6.2.31 Width of Breezeway (69) ........... 44
6.2.32 Front Porch (6C)....................... 44
6.2.33 Active Video Line (71-72), First
Video Line (73)......................... 45
6.2.34 Miscellaneous Bits 74, Sync Level
(75) ......................................... 46
6.2.35 VBI Blank Level (7C)................. 47
6.2.36 SOFT_RST, ENC_VER - Encoder
Soft Reset, Encoder Version ..... 47
6.2.37 Misc. Bit Reg. 80, WSS Clock (8182), WSS Data F1(83-85).......... 48
6.2.38 WSS Data Field 0(86-88), WSS
Line Number Field 1 (89) ........... 49
6.2.39 WSS Field 0 Line Number, WSS
Level, Misc. Bits Reg. 8D (8A-8D)50
7.
Design and Layout Considerations
52
7.1 Pixel Phase Lock Loop ...................... 52
7.2 Video Output Filters........................... 52
7.3 Analog Power Supply Bypassing,
Filtering, and Isolation........................ 52
7.4 Power and Ground............................. 52
7.5 Interfacing to the FS450 in a Mixed
Voltage Environment .......................... 53
7.5.1 Interfacing to the SIO bus.......... 53
8.
Specifications
55
8.1 Absolute Maximum and Recommended
Ratings............................................. 55
8.2 Electrical Characteristics ................... 56
8.3 Switching Characteristics................... 57
9.
Mechanical Dimensions
58
9.1 100-Lead PQFP (KH) Package ........... 58
10. Revision History
59
11. Order Information
59
3
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Figure 1: Typical System Block Diagram ................ 2
Figure 2: FS450 Functional Block Diagram ............. 5
Figure 3: GCC Frame Format ................................ 6
Figure 4: CCIR 601/656 Field Format...................... 7
Figure 5: GCC ⇒ TV Output Only .......................... 8
Figure 6: GCC or DVD output switched ⇒ TV ......... 9
Figure 7: Multiple digital video sources blended
⇒ TV ......................................................... 10
Figure 8: CCIR 656 Timing Block Diagram ............ 30
Figure 9: Auxiliary NTSC Reference Signals.......... 31
Figure 10: Auxiliary PAL Reference Signals .......... 31
Figure 11. SIO Translation Using Long-tail
Resistors D1 = 1N4148................................ 53
Figure 12. SIO Translation Using Current Mirrors
D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904 .... 54
Figure 13: Package Outline & Dimensions ............ 58
Table 1: FS45x Pin Assignments......................... 11
Table 2: FS450 to GCC Pin Mapping.................... 12
Table 3: SAV and EAV Control Words.................. 24
Table 4: GCC Port Mapping (UIM_MOD)............... 24
Table 5: NCO_LOAD Control Bits......................... 34
Table 6: NOTCH_FRQ Values.............................. 50
Table 7: Typical Register Values for Various
Standards ................................................... 51
JUNE, 2000, VERSION 1.2
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
4
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
2. Architectural Overview
The FS450 i-Net TV Video Interface Processor provides NTSC or PAL TV out for Intel's 82810 Video Coprocessor and many other 3D graphic controller ("GCC") chips. It accepts digital RGB in, converts it to
CCIR 656 digital video, provides interfaces to external 656 digital DVD systems, windowing hardware, alpha
blenders, et al and outputs very high quality RGB, YUV, S-Video, or Composite Video. The chip consists of
the following major sections:
VSync
HSync
Blank
/6
/24
Cache /24
RGB
to
YUV
/16
V
/16
Flicker
/32
Filter
FIFO
H
/16
/3
VGA
Timing
Generator
/3
/32
CCIR656
Formatter
H
/24
Color Space Converter & Scaler
Flicker Filter
Encoder
YUV to RGB Converter
CCIR
656
In
/8
CCIR 656
Timing
Generator
YUV
to
RGB
/16
/30
Multiplexer
ERED
EGRN
EBLU
/12
Demux
RED
GRN
BLU
•
•
•
•
Oscillators and PLLs
Serial Control Port
Sync Control
Input and Output Frame Formats
Universal Input Mux
& Prescaler
•
•
•
•
H
Encoder
HBlank In
VBlank In
Field In
/30
/10
DAC
RED/LUMA
/10
DAC
GRN/CVBS
/10
DAC
BLU/CHRMA
/2
/8
HBlank Out
VBlank Out
Field Out
Auxiliary
HREF
VREF
/3
Decoder
27 MHz
Clock
NCO
Divider
ow
VCO
CPU
VGA
Clock
Divider
Figure 2: FS450 Functional Block Diagram
2.1 Oscillators and PLLs
The FS450 synthesizes a 27 to 85 MHz clock off of the 27 MHz Television clock and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to
the RGB data and Sync information. This clock has a 1½ Hz resolution and must be adjusted so the GCC
scaled input data rate exactly matches the CCIR 656 data output rate.
The VG_CKOUT Phase Lock Loop (PLL) synthesizer uses Numerically Controlled Oscillator (NCO) to fine
adjust the 27MHz oscillator to a clock precisely matched to the digital RGB data coming from the GCC.
Additionally, the PLL itself can be controlled by programming the numerator (M) and denominator (N) of the
PLL itself. The combination of the PLL synthesizer and NCO are used to precisely match the input to the
output.
JUNE, 2000, VERSION 1.2
5
CCIR
656
Out
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
2.2 Serial Control Port
FS450 setup is programmed by registers that are accessible via the I2C‡ compatible serial port (SIO).
Status and Revision ID can also be read from the registers.
‡
Note: I2C is a registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identical
to Philips I2C bus.
2.3 Sync Control
The FS450 operates in a slave mode, pseudo-master mode or full master mode. In pseudo-master mode,
the GCC graphic controller derives the VGA pixel clock, horizontal sync, and vertical sync from
VGA_CLKOUT supplied by the FS450. The syncs are used inside the FS450 to capture the computer video
and are regenerated to supply to external devices such as genlocked video from a DVD player or tuner. In
full master mode, the FS450 supplies to the GCC horizontal and vertical sync in addition to the VGA pixel
clock.
2.4 Input and Output Frame Formats
The FS450 does not contain a frame memory. Therefore, the FS450 output frame rate must be
synchronous to the input frame rate. To accomplish this, the active video portion in the output stream must
overlay the corresponding active video time in the input stream. Several registers on the FS450 control this
timing as illustrated in the following figures:
VGA_HSYNC
IHO
VGA_VSYNC
IVO
C
D
IVO + IVW
B
A
IHO + IHW
Blank
Blank
Blank
Blank
Blank
Black
Blank
Black
Blank
Black
Blank
Black
Active Video
Black
Blank
Blank
Blank
Black
Blank
Black
Blank
Black
Blank
Blank
Blank
Figure 3: GCC Frame Format
IHO = OHO / Hscale
IHW = OHW / Hscale
IVO = OVO / Vscale
IVW = OVW / Vscale
The output frame timing is determined by the CCIR601 and 656 specifications. Input parameters IHO, IVO,
and IHW must be set correctly so that when the image is scaled to the 656 output frame, the timing
requirements are met. Parameters A, B, C, and D are determined by the amount of underscan the user
wants on the target television screen.
JUNE, 2000, VERSION 1.2
6
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
656_HSYNC
OHO
656_VSYNC
OVO
C^
D^
OVO + OVW
B^
A^
OHO + OHW
Blank
Blank
Blank
Black
Blank
Black
Blank
Black
Blank
Black
Active Video
Black
Blank
Blank
Black
Blank
Black
Blank
Black
Blank
Figure 4: CCIR 601/656 Field Format
OHO = 139 NTSC, 145 PAL
OHW = 720
OVO = 20 NTSC, 23 PAL
OVW = 487 NTSC, 576 PAL
2.5 Color Space Converter and Scaler
The digital RGB from the GCC is horizontally compressed, stored into a line buffer cache. As the data is
pulled from the line buffer cache, it is converted to 656 YUV and compressed vertically.
2.6 Flicker Filter
The FS450 flicker filter provides significantly more control over the display characteristics than a typical 3
line average flicker filter. The FS450's flicker filter consists of both horizontal (Sharpness) and vertical
(Flicker) controls. Thus, it is called a 2D flicker filter. Both the Sharpness and Flicker registers can be
programmed over a wide range to allow the user to tradeoff flicker and sharpness for readability and reduced
eye fatigue.
2.7 Encoder
The FS450 contains a high quality 2x oversampled video encoder. The 656 luma information is up-sampled
from 13.5 MHz sample rate to 27 MHz with a 19 tap filter which offers excellent flatness to 6MHz and 50 dB
image aliasing suppression. Chrominance information is up-sampled from 6.75MHz sample rate to 27 MHz
with four user selectable bandwidths. The encoder has programmable width and frequency luma notch filter.
The encoder subcarrier is programmable in frequency and phase and with the independence of color format,
vsync, and number of lines allows for the support of the many video standards, including all South American
variations. The FS450 video encoder outputs NTSC M, J and PAL B, D, G, H, I, M, N, Combination N
formats with 10 bits of resolution. Both Composite and S-Video outputs are available simultaneously.
2.8 YUV to RGB Converter
As an alternative to encoded PAL or NTSC, the user may select analog RGB outputs. Each channel of
RGB has 10 bits of resolution.
JUNE, 2000, VERSION 1.2
7
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
3. Typical System Configurations
There are 3 "typical" system configurations envisioned for the FS450:
1) GCC ⇒ TV output only;
2) GCC or DVD output switched ⇒ TV;
3) Multiple digital video sources blended ⇒ TV.
3.1 GCC ⇒ TV Output Only
27 MHz
OSC
YUV to
RGB
Synch
Control
VGA
Synchs
GCC
DACs
RGB
Color Space
Converter
Horz and
Down
Vertical
Scaler
Flicker
Filter
Encoder
Composite
and Y/C
VGA Pixel
Clock
PLL
FS450
Figure 5: GCC ⇒ TV Output Only
JUNE, 2000, VERSION 1.2
8
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
3.2 GCC or DVD Output Switched ⇒ TV
OSC
DVD
656
YUV to
RGB
Synch Control
VGA Synchs
GCC
RGB
DACs
Color Space
Converter
Horz and Vertical
Down Scaler
Flicker
Filter
656
Composite
and Y/C
Encoder
VGA Pixel
Clock
PLL
FS450
Figure 6: GCC or DVD output switched ⇒ TV
JUNE, 2000, VERSION 1.2
9
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
3.3 Multiple Digital Video Sources Blended ⇒ TV
MPEG2
Decoder
CCIR 656
Video
Decoder
Frame
Memory
CCIR 656
CCIR 656
Output
Control
CCIR 656
Alpha
Blend
Video Syncs
27 MHz Decoder Clk
CCIR
656
Crystal
Osc
27 MHz Encoder Clk
CCIR
656
Sync Control
YUV to
RGB
RGB
VGA Syncs
VGA
Controller
DA
Cs
RGB
Color Space
Converter
Horz and Vertical
Down Scaler
Flicker
Filter
Encoder
Composite
and Y/C
VGA Clk In
VGA Clk Out
NCO
and
PLL
Houston
Figure 7: Multiple digital video sources blended ⇒ TV
JUNE, 2000, VERSION 1.2
10
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
4. Pin Assignments
51
80
81
50
100
31
1
Pin
30
Name
Pin
Name
Pin
Name
Pin
Name
1.
R
TV_CKIN
31. P
VGA_CKOUT
51. R
P2
81. O
V656_OUT4
2.
O
XTAL
32. R
V SS
52. R
P3
82. R
V DD
3.
R
V DDOSC
33. R
V DD
53. R
P4
83. O
V656_OUT5
4.
R
V SSOSC
34. O
Reserved (open)
54. R
P5
84. O
V656_OUT6
5.
G
Reserved (GND)
35. O
Reserved (open)
55. R
GTL_REF
85. O
V656_OUT7
6.
N
Reserved (open)
36. S
E5
56. R
V DD
86. R
V SS
7.
R
V SSDA
37. O
E4
57. R
P6
87. S
FIELD_IN
8.
R
V REF
38. R
V SS
58. R
P7
88. S
VBNK_IN
9.
R
RREF
39. O
VGA_CKOUTTL
59. R
P8
89. S
HBNK_IN
10. R
V DDDA
40. O
E3
60. R
P9
90. R
V DD
11. R
CBYPASS
41. O
E2
61. R
V SS
91. S
V656_IN0
12. O
Y/Red
42. O
E1
62. R
P10
92. S
V656_IN1
13. R
V DDDA
43. O
E0
63. R
P11
93. S
V656_IN2
14. R
V SSDA
44. R
BLANK
64. R
VGA_NCKIN
94. S
V656_IN3
15. O
CVBS/Green
45. R
V DD
65. R
VGA_PCKIN
95. R
V SS
16. R
V DDDA
46. R
VSYNC_IN
66. R
V DD
96. S
V656_IN4
17. O
C/Blue
47. R
HSYNC_IN
67. O
AVREF
97. S
V656_IN5
18. R
V DDDA
48. R
P0
68. O
VSYNC_OUT
98. S
V656_IN6
19. O
CSYNC
49. R
P1
69. O
AHREF
99. S
V656_IN7
20. N
Reserved (open)
50. R
V SS
70. R
V SS
100. N
Reserved (open)
21. N
Reserved (open)
71. O
HSYNC_OUT
22. R
V DDPA
72. O
FIELD_OUT
23. R
SCLK
73. O
VBNK_OUT
24. R
25. R
SDATA
SA 10/7
74. R
75. O
V DD
HBNK_OUT
26. R
SA 0
76. O
V656_OUT0
27. R
V SSPA
77. O
V656_OUT1
28. R
RESET
78. R
V SS
29. G
Reserved (GND)
79. O
V656_OUT2
30. G
Reserved (GND)
80. O
V656_OUT3
Table 1: FS45x Pin Assignments
R = Signal Required
O = Signal if used, else no connect
S = Signal if used, else ground
JUNE, 2000, VERSION 1.2
G = Always Ground
N = Always No Connect
11
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
4.1 FS450 ⇔ GCC Pin Mapping
The following table maps the FS450/1 pins to the host GCC controller chip. Please contact your FOCUS
representative to obtain the most up-to-date reference schematics before initiating a design.
FS450
Pin #
FS450/1
Pin Name
Intel
82810
Pin Name
UIM_MOD=0
National
Cx5530
MediaGX
UIM_MOD=3
nVidia
Riva TNT
Pin Name
UIM_MOD=1
S3
Savage
Pin Name
UIM_MOD=1
31
VGA_CKOUT
TVCLKIN
39
VGA_CKOUTTL
TVCLK
TVCLKIN
TVCLK
65
VGA_PCKIN
CLKOUT0
64
VGA_NCKIN
CLKOUT1
FP_CLK
TVCLKOUT
TVCLKR
47
HSYNC_IN
TVHSYNC
FP_HSYNC_OUT
TVHS
46
VSYNC_IN
TVVSYNC
FP_VSYNC_OUT
TVVS
71
HSYNC_OUT
TVHSYNC
68
VSYNC_OUT
TVVSYNC
44
BLANK
BLANK
48
P0
LTVDATA0
FP_DATA6
TVD0
TVDAT0
49
P1
LTVDATA1
FP_DATA7
TVD1
TVDAT1
51
P2
LTVDATA2
FP_DATA8
TVD2
TVDAT2
52
P3
LTVDATA3
FP_DATA9
TVD3
TVDAT3
53
P4
LTVDATA4
FP_DATA10
TVD4
TVDAT4
54
P5
LTVDATA5
FP_DATA11
TVD5
TVDAT5
57
P6
LTVDATA6
FP_DATA12
TVD6
TVDAT6
58
P7
LTVDATA7
FP_DATA13
TVD7
TVDAT7
59
P8
LTVDATA8
FP_DATA14
TVD8
TVDAT8
60
P9
LTVDATA9
FP_DATA15
TVD9
TVDAT9
62
P10
LTVDATA10
FP_DATA16
TVD10
TVDAT10
63
P11
LTVDATA11
FP_DATA17
TVD11
TVDAT11
43
E0
FP_DATA0
42
E1
FP_DATA1
41
E2
FP_DATA2
40
E3
FP_DATA3
37
E4
FP_DATA4
36
E5
23
SCLK
LTVCL
DDC_SCL
SPSCL
SPCLK1
24
SDATA
LTVDA
DDC_SDA
SPSDA
SPD1
BLANK
FP_DATA5
Table 2: FS450 to GCC Pin Mapping
JUNE, 2000, VERSION 1.2
12
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
5. Pin Descriptions
Pin
Name
Clocks
VGA_CKOUT
Pin
Number
Type/Value
Pin Function Description
31
VGA_CKOUTTL
39
GTLP output
(open drain)
LVTTL output
VGA_PCKIN
65
GTLP input
VGA_NCKIN
64
GTLP input
TV_CKIN
1
LVTTL input
XTAL
2
LVTTL output
HSYNC_OUT
71
LVTTL output
VSYNC_OUT
68
LVTTL output
VGA Clock Output. Clock to GCC TVCLKIN. Synthesized
from TV_CKIN. 27 to 85 MHz range.
VGA Clock Output. Clock to GCC TVCLKIN. Synthesized
from TV_CKIN. 27 to 85 MHz range.
VGA Clock Input Positive Edge. Clock from GCC
CLKOUT, buffered form of VGA_CKOUT. Used to latch rising
edge RGB data.
VGA Clock Input Negative Edge. Clock from GCC
CLKOUT, buffered form of VGA_CKOUT. Used to latch
negative edge RGB data.
Television Clock Input. Clock for the CCIR 656 I/O and the
video encoder. 27 MHz.
Television Clock XTAL Output. Buffered version of
TV_CKIN. For use with a 27 MHz crystal.
HSYNC Output. Output from FS450 to GCC to support slave
mode operation.
VSYNC Output. Output from FS450 to GCC to support slave
mode operation.
Global Controls and Reserved Pins
RESET
28
TTL input
(pull down)
Reserved
5,29,30
TTL input
(ground)
Reserved
6,20,21, LVTTL output
34,35,100 (leave open)
Digital RGB Inputs
P11-P0
63,62,60,5 GTLP input
9,58,57,54
,53,52,51,
49,48
E5-E0
36,37,40,4 GTLP input
1,42,43
GTL_REF
55
GTLP REF
HSYNC_IN
VSYNC_IN
BLANK
47
46
44
JUNE, 2000, VERSION 1.2
GTLP input
GTLP input
GTLP input
Reset. Active Low. Resets internal state machines and
initializes default register values.
Reserved Inputs. Connect to VSS.
Reserved Outputs. Do not connect.
Digital GTLP port input. Digital video input, multiplexed or
non-multiplexed. Connects to GCC's digital video out.
Digital GTLP port input. Non-multiplexed extended digital
video input. Connects to GCC's digital video out.
Digital GTLP Reference input. Voltage threshold reference
for GTLP inputs. Reference is 1.0 volts.
Digital HSYNC VGA input. Connects to GCC TVHSYNC.
Digital VSYNC VGA input. Connects to GCC TVVSYNC.
Digital BLANK VGA input. True outside of GCC active
area. Connects to GCC BLANK#.
13
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
Pin
Name
Video Outputs
Y/Red
PRELIMINARY PRODUCT DESCRIPTION
Pin
Number
Type/Value
12
analog video
CVBS/Green
15
analog video
C/Blue
17
analog video
CSYNC
19
LVTTL output
Voltage Reference
VREF
8
+1.276 V
RREF
390/780Ω
CBYPASS
9
11
0.1 µF
CCIR 656 Input Port
V656_IN7-0
99,98,97,9 TTL input
6,94,93,92 (pull down)
,91
HBNK_IN
89
TTL input
(pull down)
VBNK_IN
88
TTL input
(pull down)
FIELD_IN
87
TTL input
(pull down)
JUNE, 2000, VERSION 1.2
Pin Function Description
Video output. As programmed by Command Register
OFMT bit:
0 Luminance component Y of S-video.
1 Red component of RGB.
Video output. As programmed by Command Register OFMT
bit:
0 Composite video.
1 Green component of RGB.
Video output. As programmed by Command Register OFMT
bit:
0 Chrominance component of S-video.
1 Blue component of RGB.
Composite sync output. Active high digital composite sync
for SCART video outputs.
Voltage reference input/output. If unconnected, except for
a 0.1µF capacitor to ground for noise decoupling, the internal
1.276 Volt band-gap reference will be supplied to the three
D/A Converters. An external 1.276 Volt reference connected
to the VREF pin, will override the internal voltage reference.
Reference resistor. Connected between RREF and ground,
this resistor sets the current range of the D/A converters.
Use 390Ω for a 37.5Ω load and 780Ω for a 75Ω load.
Bypass Capacitor. A 0.1µF capacitor must be connected
between CBYPR and VDDDA to reduce noise at the D/A
outputs.
Digital CCIR 656 port input. 8 bits wide. Y, Cr, Cb
multiplexed digital input port
Digital TV Horizontal Blank input. Horizontal Blank for use
with the V656_IN ports.
Digital TV Vertical Blank input. Vertical Blank for use with
the V656_IN ports.
Digital TV Field input. Field bit for use with the V656_IN
ports.
14
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Pin
Pin
Type/Value
Name
Number
CCIR 656 Output Port
V656_OUT7-0
85,84,83,8 LVTTL output
1,80,79,77
,76
HBNK_OUT
75
LVTTL output
VBNK_OUT
73
LVTTL output
FIELD_OUT
72
LVTTL output
AHREF
69
LVTTL output
AVREF
67
LVTTL output
Serial Port
SA10/7
25
TTL input
(pull down)
SA0
26
TTL input
(pull down)
SDATA
24
SCLK
23
TTL I/0
(open drain)
TTL Input
Power and Ground
VDDPA
22
+3.3 V
VDDOSC
3
+3.3 V
33,45,56,6
6,74,82,90
10,13,16,1
8
27
4
32,38,50,6
1,70,78,86
,95
7,14
+3.3 V
VDD
VDDDA
VSSPA
VSSOSC
VSS
VSSDA
JUNE, 2000, VERSION 1.2
+3.3 V
Pin Function Description
Digital CCIR 656 port output. 8 bits wide. Y, Cr, Cb
multiplexed digital output port
Digital TV Horizontal Blank output. Horizontal Blank for
use with the V656_OUT ports.
Digital TV Vertical Blank output. Vertical Blank for use
with the V656_OUT ports.
Digital TV Field output. Field bit for use with the V656_OUT
ports.
Digital Auxiliary Horizontal Reference output. Horizontal
Sync for external hardware. Programmable advance or
retard.
Digital Auxiliary Vertical Reference output. Vertical Sync
for external hardware. Programmable advance or retard.
Serial address length select. Selects the length of the
serial address:
SA10/7 = H: 10-bits
SA10/7 = L: 7-bits
Serial data address bit 0. . Selects the serial bus address:
SA0 = H: 0x6A, 276
SA0 = L: 0x4A, 224
Serial data. Data line of the serial port. Connect to GCC
LTVDA.
Serial clock. Clock line of the serial port. Connect to GCC
LTVCL.
VGA_CKOUT Phase-locked loop Power. Filtered +3.3 volt
power for VGA_CKOUT phase locked loop.
TV Crystal Oscillator Power. Filtered +3.3 volt power for
TV XTAL oscillator.
Digital Power. 3.3 volt power for digital section of chip.
0V
0V
0V
D/A Converter Power. Filtered +3.3 volt power for 10 bit
video D/A converters.
VGA_CKOUT phase-locked loop ground.
TV Crystal Oscillator ground.
Digital ground. +3.3 volt power return.
0V
D/A Converter Ground.
15
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6. Control Register Definitions
6.1 Control Register Map
Function
Reg.
Bit #
Name
Type
Input Horizontal Offset
0
7-0
IHO7-0
R/W
1
2-0
IHO10-8
R/W
Input Vertical Offset
2
7-0
IVO7-0
R/W
3
2-0
IVO10-8
R/W
Input Horizontal Width
4
7-0
IHW 7-0
R/W
5
1-0
IHW 9-8
R/W
Vertical Scaling Coefficient
6
7-0
VSC7-0
R/W
7
7-0
VSC15-8
R/W
Horizontal Down/Up Scaling Coefficients
8
7-0
HDSC7-0
R/W (Down)
9
7-0
HUSC7-0
R/W (Up)
Command Register
C
7-0
CR7-0
R/W
D
7-0
CR15-8
R/W
Status Port
E
7-0
SP7-0
R
F
R
Numerator of NCO Low Word
10
7-0
NCON7-0
R/W
11
7-0
NCON15-8
R/W
Numerator of NCO High Word
12
7-0
NCON23-16
R/W
13
Denominator of NCO Low Word
14
7-0
NCOD7-0
R/W
15
7-0
NCOD15-8
R/W
Denominator of NCO High Word
16
7-0
NCOD23-16
R/W
17
Auxiliary Pixel Offset
18
7-0
APO7-0
R/W
19
1-0
APO9-8
R/W
Auxiliary Line Offset
1A
6-0
ALO6-0
R/W
1B
R/W
Auxiliary Field Offset
1C
0
AFO
R/W
1D
HSync Pulse Width
1E
7-0
HSOUTWID7-0 R/W
1F
2-0
HSOUTWID 10-8 R/W
JUNE, 2000, VERSION 1.2
Reset Value
00
00
00
00
D0 (720.)
02
00
00
00
00
00
10
00
00
00 (131,072.)
00
02
00 (524,288.)
00
08
00
00
00
00
00
00
00
00
16
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Function
Reg.
Bit #
Name
Type
HSync Starting Edge
20
7-0
HSOUTST7-0
R/W
21
2-0
HSOUTST10-8
R/W
HSync Ending Edge
22
7-0
HSOUTEND7-0 R/W
23
2-0
HSOUTEND10-8 R/W
Flicker Filter Sharpness
24
4-0
SHP 4-0
R/W
25
Flicker Filter
26
4-0
FLK 4-0
R/W
27
Part Revision
32
7-0
REV7-0
R/W
33
7-0
REV15-8
R/W
Misc Register
34
7-0
MISC7-0
R/W
35
7-0
MISC15-8
R/W
FIFO Status Port Full/FIFO Status Port Empty
36
7-0
FIFOF7-0
R/W
37
7-0
FIFOE7-0
R/W
FIFO Latency
38
7-0
FIFOL7-0
R/W
39
7-0
FIFOL15-8
R/W
VSync Pulse Width
3A
7-0
VSOUTWID7-0 R/W
3B
2-0
VSOUTWID 10-8 R/W
VSync Starting Edge
3C
7-0
VSOUTST7-0
R/W
3D
2-0
VSOUTST10-8
R/W
VSync Ending Edge
3E
7-0
VSOUTEND7-0 R/W
3F
2-0
VSOUTEND10-8 R/W
JUNE, 2000, VERSION 1.2
Reset Value
00
00
00
00
00
00
00
00
01
00
00
80
00
00
00
00
00
00
00
00
00
00
17
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Function
Reg.
Bit #
Name
Type
Chroma Frequency
CHR_FREQ31-24 R/W
40
7-0
CHR_FREQ23-16 R/W
41
7-0
CHR_FREQ15-8 R/W
42
7-0
CHR_FREQ7-0
43
7-0
R/W
Chroma Phase, Miscellaneous Bits 45
CHR_PHASE7-0 R/W
44
7-0
45
1,0
MISC45
R/W
Miscellaneous Bits 46, 47
46
7-0
MISC46
R/W
47
3-0
MISC47
R/W
HSync Width, Burst Width
HSYNC_WID 7-0 R/W
48
7-0
BURST_WID 6-0 R/W
49
6-0
Backporch Width, CB Burst Level
BPORCH7-0
4A
7-0
R/W
CB_BURST7-0
4B
7-0
R/W
CR Burst Level, Miscellaneous Bits 4D
CR_BURST7-0
4C
7-0
R/W
4D
1-0
MISC4D
R/W
Black Level
4E
7-0
BLACK_LVL9-2 R/W
4F
1-0
BLACK_LVL1-0 R/W
Blank Level
50
7-0
BLANK_LVL9-2 R/W
51
1-0
BLANK_LVL1-0 R/W
Number Lines
LINE_FRAME 9-2 R/W
57
7-0
LINE_FRAME 1-0 R/W
58
1-0
White Level
5E
7-0
WHITE_LVL9-2 R/W
5F
1-0
WHITE_LVL1-0 R/W
Cb Gain
60
7-0
CB_GAIN7-0
R/W
61
R/W
Cr Gain
62
7-0
CR_GAIN7-0
R/W
63
R/W
Chroma Tint Adjustment
64
R/W
65
7-0
TINT7-0
R/W
Status Port
68
R/W
69
4-0
BREEZE_WAY4-0
R/W
Status Port
6C
5-0
FRNT_PORCH5-0
R/W
6D
R/W
JUNE, 2000, VERSION 1.2
Reset Value
21 (569,408,543.)
F0
7C
1F
00
00
05
00
7E (126.)
44 (68.)
76 (118.)
3B (59.)
00
00
86 (282.)
02
3C (240.)
00
83 (525.)
01
C8 (800.)
00
22 (137.)
01
22 (137.)
01
00
00
00
16 (22.)
20 (32.)
00
18
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Function
Reg.
Bit #
Name
Type
Reset Value
ActiveLine
ACTIVELINE10-3 R/W
71
7-0
B4 (1440.)
ACTIVELINE2-0
72
2-0
R/W
00
Chroma Phase
FIRST_LINE7-0
73
7-0
R/W
15 (21.)
Miscellaneous Bits 74, Sync Level
74
7-0
MISC74
R/W
02
75
7-0
SYNC_LVL7-0 R/W
48 (72.)
VBI Blank Level
VBIBLNK_LVL9-2
7C
7-0
R/W
4A (296.)
VBIBLNK_LVL
7D
1-0
1-0
R/W
00
Reset, Encoder Version
7E
0
SOFT_RST
R/W
1
7F
7-0
ENC_VER7-0
R
20
Miscellaneous Bits 80, WSS Clock Frequency (upper)
80
6-0
MISC80
R/W
7
81
7-0
WSS_CLK 11-4 R/W
2F (759.)
WSS Clock Frequency (lower), WSS Data Field 1 (upper)
82
3-0
WSS_CLK 3-0
R/W
07
WSS_DAT1 19-12 R/W
83
7-0
00
WSS Data Field 1 (lower)
WSS_DAT1 11-4 R/W
84
7-0
00
85
3-0
WSS_DAT1 3-0 R/W
00
WSS Data Field 0 (upper)
WSS_DAT0 19-12 R/W
86
7-0
00
WSS_DAT0 11-4 R/W
87
7-0
00
WSS Data Field 0 (lower), WSS Line 1 Delay
88
3-0
WSS_DAT0 3-0 R/W
00
89
7-0
WSS_LINF17-0 R/W
00
WSS Level (lower)
8A
7-0
WSS_LINF07-0 R/W
00
8B
7-0
WSS_LVL9-2
R/W
FF (1023.)
WSS Level (upper), Miscellaneous Bits 8D
8C
1-0
WSS_LVL1-0
R/W
03
8D
4-0
MISC8D4-0
R/W
00
JUNE, 2000, VERSION 1.2
19
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2 Control Register Definitions
In the following definitions, range is defined as:
{min value : [max value]}
Please note that registers 0-3F use the little endian numbering scheme while registers 40-8D use
the big endian numbering scheme.
6.2.1 IHO - Input Horizontal Offset
Input Horizontal Offset Low (0)
7
6
5
4
3
2
1
0
IHO7
IHO6
IHO5
IHO4
IHO3
IHO2
IHO1
IHO0
Input Horizontal Offset High (1)
7
6
5
4
3
2
1
0
0
0
0
0
0
IHO10
IHO9
IHO8
Reg
Bit#
Bit Name
Description
1, 0
2-0, 7-0
IHO10-0
Input horizontal offset bits [10-0]. Horizontal displacement of the
image in pixels from the leading edge of horizontal sync. IHO is an
unsigned number.
Range: {0 : [Total Pixels/Line]-1}
6.2.2 IVO - Input Vertical Offset
Input Vertical Offset Low (2)
7
6
5
4
3
2
1
0
IVO7
IVO6
IVO5
IVO4
IVO3
IVO2
IVO1
IVO0
Input Vertical Offset High (3)
7
6
5
4
3
2
1
0
0
0
0
0
0
IVO10
IVO9
IVO8
Reg
Bit#
Bit Name
Description
3, 2
2-0, 7-0
IVO10-0
Input vertical offset bits [10:0]. Vertical displacement of the
image in lines from the leading edge of vertical sync plus a one line
bias. IVO is an unsigned number.
Range: {0 : [Total Lines/Frame]-1}
JUNE, 2000, VERSION 1.2
20
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.3 IHW - Input Horizontal Width
Input Horizontal Width Low (4)
7
6
5
4
3
2
1
0
IHW 7
IHW 6
IHW 5
IHW 4
IHW 3
IHW 2
IHW 1
IHW 0
Input Horizontal Width High (5)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
IHW 9
IHW 8
Reg
Bit#
Bit Name
Description
5, 4
1-0, 7-0
IHW 9-0
Input horizontal width [9:0]. Total number of active VGA pixels
per line. IHW is an unsigned number.
Range: {0 : 970}
6.2.4 VSC – Vertical Scaling Coefficient
Vertical Scaling Coefficient (6)
7
6
5
4
3
2
1
0
VSC7
VSC6
VSC5
VSC4
VSC3
VSC2
VSC1
VSC0
Vertical Scaling Coefficient (7)
7
6
5
4
3
2
1
0
VSC15
VSC14
VSC13
VSC12
VSC11
VSC10
VSC9
VSC8
Reg
Bit#
Bit Name
Description
7, 6
7-0
VSC7-0
Vertical scaling coefficient bits [15:0]. Vertical down scaling
factor = (1 + VSC/65,536). VSC is a two's complement number. If
VSC => 0, then the image is not effected.
Range: { [-32,769]:0}
JUNE, 2000, VERSION 1.2
21
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.5 HDSC, HUSC – Horizontal Down/Up Scaling Coefficients
Horizontal Down Coefficient (8)
7
6
5
4
3
2
1
0
HDSC7
HDSC6
HDSC5
HDSC4
HDSC3
HDSC2
HDSC1
HDSC0
Horizontal Up Coefficient (9)
7
6
5
4
3
2
1
0
HUSC7
HUSC6
HUSC5
HUSC4
HUSC3
HUSC2
HUSC1
HUSC0
Reg
Bit#
Bit Name
Description
8
7-0
HDSC7-0
Horizontal down scaling coefficient bits [7:0]. Horizontal down
scaling factor = (1 + VSC/128). HDSC is a two's complement
number. If HDSC => 0, then the image is not effected.
9
7-0
HUSC7-0
Horizontal up scaling coefficient bits [7:0]. Horizontal up
scaling factor = (1 + VSC/128). HDSC is a two's complement
number. If HDSC <= 0, then the image is not effected.
HDSC Range: { [-63]:0 }
HUSC Range: { 0:127 }
JUNE, 2000, VERSION 1.2
22
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.6 CR - Command Register
Command Register (C)
7
6
5
4
3
2
1
0
FFO_CLR
CACQ_CLR
LP_EN
YCOFF
COMPOFF
NCO_EN
CLKOFF
SRESET
Command Register (D)
7
6
5
4
3
2
1
0
UIM_MOD1
UIM_MOD0
0
UIM_DEC
UIM_CLK
OFMT
STD_VMI
NTSC_PALIN
Reg
Bit#
Bit Name
Description
C
0
SRESET
Soft Reset. Resets the FS450.
C
1
CLKOFF
Clock Off. Turns off FS450 clock to minimize power.
C
2
NCO_EN
Enable NCO Latch. When this bit is set, transfers the NCO
words from the I2C registers into the NCO. The NCO synthesizes
the VGA clock from the 27MHz FS450 clock. This clock must be
adjusted so the VGA scaled input data rate exactly matches the
CCIR 656 data output rate.
C
3
COMPOFF
Composite (CVBS) Output Off. Turns off the CVBS output D/A.
C
4
YCOFF
SVideo (YC) Outputs Off. Turns off the YC output D/As.
C
5
LP_EN
Loop Through Enable. Enables the CCIR 656 data on the output
port to loop directly to the input port (no external routing).
C
6
CACQ_CLR
Counter Acquisition Flag Clear. Setting this bit clears the
Counter Acquisition Flag.
C
7
FFO_CLR
FIFO Clear. Setting this bit clears the FIFO depth registers and
the FIFO State register.
D
0
NTSC_PALIN
CCIR 656 PAL or NTSC Input. Sets the number of lines written
through the FIFO. When set, the number of lines is 576 for PAL,
when clear, 487 lines for NTSC.
D
1
STD_VMI
Standard or VMI 656 Input Control. Select standard (external
pins) horizontal/vertical blank and field codes or inserted CCIR
601/656 SAV/EAV (Start/End Active Video) embedded codes.
D
2
OFMT
Output Format Control. Switches between RGB or
Composite/YC output. When set, the output is RGB.
D
3
UIM_CLK
Universal Interface Mux Clock Mode. If set, input pixels are
clocked in on the falling edge of the P and N input clocks. If clear,
input pixels are clocked on the rising and falling edge of N clock.
D
4
UIM_DEC
Universal Interface Mux Decimator. Turns on the horizontal
prescaler divide by 2 to support XGA mode.
D
7,6
UIM_MOD 1-0
Universal Interface Mode Select. Selects the VGA interface
mode (see table below).
JUNE, 2000, VERSION 1.2
23
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Notes:
VMI 656 Input Control: If the Video Module Interface (VMI) mode is specified, SAV and EAV commands are
inserted into the CCIR601 data stream to coordinate down stream data processing. The SAV and EAV Control
words have the following format:
YC Data
Preamble C
Preamble Y
Status Word C
Status Word Y
D7
1
0
0
1
D6
1
0
0
F
D5
1
0
0
V
D4
1
0
0
H
D3
1
0
0
P3
D2
1
0
0
P2
D1
1
0
0
P1
D0
1
0
0
P0
Table 3: SAV and EAV Control Words
F = 0 during field 1, F = 1 during field 2
H = 0 for SAV, H = 1 for EAV
V = 1 during vertical blanking
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
UIM_MOD Mapping: The UIM_MOD (Universal Input Mux, UIM) bits select the mode for P0-P11 and E0-E5. The
intention is to support as many different 3D and GCC graphic controllers, CPU support chips and integrated
CPUs as possible (collectively referred to in this data sheet as "GCC"). The following table shows the mapping
in each mode for the digital RGB from the GCC to the appropriate port or extended port pin:
UIM_MOD
0
0
1
1
1
1
2
2
3
3
3
P/E Port
M888DL
M888DH
M888IL
M888IH
M565IL
M565IH
M555L
M555H
N666
N565
N555
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
E5
E4
E3
E2
E1
E0
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
R7
R6
R5
R4
R3
R2
R1
R0
G7
G5
G4
G3
X
X
X
X
X
X
G4
G3
G2
B7
B6
B5
B4
B3
G0
B2
B1
B0
X
X
X
X
X
X
R7
R6
R5
R4
R3
G7
G6
G5
R2
R1
R0
G1
X
X
X
X
X
X
G2
G1
G0
B4
B3
B2
B1
B0
0
0
0
0
X
X
X
X
X
X
R4
R3
R2
R1
R0
G5
G4
G3
0
0
0
0
X
X
X
X
X
X
G2
G1
G0
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
R4
R3
R2
R1
R0
G4
G3
X
X
X
X
X
X
X
X
X
X
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
R4
R3
R2
R1
R0
0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
0
R4
R3
R2
R1
R0
0
G4
G3
G2
G1
G0
0
B4
B3
B2
B1
B0
0
Table 4: GCC Port Mapping (UIM_MOD)
1) All input bits are MSB justified
3) For GCC to P/E Mapping, see Table 2
JUNE, 2000, VERSION 1.2
2) Shaded modes require zero padding at input port
24
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.7 SP - Status Port
Status Port Low (E)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FIFO_ST
CACQ_ST
Status Port High (F)
Reg
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Bit#
Bit Name
Description
E
0
CACQ_ST
Cache Status. Status of horizontal downscaler cache (=1 if over
flowed).
E
1
FIFO_ST
FIFO Status. Output FIFO status (=1 if over/under flowed).
Notes:
FIFO Status:
FS450 does not have a frame memory. In FS450 the scaled input data rate and the output data rates are the
same. The FIFO takes up the slack during the asynchronous horizontal blanking interval of the input and output.
The FIFO depth (1024) is only slightly larger that the 720 output pixels required to form a CCIR 601 data stream.
The extra pixels are used for data overrun protection.
At the coincidence of a Filtered Horizontal and Vertical Start, the input and output FIFO pointers are reset to the to
beginning of the memory and data writes commence. Next, 24 output clock cycles after the Filtered Horizontal and
Vertical Start occur, the CCIR 656 Timing Generator issues a FIFO Horizontal and Vertical Start. This causes the
Horizontal Upscaler to issue a TV read and the FIFO starts to read data.
If a data overrun occurs, the offending FIFO’s pointer is halted and black is output to the Horizontal Upscaler. Also,
the FIFO data overrun flag is set.
JUNE, 2000, VERSION 1.2
25
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.8 NCON - Numerator of NCO Word
Numerator of NCO Word (10)
7
6
5
4
3
2
1
0
NCON7
NCON6
NCON5
NCON4
NCON3
NCON2
NCON1
NCON0
Numerator of NCO Word (11)
7
6
5
4
3
2
1
0
NCON15
NCON14
NCON13
NCON12
NCON11
NCON10
NCON9
NCON8
Numerator of NCO Word (12)
7
6
5
4
3
2
1
0
NCON23
NCON22
NCON21
NCON20
NCON19
NCON18
NCON17
NCON16
Numerator of NCO Word (13)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
12, 11, 10
7-0,7-0,7-0
NCON23-0
Numerator of NCO Word [23:0]. Numerator of clock synthesizer
to generate VGA input clock. NCON is a 24 bit unsigned number.
Range: {0 : NCOD/2}
The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to
the RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGA
scaled input data rate exactly matches the CCIR 656 data output rate.
Frequency VGA / Frequency 656 = # VGA Pixels / # 656 Pixels x # VGA Lines / # 656 Lines
Frequency VGA / Frequency 656 = NCON / NCOD x M / N
Example: for SVGA mode, typ. total pixels x lines ~ 1024 x 625; let M=512, N=128:
NTSC and PAL: NCON = 1024 x 625 = 640,000
JUNE, 2000, VERSION 1.2
26
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.9 NCOD - Denominator of NCO Word
Denominator of NCO Word (14)
7
6
5
4
3
2
1
0
NCOD7
NCOD6
NCOD5
NCOD4
NCOD3
NCOD2
NCOD1
NCOD0
Denominator of NCO Word (15)
7
6
5
4
3
2
1
0
NCOD15
NCOD14
NCOD13
NCOD12
NCOD11
NCOD10
NCOD9
NCOD8
Denominator of NCO Word (16)
7
6
5
4
3
2
1
0
NCOD23
NCOD22
NCOD21
NCOD20
NCOD19
NCOD18
NCOD17
NCOD16
Denominator of NCO Word (17)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
16, 15, 14
7-0,7-0,7-0
NCOD23-0
Denominator of NCO Word [23:0]. Denominator of clock
synthesizer to generate VGA input clock. NCOD is a 24 bit
unsigned number.
Range: {NCON*2 : (224-1)}
The FS450 synthesizes a 27-85 MHz clock from the 27 MHz TV_CKIN and supplies this clock
(VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to
the RGB data and Sync information. This clock has a 1.5 Hz resolution and can be adjusted so the VGA
scaled input data rate exactly matches the CCIR 656 data output rate.
Frequency VGA / Frequency 656 = # VGA Pixels / # 656 Pixels x # VGA Lines / # 656 Lines
Frequency VGA / Frequency 656 = NCON / NCOD x M / N
Example: for SVGA mode, typ. total pixels x lines ~ 1024 x 625; let M=512, N=128:
NTSC: NCOD = 858 x 525 x 512 / 128 = 1,801,800
PAL: NCOD = 864 x 625 x 512 / 128 = 2,160,000
JUNE, 2000, VERSION 1.2
27
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.10 APO, ALO, AFO - Auxiliary Pixel, Line, and Field Offsets
Auxiliary Pixel Offset Low (18)
7
6
5
4
3
2
1
0
APO7
APO6
APO5
APO4
APO3
APO2
APO1
APO0
Auxiliary Pixel Offset High (19)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
APO9
APO8
Auxiliary Line Offset (1A)
7
6
5
4
3
2
1
0
-
ALO6
ALO5
ALO4
ALO3
ALO2
ALO1
ALO0
Not Used (1B)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Auxiliary Field Offset (1C)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
AFO0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Not Used (1D)
Reg
Bit#
Bit Name
Description
19, 18
9-0
APO9-0
Auxiliary Pixel Offset [9:0]. Number of 27MHz cycles of
delay/advance of the Auxiliary Video Reference signals. APO is a
10 bit signed number.
1A
6-0
ALO6-0
Auxiliary Line Offset [6:0]. Number of lines of delay/advance of
the Auxiliary Video Reference signals. AFO is a 7 bit signed
number.
1C
0
AFO
Auxiliary Field Offset [0]. Inverts the field of the Auxiliary Video
Reference signals.
APO Range: {-512 : 511}, ALO Range: {-64 : 63}, AFO Range: {0 : 1}
JUNE, 2000, VERSION 1.2
28
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.11 HSOUTWID, HSOUTST, HSOUTEND - HSync Out Width, Starting and
Ending Edge
HSync Out Width Low (1E)
7
6
5
4
3
2
1
0
HSOUTWID7
HSOUTWID6
HSOUTWID5
HSOUTWID4
HSOUTWID3
HSOUTWID2
HSOUTWID1
HSOUTWID0
HSync Out Width High (1F)
7
6
5
4
3
2
1
0
0
0
0
0
0
HSOUTWID10
HSOUTWID9
HSOUTWID8
HSync Out Starting Edge Low (20)
7
6
5
4
3
2
1
0
HSOUTST7
HSOUTST6
HSOUTST5
HSOUTST4
HSOUTST3
HSOUTST2
HSOUTST1
HSOUTST0
HSync Out Starting Edge High (21)
7
6
5
4
3
2
1
0
0
0
0
0
0
HSOUTST10
HSOUTST9
HSOUTST8
HSync Out Ending Edge Low (22)
7
6
5
4
3
2
1
0
HSOUTEND7
HSOUTEND6
HSOUTEND5
HSOUTEND4
HSOUTEND3
HSOUTEND2
HSOUTEND1
HSOUTEND0
HSync Out Ending Edge High (23)
7
6
5
4
3
2
1
0
0
0
0
0
0
HSOUTEND10
HSOUTEND9
HSOUTEND8
Reg
Bit#
Bit Name
Description
1F, 1E
10-0
HSOUTWID10-0
HSync Out Width [10:0]. Width of HSync Out during a frame.
21, 20
10-0
HSOUTST10-0
HSync Starting Edge [10:0]. Starting edge of HSync Out during a
frame.
23, 22
10-0
HSOUTEND10-0
HSync Ending Edge [10:0]. Ending edge of HSync Out during a
frame.
Range of HSOUTWID, HSOUTST, and HSOUTEND: {0 : 2048}
JUNE, 2000, VERSION 1.2
29
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
FLT_HSTART
FLT_VSTART
TV Line
Counter
TV Field
Counter
Aux Pixel
Counter
Aux Line
Counter
Aux Field
Counter
Start and End
Comparator
TV Pixel
Counter
TV_HEND
TV_VSTART
TV_VEND
TV_FIELD
Load
Sync
Comparator
FLT_FIELD
Hysteresis
Comparator
TV_HSTART
AUX_HREF
AUX_VREF
Figure 8: CCIR 656 Timing Block Diagram
The TV and Auxiliary Pixel/Line/Field Counters are freewheeling counters that are only loaded/reloaded
during an error condition. If the value of the TV Pixel/Line/Field Counters are within 4 TV pixels of the ideal
values during a Frame Start, no adjustment to the freewheeling counters are made. However, if the values
exceeds 4 pixels (150 nsec) the ideal values, the TV Pixel/Line/Field Counters are reloaded and the TV
Counter Acquisition Flag is set.
When the TV Pixel/Line/Field Counters are reloaded, the Auxiliary Pixel/Line/Field Counters are also
reloaded. However, their load values are offset from the TV counter by the Auxiliary Pixel, Line, and Field
Offset values stored in its I2C registers (APO, ALO, and AFO). From these counters the Auxiliary
Horizontal and Vertical Syncs are formed. This feature allows a user to program advance timing signals to
compensate for external hardware processing latency when doing a mix/overlay with FS450’s CCIR 656
input and output.
The FIFO Latency register delays the Frame Start occurrence by 4x its value in 27MHz clock cycles. This
delays the output 656 timing with respect to the input VGA timing and allows the FS450’s FIFO to fill
appropriately before a FIFO read is initiated.
JUNE, 2000, VERSION 1.2
30
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
1716
HREF
276
1
1440
2
3
4
5
6
7
8
VREF
PIXEL NO. 1
PIXEL NO. 1006
263
264
265
266
267
268
269
270
VREF
PIXEL NO. 1
PIXEL NO. 154
Figure 9: Auxiliary NTSC Reference Signals
1728
HREF
288
1
1440
2
3
4
5
6
7
8
VREF
PIXEL NO. 1
313
PIXEL NO. 1006
314
315
316
317
318
319
320
VREF
PIXEL NO. 1
PIXEL NO. 134
Figure 10: Auxiliary PAL Reference Signals
JUNE, 2000, VERSION 1.2
31
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.12 SHP, FLK - Sharpness and Flicker Filter
Sharpness Low (24)
7
6
5
4
3
2
1
0
0
0
0
SHP 4
SHP 3
SHP 2
SHP 1
SHP 0
Sharpness High (25)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
24
4-0
SHP 4-0
Flicker Filter Sharpness [4-0]. SHP accentuates the joint high
vertical - high horizontal frequencies to sharpen edges. SHP is an
unsigned number.
Range: {0 : 31} Provides 0 to 31/16 (6 dB) joint high horizontal and vertical frequency boost.
Flicker Filter Coefficient Low (26)
7
6
5
4
3
2
1
0
0
0
0
FLK 4
FLK 3
FLK 2
FLK 1
FLK 0
Flicker Filter Coefficient Low (27)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
26
4-0
FLK 4-0
Flicker Filter Coefficient [4:0]. Provides weighting factor for 3
line flicker filter. FLK is an unsigned number.
Range: {0 : 23}
Notes:
The FS450 Flicker Filter is more complex than a Three Line Average (TLA) flicker filter. The FS450 flicker filter
includes a variable vertical filter response in addition to a sharpness function. Adjusting the FLK Coefficient
modifies the vertical filter from no filtering (FLK = 0) to a Three Line Average (FLK = 16), giving the user the best
choice in filtering options.
In addition to the variable vertical settings, the FS450 flicker filter has a sharpness function. This function is a two
dimensional peaking function which accentuates the joint high vertical - high horizontal spatial frequencies (an
"edge enhancer"). The three line variable two dimensional flicker filter is formed by summing the unit impulse
function with a vertical flicker function scaled by FLK (Flicker Coefficient) and the peaking function which is scaled
by SHP (Sharpness Coefficient). The FLK and SHP variables have 5 bits of resolutions, with a usable a range
from 0 to 16/16 for FLK, and 0 to 31/16 for SHP.
JUNE, 2000, VERSION 1.2
32
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.13 REV - Revision Number
Part Number (32)
7
6
5
4
3
2
1
0
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
Revision Number (33)
7
6
5
4
3
2
1
0
REV15
REV14
REV13
REV12
REV11
REV10
REV9
REV8
Reg
Bit#
Bit Name
Description
33,32
15-0
REV15-0
Revision Number [15:0]. Identifies the revision for software ID
purposes (Rev A = 0, Rev B = 1).
JUNE, 2000, VERSION 1.2
33
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.14 MISC - Miscellaneous Bits 34, 35 Register
Miscellaneous Bits Register (34)
7
6
5
4
3
2
1
0
0
0
NCO_LOAD1
NCO_LOAD0
0
0
0
0
Miscellaneous Bits Register (35)
7
6
5
4
3
2
1
0
GTLIO_PD
0
0
0
0
0
VGACKDIV
0
Reg
Bit#
Bit Name
Description
NCO_LOAD 1-0
NCO Load Control Bits. The PLL M and N dividers and the
NCO Numerator (NCON) and denominator (NCOD) share the
same address (separate memory). The NCO Load Control bits
determine which registers are loaded when the NCON and
NCOD registers are written (see table below). M uses the lower
11 bits of NCON, and N uses the lower 11 bits of NCOD.
34
5,4
35
1
VGACKDIV
VGA Clock Divide. Setting this bit divides the internal clock by
2 when the VGA input is in decimation (for XGA) mode.
35
7
GTLIO_PD
GTL I/O Power Down. Setting this bit puts all the GTL pins
into power down mode.
Notes:
NCO_LOAD
0
1
2
3
Meaning
Load NCO Numerator and Denominator only.
Load M and N PLL Dividers only.
Load NCO Numerator and Denominator and
set M=512, N=128.
Load M and N PLL Dividers and set NCO
Numerator and Denominator both to 50.
Table 5: NCO_LOAD Control Bits
1)
2)
3)
4)
5)
M is loaded with the desired value -2
N is loaded with the desired value -1
Using the 24 bit NCON and NCOD yields a very fine frequency resolution of 1.5 Hz but dithers the clock.
The speed of the clock dither is sufficiently limited by the narrowband (around 5 kHz) PLL to prevent any
problem with data transfers to the FS450. In fact, it provides an advantage for passing EMI certification
and behaves much like off the shelf dithered clocks designed specifically for that purpose.
Using the 11 bit M/N ratio gives a frequency resolution of 13 kHz, but it has no dithering. This is ideal for
dual VGA monitor and TV applications. Dithering the clock to a VGA controller makes the lines wiggle on
the connected VGA monitor, making it difficult to read. This however limits the scaling possibilities, and
close attention has to be paid to the factors of the VGA/TV pixels and lines so that they cancel down to 11
bit M and N numbers.
Both M/N and Numerator/Denominator can be used together, to generate a compromise performance.
JUNE, 2000, VERSION 1.2
34
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.15 FIFOL, FIFOH - FIFO Status Port Full/Empty
FIFO Status Port Full (36)
7
6
5
4
3
2
1
0
FFOL7
FFOL6
FFOL5
FFOL4
FFOL3
FFOL2
FFOL1
FFOL0
FIFO Status Port Empty (37)
7
6
5
4
3
2
1
0
FFOH7
FFOH6
FFOH5
FFOH4
FFOH3
FFOH2
FFOH1
FFOH0
Reg
Bit#
Bit Name
Description
36
7-0
FFOL7-0
FIFO Status Port Full [7:0]. Maximum number of FIFO memory
locations underrun during the VGA image (multiply by 4 to get
number of pixels corrupted). Unsigned number.
37
7-0
FFOH7-0
FIFO Status Port Empty [7:0]. Maximum number of FIFO
memory locations used during a VGA frame (multiply by 4 to get
number of pixels filled). Unsigned number.
Range: {0 : 255}
6.2.16 FFO_LAT - FIFO Latency
FIFO Latency Low (38)
7
6
5
4
3
2
1
0
FFO_LAT7
FFO_LAT6
FFO_LAT5
FFO_LAT4
FFO_LAT3
FFO_LAT2
FFO_LAT1
FFO_LAT0
FIFO Latency High High (39)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
38
7-0
FFO_LAT 7-0
FIFO Latency [7:0]. Number of output clock cycles between the
initiation of VGA writes to the FIFO memory and the TV reads from
it. Multiply by 4 to get the number of 27 MHz clock delays.
Range: {0 : 255}
JUNE, 2000, VERSION 1.2
35
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.17 VSOUTWID, VSOUTST, VSOUTEND - VSync Out Width, Starting and
Ending Edge
VSync Out Width Low (3A)
7
6
5
4
3
2
1
0
VSOUTWID7
VSOUTWID6
VSOUTWID5
VSOUTWID4
VSOUTWID3
VSOUTWID2
VSOUTWID1
VSOUTWID0
VSync Out Width High (3B)
7
6
5
4
3
2
1
0
0
0
0
0
0
VSOUTWID10
VSOUTWID9
VSOUTWID8
VSync Out Starting Edge Low (3C)
7
6
5
4
3
2
1
0
VSOUTST7
VSOUTST6
VSOUTST5
VSOUTST4
VSOUTST3
VSOUTST2
VSOUTST1
VSOUTST0
VSync Out Starting Edge High (3D)
7
6
5
4
3
2
1
0
0
0
0
0
0
VSOUTST10
VSOUTST9
VSOUTST8
VSync Out Ending Edge Low (3E)
7
6
5
4
3
2
1
0
VSOUTEND7
VSOUTEND6
VSOUTEND5
VSOUTEND4
VSOUTEND3
VSOUTEND2
VSOUTEND1
VSOUTEND0
VSync Out Ending Edge High (3F)
7
6
5
4
3
2
1
0
0
0
0
0
0
VSOUTEND10
VSOUTEND9
VSOUTEND8
Reg
Bit#
Bit Name
Description
3B, 3A
10-0
VSOUTWID10-0
VSync Out Width [10:0]. Width of VSync Out during a frame.
3D, 3C
10-0
VSOUTST10-0
VSync Starting Edge [10:0]. Starting edge of VSync Out during a
frame.
3F, 3E
10-0
VSOUTEND10-0
VSync Ending Edge [10:0]. Ending edge of VSync Out during a
frame.
Range of VSOUTWID, VSOUTST, and VSOUTEND: {0 : 2048}
JUNE, 2000, VERSION 1.2
36
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.18 CHR_FREQ - Chroma Subcarrier Frequency
CHR_FREQ (40)
7
6
5
4
3
2
1
0
CHR_FREQ31
CHR_FREQ30
CHR_FREQ29
CHR_FREQ28
CHR_FREQ27
CHR_FREQ26
CHR_FREQ25
CHR_FREQ24
CHR_FREQ (41)
7
6
5
4
3
2
1
0
CHR_FREQ15
CHR_FREQ14
CHR_FREQ13
CHR_FREQ12
CHR_FREQ11
CHR_FREQ10
CHR_FREQ9
CHR_FREQ8
CHR_FREQ (42)
7
6
5
4
3
2
1
0
CHR_FREQ15
CHR_FREQ14
CHR_FREQ13
CHR_FREQ12
CHR_FREQ11
CHR_FREQ10
CHR_FREQ9
CHR_FREQ8
CHR_FREQ (43)
7
6
5
4
3
2
1
0
CHR_FREQ7
CHR_FREQ6
CHR_FREQ5
CHR_FREQ4
CHR_FREQ3
CHR_FREQ2
CHR_FREQ1
CHR_FREQ0
Reg
Bit#
Bit Name
Description
40,41,42,43
all
CHR_FREQ31-0
Chroma Subcarrier Frequency. Sets the subcarrier
frequency, = subcarrier/27,000,000*2^32..
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.19 Chroma Phase, Miscellaneous Bits 45
Chroma Phase (44)
7
6
5
4
3
2
1
0
CHR_PHASE7
CHR_PHASE6
CHR_PHASE5
CHR_PHASE4
CHR_PHASE3
CHR_PHASE2
CHR_PHASE1
CHR_PHASE0
Miscellaneous Bit Register 45 (45)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CLRBAR
BYPYCLP
Reg
Bit#
Bit Name
Description
44
7-0
CHR_PHASE7-0
Pre-set Subcarrier Phase [7:0]. Value for pre-set subcarrier
phase (only upper 8 bit programmable, lower 24 bits =0).
45
0
BYPYCLP
Bypass Y Clamp. Allows for non-standard range of Luma on Yinputs. 0=Luma expected range [16:235], and clamped to this
range. 1=Luma expected in range [0:255] and no clamping is
performed.
45
1
CLRBAR
Color Bar Mode. Causes the YC inputs in the encoder to be
ignored and forces a color bar pattern onto the input. The color bar
pattern is a repeating sequence of 8 colors at 75% amplitude and
100% saturation.
JUNE, 2000, VERSION 1.2
38
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.20 Miscellaneous Bits Registers 46 and 47
Miscellaneous Bits Register 46
7
6
5
4
3
2
1
0
RGB_SETUP
RGB_SYNC2
RGB_SYNC1
RGB_SYNC0
YC_DELAY2
YC_DELAY1
YC_DELAY0
CVBS_EN
Miscellaneous Bits Register 47
7
6
5
4
3
2
1
0
0
0
0
0
CHR_BW1
COMP_YUV
COMP_GAIN1
COMP_GAIN0
Reg
Bit#
Bit Name
Description
46
0
CVBS_EN
CVBS Enable. Enables composite and luma outputs.
46
3-1
YC_DELAY2-0
YC Delay. Relative pipeline delay between luma and chroma
outputs (4=0 clock; 0=luma lags chroma by 4 clocks; 7=chroma
lags luma by 3 clocks).
46
6-4
RGB_SYNC2-0
RGB Sync. Provide sync to RGB components: [2]=1, sync on
red; [1]=1, sync on green; [0]=1, sync on blue.
46
7
RGB_SETUP
RGB Setup. Provide black level (0) or blank level (1) setup for
RGB outputs..
47
1-0
COMP_GAIN1-0
Composite Chroma Gain. Percentage of chroma used in
composite output: 00=100%, 01=25%, 10=50%, 11=75%.
47
2
COMP_YUV
Component YUV. Enables bypass on the RGB inputs sending
component data YUV through.
47
3
CHR_BW1
Chroma Filter Bandwidth Control. 00=narrow, 01=wide,
10=extra wide, 11=ultra wide (see Miscellaneous Bit Register 74
for bit 0).
JUNE, 2000, VERSION 1.2
39
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.21 HSync Width (48), Burst Width (49)
HSync Width (48)
7
6
5
4
3
2
1
0
HSYNC_WID7
HSYNC_WID6
HSYNC_WID5
HSYNC_WID4
HSYNC_WID3
HSYNC_WID2
HSYNC_WID1
HSYNC_WID0
Burst Width (49)
7
6
5
4
3
2
1
0
-
BURST_WID6
BURST_WID5
BURST_WID4
BURST_WID3
BURST_WID2
BURST_WID1
BURST_WID0
Reg
Bit#
Bit Name
Description
48
7-0
HSYNC_WID7-0
HSync Width. Width of HSync in 27MHz clocks (LSB bit 0 is
tied to zero).
49
6-0
BURST_WID6-0
Burst Width. Width of the burst in 27MHz clocks.
6.2.22 Back Porch Width (4A), Cb Burst Amplitude (4B)
Back Porch Width (4A)
7
6
5
4
3
2
1
0
BPORCH7
BPORCH6
BPORCH5
BPORCH4
BPORCH3
BPORCH2
BPORCH1
BPORCH0
4
3
2
1
0
Cb Burst Amplitude (4B)
7
6
5
CB_BURST7 CB_BURST6 CB_BURST5 CB_BURST4 CB_BURST3 CB_BURST2 CB_BURST1 CB_BURST0
Reg
Bit#
Bit Name
Description
4A
7-0
BPORCH7-0
Back Porch Width. Width of the back porch in 27MHz clocks
(LSB bit 0 is tied to zero).
4B
7-0
CB_BURST7-0
Cb Burst Amplitude Setting. Range {-127:127}
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.23 Cr Burst Amplitude (4C), Miscellaneous Bits Register 4D
Cr Burst Amplitude (4C)
7
6
5
4
3
2
1
0
CR_BURST7
CR_BURST6
CR_BURST5
CR_BURST4
CR_BURST3
CR_BURST2
CR_BURST1
CR_BURST0
Miscellaneous Bits Register 4D
7
6
5
4
3
2
1
0
0
0
0
0
0
0
SLV_THRS
SLV_MOD
Reg
Bit#
Bit Name
Description
4C
7-0
CR_BURST7-0
Cr Burst Amplitude Setting. Range {-127:127}
4D
0
SLV_MOD
Slave Mode. Enable bit for Full Slave Mode timing. This does
not enable Partial Save Mode and should be cleared unless Full
Slave Mode operation is required.
4D
1
SLV_THRS
Slave Mode Threshold. Controls the threshold at which the
encoder begins the horizontal line adjustments (0=0 line, 1=30
line).
6.2.24 Black Level (4E)
Black Level (4E)
7
6
5
4
3
2
1
0
BLACK_LVL9
BLACK_LVL8
BLACK_LVL7
BLACK_LVL6
BLACK_LVL5
BLACK_LVL4
BLACK_LVL3
BLACK_LVL2
Black Level (4F)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BLACK_LVL1
BLACK_LVL0
Reg
Bit#
Bit Name
Description
4E, 4F
7-0, 1-0
BLACK_LVL9-0
Black Level. Used to create a setup.
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.25 Blank Level (50)
Blank Level (50)
7
6
5
4
3
2
1
0
BLANK_LVL9
BLANK_LVL8
BLANK_LVL7
BLANK_LVL6
BLANK_LVL5
BLANK_LVL4
BLANK_LVL3
BLANK_LVL2
Blank Level (51)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BLANK_LVL1
BLANK_LVL0
Reg
Bit#
Bit Name
Description
50, 51
7-0, 1-0
BLANK_LVL9-0
Blanking Level. Blanking level during non VBI.
6.2.26 Number of Lines (57-58)
Unused (56)
Number of Lines (57)
7
6
5
4
3
2
1
0
NUM_LINES9
NUM_LINES 8
NUM_LINES7
NUM_LINES6
NUM_LINES5
NUM_LINES4
NUM_LINES3
NUM_LINES2
Number of Lines (58)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
NUM_LINES1
NUM_LINES 0
Unused (59)
Reg
Bit#
Bit Name
Description
57, 58
7-0, 1-0
NUM_LINES9-0
Number of Lines. Number of lines in a frame. Note that an odd
number implies an interlaced image and an even number implies
a progressive image.
JUNE, 2000, VERSION 1.2
42
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.27 White Level (5E)
White Level (5E)
7
6
5
4
3
2
1
0
WHITE_LVL9
WHITE_LVL8
WHITE_LVL7
WHITE_LVL6
WHITE_LVL5
WHITE_LVL4
WHITE_LVL3
WHITE_LVL2
White Level (5F)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
WHITE_LVL1
WHITE_LVL0
Reg
Bit#
Bit Name
Description
5E, 5F
7-0, 1-0
WHITE_LVL9-0
White Level.
6.2.28 Cb Color Saturation (60)
Cb Color Saturation (60)
7
6
5
4
3
2
1
0
CB_GAIN7
CB_GAIN6
CB_GAIN5
CB_GAIN4
CB_GAIN3
CB_GAIN2
CB_GAIN1
CB_GAIN0
Unused (61)
Reg
Bit#
Bit Name
Description
60
7-0
CB_GAIN7-0
Cb Color Saturation Control. (1 LSB = 1/128).
6.2.29 Cr Color Saturation (62)
Cb Color Saturation (60)
7
6
5
4
3
2
1
0
CR_GAIN7
CR_GAIN6
CR_GAIN5
CR_GAIN4
CR_GAIN3
CR_GAIN2
CR_GAIN1
CR_GAIN0
Unused (63)
Reg
Bit#
Bit Name
Description
62
7-0
CR_GAIN7-0
Cr Color Saturation Control. (1 LSB = 1/128).
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.30 Tint (65)
Unused (64)
Tint (65)
7
6
5
4
3
2
1
0
TINT7
TINT6
TINT5
TINT4
TINT3
TINT2
TINT1
TINT0
Reg
Bit#
Bit Name
Description
65
7-0
TINT7-0
Tint Adjustment on Chroma.
6.2.31 Width of Breezeway (69)
Unused (68)
Width of Breezeway (69)
7
6
5
4
3
2
1
0
0
0
0
BR_WAY4
BR_WAY3
BR_WAY2
BR_WAY1
BR_WAY0
Reg
Bit#
Bit Name
Description
69
4-0
BR_WAY4-0
Width of Breezeway. In 27MHz clocks.
6.2.32 Front Porch (6C)
Front Porch (6C)
7
6
5
4
3
2
1
0
0
0
FR_PORCH5
FR_PORCH4
FR_PORCH3
FR_PORCH2
FR_PORCH1
FR_PORCH0
Unused (6D)
Reg
Bit#
Bit Name
Description
6C
5-0
FR_PORCH5-0
Front Porch. Width of front porch in 27MHz clocks (LSB bit 0
tied to zero).
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.33 Active Video Line (71-72), First Video Line (73)
Unused (70)
Active Video Line (71)
7
6
5
4
3
2
1
0
ACT_LINE10
ACT_LINE 9
ACT_LINE 8
ACT_LINE 7
ACT_LINE 6
ACT_LINE 5
ACT_LINE 4
ACT_LINE 3
Active Video Line (72)
7
6
5
4
3
2
1
0
0
0
0
0
0
ACT_LINE 2
ACT_LINE 1
ACT_LINE 0
First Video Line (73)
7
6
5
4
3
2
1
0
1ST_LINE 7
1ST_LINE 6
1ST_LINE 5
1ST_LINE 4
1ST_LINE 3
1ST_LINE 2
1ST_LINE 1
1ST_LINE 0
Reg
Bit#
Bit Name
Description
71, 72
7-0, 2-0
ACT_LINE10-0
Active Video Line. Number of 27MHz clocks in active video line
(1440 setting refers to 720 of luma pixels and 720 chroma (Cb
and Cr) pixels; the LSB bits [1:0] are tied to zero).
73
7-0
1ST_LINE 7-0
First Line of Video. Line number for the first line of video in a
field.
JUNE, 2000, VERSION 1.2
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PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.34 Miscellaneous Bits 74, Sync Level (75)
Miscellaneous Bit Register 74
7
6
5
4
3
2
1
0
UV_ORDER
PAL_MODE
CHR_BW0
INVERT_TOP
SYS625_50
CPHASE1
CPHASE0
VSYNC5
Sync Level (75)
7
6
5
4
3
2
1
0
SYNC_LVL 7
SYNC_LVL 6
SYNC_LVL 5
SYNC_LVL 4
SYNC_LVL 3
SYNC_LVL 2
SYNC_LVL 1
SYNC_LVL 0
Reg
Bit#
Bit Name
Description
74
0
VSYNC5
VSync Equalization Pulses. 0=6 and 1=5 VSync equalization
and broad pulses.
74
2-1
CPHASE1-0
Resetting Period of Carrier Clock. 0=every 8 fields, 1=every 4
fields, 2=every other line, 3=once before any chroma burst and then
never reset again.
74
3
SYS625_50
System Field Format. 0=525 lines and 59.94 fields/sec system;
1=625 lines and 50 fields/sec system..
74
4
INVERT_TOP
Invert Field ID Polarity. Inverts the polarity of the encoder's field
identification signal.
74
5
CHR_BW0
Chroma Filter Bandwidth Control. 00=narrow, 01=wide,
10=extra wide, 11=ultra wide (see Miscellaneous Bit Register 47
for bit 1).
74
6
PAL_MODE
PAL or NTSC Mode. 0=NTSC, 1=PAL.
74
7
UV_ORDER
UV Order. Switches ordering of Cb and Cr inputs.
75
7-0
SYNC_LVL7-0
Sync Level. Sync level during non-VBI lines.
JUNE, 2000, VERSION 1.2
46
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.35 VBI Blank Level (7C)
VBI Blank Level (7C)
7
6
5
4
3
2
1
0
VBIBL_LVL 9
VBIBL_LVL 8
VBIBL_LVL 7
VBIBL_LVL 6
VBIBL_LVL 5
VBIBL_LVL 4
VBIBL_LVL 3
VBIBL_LVL 2
VBI Blank Level (7D)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
VBIBL_LVL 1
VBIBL_LVL 0
Reg
Bit#
Bit Name
Description
7C, 7D
7-0, 1-0
VBIBL_LVL 9-0
VBI Blanking Level. Blanking level during VBI lines.
6.2.36 SOFT_RST, ENC_VER - Encoder Soft Reset, Encoder Version
Encoder Soft Reset (7E)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SOFT_RST
Encoder Version Number (7F)
7
6
5
4
3
2
1
0
ENC_VER7
ENC_VER6
ENC_VER5
ENC_VER4
ENC_VER3
ENC_VER2
ENC_VER1
ENC_VER0
Reg
Bit#
Bit Name
Description
7E
0
SOFT_RST
Encoder Soft Reset. Writing to this bit resets the video encoder.
7F
7-0
ENC_VER7-0
Encoder Version Number. Contains the version of the encoder.
This is a read-only register.
JUNE, 2000, VERSION 1.2
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COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.37 Misc. Bit Reg. 80, WSS Clock (81-82), WSS Data F1(83-85)
Miscellaneous Bit Register 80
7
6
5
4
3
2
1
0
0
WSS_F1EN
WSSF0_EN
WSS_TYPE
WSS_CLKBY
WSS_EDGE1
WSS_EDGE0
0
WSS Clock (81)
7
6
5
4
3
2
1
0
WSS_CLK11
WSS_CLK10
WSS_CLK9
WSS_CLK8
WSS_CLK7
WSS_CLK6
WSS_CLK5
WSS_CLK4
WSS Clock (82)
7
6
5
4
3
2
1
0
0
0
0
0
WSS_CLK3
WSS_CLK2
WSS_CLK1
WSS_CLK0
WSS Data Field 1 (83)
7
6
5
4
3
2
1
0
WSS_DATF019
WSS_DATF018
WSS_DATF017
WSS_DATF016
WSS_DATF015
WSS_DATF014
WSS_DATF013
WSS_DATF012
WSS Data Field 1 (84)
7
6
5
4
3
2
1
0
WSS_DATF011
WSS_DATF010
WSS_DATF09
WSS_DATF08
WSS_DATF0 7
WSS_DATF0 6
WSS_DATF0 5
WSS_DATF0 4
WSS Data Field 1 (85)
7
6
5
4
3
2
1
0
0
0
0
0
WSS_DATF0 3
WSS_DATF0 2
WSS_DATF0 1
WSS_DATF0 0
Reg
Bit#
Bit Name
Description
80
2-1
WSS_EDGE1-0
WSS Edge Rate Control. Edge rates are proportional to the
frequency of the WSS clock, but can also be scaled by the
WSS_EDGE parameter. Higher numbers indicate faster rise
and fall times on the WSS pulses.
80
3
WSS_CLKBY
WSS Clock Bypass. Typically this is set=1 in NTSC and 0 in
PAL. =1 Causes the chroma clock to be used as the WSS
clock, =0 forces the local 12-bit WSS clock to be used.
80
4
WSS_TYPE
WSS Type. 1=PAL, ITU-R BT.1119-2, 0=NTSC, EIAJ CPR1204
80
5
WSSF0_EN
WSS Field 0 Enable. Enables WSS signal in Field 0.
80
6
WSSF1_EN
WSS Field 1 Enable. Enables WSS signal in Field 1.
81, 82
7-0, 3-0
WSS_CLK11-0
WSS Clock Frequency. Calculated from:
WSS Clock Frequency / Encoder Clock Frequency.
83,84,85
7-0,7-0,3-0
WSS_DATAF1 19-0
WSS Data for Field 1. A waveform only appears when
WSSF1_EN=1.
JUNE, 2000, VERSION 1.2
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PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.38 WSS Data Field 0(86-88), WSS Line Number Field 1 (89)
WSS Data Field 0 (86)
7
6
5
4
3
2
1
0
WSS_DATF019
WSS_DATF018
WSS_DATF017
WSS_DATF016
WSS_DATF015
WSS_DATF014
WSS_DATF013
WSS_DATF012
WSS Data Field 0 (87)
7
6
5
4
3
2
1
0
WSS_DATF011
WSS_DATF010
WSS_DATF09
WSS_DATF08
WSS_DATF0 7
WSS_DATF0 6
WSS_DATF0 5
WSS_DATF0 4
WSS Data Field 0 (88)
7
6
5
4
3
2
1
0
0
0
0
0
WSS_DATF0 3
WSS_DATF0 2
WSS_DATF0 1
WSS_DATF0 0
4
3
2
1
0
WSS Line Number Field 1 (89)
7
6
5
WSS_LNF1 7 WSS_LNF1 6 WSS_LNF1 5 WSS_LNF1 4 WSS_LNF1 3 WSS_LNF1 2 WSS_LNF1 1 WSS_LNF1 0
Reg
Bit#
Bit Name
Description
86,87,88
7-0,7-0,3-0
WSS_DATAF0 19-0
WSS Data for Field 0. A waveform only appears when
WSSF0_EN=1.
89
7-0
WSS_LINEF1 7-0
Field 1 WSS Line. Line number (relative to the previous
VSync) at which the WSS data will appear in Field 1.
JUNE, 2000, VERSION 1.2
49
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
6.2.39 WSS Field 0 Line Number, WSS Level, Misc. Bits Reg. 8D (8A-8D)
WSS Field 0 Line Number (8A)
7
6
5
4
3
2
1
0
WSS_LNF0 7 WSS_LNF0 6 WSS_LNF0 5 WSS_LNF0 4 WSS_LNF0 3 WSS_LNF0 2 WSS_LNF0 1 WSS_LNF0 0
WSS Level (8B)
7
6
5
4
3
2
1
0
WSS_LVL9
WSS_LVL8
WSS_LVL7
WSS_LVL6
WSS_LVL5
WSS_LVL4
WSS_LVL3
WSS_LVL2
WSS Level (8C)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
WSS_LVL1
WSS_LVL0
Miscellaneous Bits Register 8D
7
6
5
4
3
2
1
0
0
0
0
NOTCH_EN
NOTCH_WD
NOTCH_FRQ2
NOTCH_FRQ1
NOTCH_FRQ0
Reg
Bit#
Bit Name
Description
8A
7-0
WSS_LNF07-0
Field 0 WSS Line. Line number (relative to the previous
VSync) at which the WSS data will appear in Field 0.
8B, 8A
7-0, 1-0
WSS_LVL9-0
WSS High Level. WSS waveform will rise from VBIBL_LVL to
WSS_LVL in a 0 to 1 transition.
8D
2-0
NOTCH_FRQ2-0 Notch Frequency. Selects from 8 possible frequencies around
which the notch will be centered (see table below).
8D
3
NOTCH_WD
Notch Filter Wide Bandwidth. 1=wide, 0=narrow.
8D
4
NOTCH_EN
Notch Filter Enable. 1=On, 0=Off.
NOTCH_FRQ
Description
0
1
2
CCIR 601 NTSC
3
4
5
SQ Pixel NTSC
SQ Pixel PAL
CCIR 601 PAL
6
7
Notch Y Value
1 + 1/8 + 1/16
1 + 1/8 + 1/64
1 + 1/8 + 1/16 (wide)
1 (narrow)
1 - 1/128
1 - 1/32 - 1/64
1 - 1/8 - 1/32 -1/128 (wide)
1 - 1/4 + 1/32 -1/128 (narrow)
1 - 1/8 - 1/16 - 1/32
1 - 1/4 - 1/32
Notch Y Value
1.1875
1.1406
1.0938
1.0000
0.9922
0.9531
0.8359
0.7734
0.7813
0.7188
Table 6: NOTCH_FRQ Values
JUNE, 2000, VERSION 1.2
50
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
Hex
Indx Register
40
44
74
60
62
4C
4B
74
74
74
48
49
4A
6C
69
71
50
7C
4E
5E
75
57
Combinatio
CHR_FREQ
CHR_PHASE
CPHASE
CR_GAIN
CB_GAIN
CR_BURST
CB_BURST
SYS625_50
VSYNC5
PAL_MODE
HSYNC_WID
BURST_WID
BPORCH
FRNT_PORCH
BREEZE_WAY
ACTIVELINE
BLANK_LVL
WSS_LVL
BLACK_LVL
WHITE_LVL
SYNC_LVL
LINE_FRAME
n
NTSC
PAL
PAL-M
PAL-N
0x21f07c1f
0x2a098acb
0x21e6efe3
0x2a098acb
0x21f69446
0
2
137
137
0
59
0
0
0
126
68
118
32
22
1440
240
240
282
800
16
525
0
0
145
145
31
44
1
1
1
126
64
138
24
26
1440
251
251
251
800
16
625
0
0
137
137
29
41
0
0
1
126
68
118
32
18
1440
240
240
282
800
16
525
0
0
137
137
29
41
1
0
1
126
64
138
24
26
1440
240
240
282
800
16
625
0
0
145
145
31
44
1
1
1
126
68
138
24
26
1440
251
251
251
800
16
625
PAL-N
Table 7: Typical Register Values for Various Standards
JUNE, 2000, VERSION 1.2
51
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
7. Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS450 in a
product. The following guidelines will help insure that your design yields the best possible results.
7.1 Pixel Phase Lock Loop
•
The analog supply for the Pixel PLL should always be clean and noise free to insure minimum jitter in
the PLL. Do not power other circuitry from the PLL supply.
•
The supply line VDDPA should be decoupled with a series resistor of 150W and a 4.7µF tantalum
capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100µF. Always have a 1000pF to 0.1µF
capacitor to remove high frequency noise.
•
Use a solid ground plane under the FS450.
7.2 Video Output Filters
•
To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75W
termination resistors and the first capacitor of the output filter close to the video output pins of the
FS450.
7.3 Analog Power Supply Bypassing, Filtering, and Isolation
•
When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator.
Switching power supply noise, and noise from the digital plane can induce visible artifacts into the
displayed video. Always provide sufficient filtering and high frequency bypassing to insure that power
supply noise is minimized for visual as well as EMI reasons.
•
It is recommended that each power supply section be isolated with a ferrite bead and a 4.7µF capacitor.
Where the power pins are so close together that the 0.1µF bypass capacitors are adjacent, consider
changing one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on the
power supply.
7.4 Power and Ground
•
Within the FS450, separate power is routed to functional sections: phase locked loop, D/A converters,
digital processors and digital drivers. All ground pins should be connected to a common ground plane.
Power pins should be segregated into analog and digital sections.
•
Clean analog power should be applied to the VDDPA, VDDOSC , and VDDDA pins. A 0.1 µF capacitor should
be placed adjacent to each group of pins. The capacitor connected to CBYPASS is critical, and it must be
connected to VDDDA to minimize noise at the D/A converter outputs. Chip capacitors are recommended.
•
Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in series
with the supply trace. A 47 µF capacitor should be placed across the common +3.3 VDC for VDD and
VDDDA to act as a reservoir for heavy currents drawn by D/A converters and internal memories. At least
one 0.1 µF capacitor should be located adjacent to VDD pins along each side of the FS450 to supply
transient currents.
JUNE, 2000, VERSION 1.2
52
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
7.5 Interfacing to the FS450 in a Mixed Voltage Environment
As many devices designed today, the FS450 is powered by +3.3 Volts. However, 5 Volt devices are still
very common today and will continue to be used for some time in the future. To meet this interface
requirement the FS450 has 5 Volt tolerant inputs.
7.5.1 Interfacing to the SIO bus.
The SIO bus was developed previous to 3.3V logic processes. The SIO bus input voltage specification is 1.5
Volts for VIL and 3.0 Volts for VIH. The FS450 is built on a 3.3 Volt process and has 5 Volt tolerant inputs
with a VIL of 0.8 Volts and a VIH of 2.0 Volts.
For most applications this voltage difference is not an issue as the output drive low specification (V OL) of the
SIO bus and the FS450 are both 0.4 Volts. However, in heavily loaded SIO busses the output VOL is not
always preserved.
An easy way to regain the 0.7 Volt difference in the VIL specification of the FS450 and the SIO bus is to bias
the FS450’s input negative by a diode drop (D1). The diode can be biased by a long-tail resistor pair or a
current source pair. Shown below is the long-tail pair:
+12V
R1
22K
To
I2C
D1
To
FS450
R2
27K
-12V
Figure 11. SIO Translation Using Long-tail Resistors
D1 = 1N4148
The long-tail pair is a simple circuit but has the disadvantage of requiring higher voltage power supplies.
Also, these supplies may have to powered up in a specific sequence so the surround circuits are not overvoltage.
The translation circuit below requires only one 5 Volt power supply and has no special sequence
requirements. In addition, the circuit offers a high impedance load (Q1 become reverse biased) to the SIO
bus when its power supply is removed. Unfortunately, it requires more parts. In applications where
transistors are more readily available, R2 and R3 can be replaced with diode connected transistors.
JUNE, 2000, VERSION 1.2
53
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
+5V
R1
2.9K
Q1
R2
1.3K
To
I2C
D1
To
FS450
R3
1.2K
Q2
Figure 12. SIO Translation Using Current Mirrors
D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904
For applications with more than one supply, combinations of the above two circuits can be used. However,
the simplest approach to this problem is to limit the loading on the SIO bus when possible. When this is
not possible, some of the SIO passive loads can be replaced with active ones. This will increase the SIO
access speed without increasing the SIO output low drive current.
JUNE, 2000, VERSION 1.2
54
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
8. Specifications
8.1 Absolute Maximum and Recommended Ratings
(beyond which the device may be damaged)1
Parameter
Power Supply Voltages
VDD (Measured to VSS)
VDDAD (Measured to VSSAD)
VDDPA and VDDPF (Measured to VSSPA and VSSPF)
VDDDA (Measured to VSSDA )
VSSAD, VSSPA, VSS, VSSPA, VSSDA (delta)
Digital Inputs
3.3 V logic applied voltage (Measured to VSS)2
Forced current 3, 4
Analog Inputs
Applied Voltage (Measured to VSSAD)2
Forced current 3, 4
Digital Outputs
3.3 V logic applied voltage (Measured to VSS)2
Forced current 3, 4
Short circuit duration (single output in HIGH state to
ground)
Temperature
Operating, Ambient (RL=37.5Ω)
Operating, Ambient (RL=75Ω)
Junction
Thermal Resistance Junction to Ambient (typical), ØJA
Thermal Resistance Junction to Case (typical), ØJC
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)1
Storage1
Electrostatic
Electrostatic Discharge5
Min
Rec.
Max
Unit
-0.3
-0.3
-0.3
-0.3
-0.3
3.0-3.6
3.0-3.6
3.0-3.6
3.0-3.6
3.8
3.8
3.8
3.8
0.3
V
V
V
V
V
-0.3
-10.0
0-V DD
VDD + 0.3
10.0
V
mA
-0.3
-10.0
0-V DD
VDDDA + 0.3
10.0
V
mA
-0.3
-6.0
0-V DD
VDD + 0.3
6.0
1
V
mA
second
65
70
125
56
5
300
220
125
°C
°C
°C
°C/W
°C/W
°C
°C
°C
±150
V
0
0
-40
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
JUNE, 2000, VERSION 1.2
55
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
8.2 Electrical Characteristics
Parameter
Power Supply Currents
IDD3
3.3 volt Digital current
IDDDA
3.3 volt Analog current
IDDDA
3.3 volt Analog DAC current
IDDOSC
3.3 volt Crystal Oscillator current
IDDDPA
3.3 volt VGA PLL current
IDDT
3.3 volt Total Current
LVTTL Inputs and Outputs
CI
Input Capacitance
CO
Output Capacitance
IIH
Input Current, HIGH
IIL
Input Current, LOW
IILP
Input Current, LOW with pull-up
VIH
VIL
IOH
IOL
VOH
VOL
GTL Inputs
CI
CO
IIH
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Output Current, Logic HIGH
Output Current, Logic LOW
Output Voltage, HIGH
Output Voltage, LOW
and Outputs
Input Capacitance
Output Capacitance
Input Current, HIGH
IIL
Input Current, LOW
VIH
VIL
VREF
IOH
IOL
VOL
Analog
VIREF
VOC
ROUT
COUT
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Voltage Reference Range
Output Current, Logic HIGH1
Output Current, Logic LOW 1
Output Voltage, LOW
DAC Current Reference Voltage
Video Output Compliance
Video Output Resistance
Video Output Capacitance
JUNE, 2000, VERSION 1.2
Conditions
Min
VGA Core
Clock=50MHz
RL=37.5Ω
RL=75Ω
VDD3 = 3.3 ± 0.3V,
VIN = max.
VDD3 = 3.3 ± 0.3V,
VIN = 0 V
VDD3 = 3.3 ± 0.3V,
VIN = 0 V
Typ
Max
165
mA
85
45
15
5
270
105
5
5
10
10
±10
pF
pF
µA
±10
µA
-10
µA
-60
0.4
V
V
mA
mA
V
V
8
8
±10
pF
pF
µA
±10
µA
VREF-.2
TBD
-10
45.0
0.34
V
V
V
µA
mA
V
0.8
-4.0
4.0
2.4
4
4
VDD3 = 3.3 ± 0.3V,
VIN = max.
VDD3 = 3.3 ± 0.3V,
VIN = 0 V
VREF+.2
IOL = 45mA
COUT = 0 mA,
Freq. = 1 MHz
56
TBD
0.9
0.12
0.20
1.15
-0.4
1.276
15
20
mA
mA
mA
2.0
IOH = -4mA
IOL = 4mA
Unit
1.40
2
V
V
KΩ
pF
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
8.3 Switching Characteristics
Parameter
Clocks
fCKIN
TV Encoder Reference Clock Frequency
fXTOL
TV Reference Clock Frequency Tolerance
tPWHT TV Reference Clock Pulse Width, HIGH
tPWLT TV Reference Clock Pulse Width, LOW
fPCKIN VGA Clock Positive Edge Frequency
fNCKIN VGA Clock Negative Edge Frequency
fCORE
VGA Core Frequency4
fVCKO
VGA Clock Output
tJIT-VCK VGA Clock Output Jitter (peak-to-peak)
fPLLREF PLL Reference Clock Frequency
M
PLL Numerator
tPWHV VGA Clock Positive Edge Pulse Width, HIGH
tPWLV VGA Clock Negative Edge Pulse Width, LOW
Reset
Assert fCKIN cycles on RESET\ to reset the part
Digital RGB Input Port
tPDH
VGA_PCKIN to Data Hold Time
tNDH
VGA_NCKIN to Data Hold Time
tPSU
VGA_PCKIN to Data Setup Time
tNSU
VGA_NCKIN to Data Setup Time
CCIR 656 Video Input and Output Port
tTDH
TV_CKIN to Data Hold Time
tTSU
TV_CKIN to Data Setup Time
tTDO
TV_CKIN to Data Out Delay
Serial Microprocessor Interface
tDAL
SCL Pulse Width, LOW
tDAH
SCL Pulse Width, HIGH
tSTAH
SDA Start Hold Time
tSTASU SCL to SDA Setup Time (Stop)
tSTOSU SCL to SDA Setup Time (Start)
tBUFF
SDA Stop Hold Time Setup
tDSU
SDA to SCL Data Setup Time
tDHO
SDA to SCL Data Hold Time
Conditions
40/60 duty cycle
40/60 duty cycle
Min
Typ2
Max
27.0
30
503
15.0
15.0
27.0
27.0
85.0
85.0
50.0
85.0
200
100
1200
27.0
over a cycle
24
500
5.0
5.0
16
0
0
1.5
1.5
ns
ns
ns
ns
0
10.0
ns
ns
ns
24.0
1.3
0.6
0.6
0.6
0.6
1.3
300
300
GTL outputs are open drain, intended to drive 31 ohm termination from 1.8 volts.
Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C
TV subcarrier acceptance band is ± 300 Hz.
VGA Core Frequency = VGA Clock Frequency/(UIM_DEC+1)
JUNE, 2000, VERSION 1.2
57
MHz
ppm
ns
ns
MHz
MHz
MHz
MHz
ps
kHz
Clocks
Notes:
1.
2.
3.
4.
Unit
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
µs
µs
µs
µs
µs
µs
ns
ns
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
9. Mechanical Dimensions
9.1 100-Lead PQFP (KH) Package
Symbol
Inches
Min.
A
A1
A2
B
C
D
D1
E
E1
e
L
N
ND
NE
α
ccc
Millimeters
Max.
100
30
20
Min.
Notes
Max.
3.00
0.05
2.55
2.75
0.25
0.40
0.10
0.25
23.60 24.20
19.80 20.20
17.30 18.20
13.80 14.20
0.65 BSC
0.60
1.00
100
30
20
0
8°
-
3,5
5
4
Notes:
1. All dimensions and tolerances
conform to ANSI Y14.5M-1982.
2. Controlling Dimension is millimeters
3. Dimension “B” does not include
dambar protrusion. Allowable
dambar protrusion shall be .08mm
(.003in.) maximum in excess of the
“B” dimension. Dambar cannot be
located on the lower radius or the
foot.
4. “L” is the length of terminal for
soldering to a substrate.
5. “b” & “C” include lead finish
thickness.
Figure 13: Package Outline & Dimensions
JUNE, 2000, VERSION 1.2
58
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
10. Revision History
October 13, 1999: First Release, V1.0.
March 7, 2000: Second Release, V1.1: Throughout: changed encoder registers (40-8D) from little endian
to big endian; p. 1, new patent referenced; p.12, corrected table by adding VGA_CKOUTTL, specifying
proper clock for non-Intel designs, and proper Syncs for nVidia; p. 13, HSYNC_OUT & VSYNC_OUT are for
Slave Mode; p. 14, CSYNC is active high and reverence output voltage is 1.276 V; p. 18 & 39, corrected
width of Burst Width register; p. 29, added HSOUTWID, HSOUTST, HSOUTEND registers description; p.
36, added VSOUTWID, VSOUTST, VSOUTEND registers description; p. 52, changes to 7.3 layout
considerations; p. 53-4, corrected 5V tolerant issues; p. 56, added VIREF.
June 24, 2000: Third Release, V1.2: minor updates for clarity & formatting, p. 52, updated analog bypass
recommendations; p. 58, added pin picture; p. 59, fixed part mark.
11. Order Information
Order Number
444-2131
444-2132
Temperature Range
0°C to 65°C
0°C to 65°C
Screening
Commercial
Commercial
Package
100 Lead PQFP
100 Lead PQFP
Package Marking
FS450AC
FS451AC
Package Markings:
FOCUS
Enhancements
iNet TV FS45x
<YYWWR>
<fab lot id>
where x = 0, or 1; YY=year; WW=work week; R=Revision.
Please forward suggestions and corrections as soon as possible to the email address below. The
information herein is accurate to the best of FOCUS’ knowledge, but not all specifications have
been characterized or tested at the time of the release of this document. Parameters will be
updated as soon as possible and updates made available.
All parameters contained in this specification are guaranteed by design, characterization, sample testing or
100% testing as appropriate. Focus Enhancements reserves the right to change products and
specifications without notice. This information does not convey any license under patent rights of Focus
Enhancements, Inc. or others.
Critical Applications Policy
Focus Enhancements components are not designed for use in Critical Applications. Critical Applications
are products whose use may involve risks of death, personal injury, severe property damage or
environmental damage or life support applications, devices, or systems, wherein a failure or malfunction of
the component can reasonably be expected to result in death or personal injury. The user of Focus
Enhancements components in Critical Applications assumes all risk of such use and indemnifies Focus
Enhancements against all damages.
FOCUS Enhancements, Inc.
JUNE, 2000, VERSION 1.2
59
COPYRIGHT 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
FS401, FS402, FS403
PRODUCT SPECIFICATION
REV. NO. 1.2
600 Research Drive
Wilmington, MA 01887
www.FOCUSinfo.com
JUNE, 2000, VERSION 1.2
Phone:
Fax:
Email:
60
(978) 988-5888
(978) 988-7555
[email protected]
COPYRIGHT 1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION