PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843034 is a general purpose, low phase ICS noise LVPECL synthesizer which can generate HiPerClockS™ frequencies for a wide variety of applications. The ICS843034 has a 4:1 input Multiplexer from which the following inputs can be selected: 1 differential input, 1 single-ended input, or two crystal oscillators, thus making the device ideal for frequency translation or frequency generation. Each differential LVPECL output pair has an output divider which can be independently set so that two different frequencies can be generated. Additionally, each LVPECL output pair has a dedicated power supply pin so the outputs can run at 3.3V or 2.5V. The ICS843034 also supplies a buffered copy of the reference clock or crystal frequency on the single-ended REF_CLK pin which can be enabled or disabled (disabled by default). The output frequency can be programmed using either a serial or parallel programming interface. • Dual differential 3.3V LVPECL outputs which can be set independently for either 3.3V or 2.5V The phase jitter of the ICS843034 is less than 1ps rms, making it suitable for use in Fibre Channel, SONET, and Ethernet applications. • RMS phase jitter at 333.33MHz, using a 22.222MHz crystal (12kHz to 20MHz): 0.80ps (typical) • 4:1 Input Mux: 1 differential input 1 single-ended input 2 crystal oscillator interfaces • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • TEST_CLK accepts LVCMOS or LVTTL input levels • Output frequency range: 35MHz to 750MHz • Crystal input frequency range: 12MHz to 40MHz • VCO range: 560MHz to 750MHz • Parallel or serial interface for programming feedback divider and output dividers • Supply voltage modes: Example applications include systems which must support both FEC and non FEC rates. In 10Gb Fibre Channel, for example, you can use a 25.5MHz crystal to generate a 159.375MHz reference clock, and then switch to a 20.544MHz crystal to generate 164.355MHz for 66/64 FEC. Other applications could include suppor ting both Ether net frequencies and SONET frequencies in an application. When Ethernet frequencies are needed, a 25MHz crystal can be used and when SONET frequencies are needed, the input MUX can be switched to select a 38.88MHz Crystal. LVPECL outputs (core/outputs): 3.3V/3.3V 3.3V/2.5V REF_CLK output (core/outputs): 3.3V/3.3V • 0°C to 70°C ambient operating temperature • Industrial temperature available upon request • Available in both, Standard and RoHS/Lead-Free compliant packages CLK nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 M5 M6 M7 PIN ASSIGNMENT M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 48-Pin LQFP 6 31 7mm x 7mm x 1.4mm 7 30 package body 8 29 Y Package 9 28 Top View 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS843034 XTAL_OUT1 XTAL_IN1 XTAL_OUT0 XTAL_IN0 TEST_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR VEE nc VCCO_REF REF_CLK VCCO_B nFOUTB0 FOUTB0 VCCO_A nFOUTA0 FOUTA0 VCC TEST The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843034AY www.icst.com/products/hiperclocks.html 1 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER BLOCK DIAGRAM OE_A VCO_SEL XTAL_IN0 XTAL_OUT0 ÷1 ÷2 ÷3 ÷4 ÷5 101 ÷6 ÷8 111 ÷16 ÷ VCCO_A 001 VCCO_B 000 001 010 011 OSC 00 OSC 01 XTAL_IN1 0 FOUTA0 nFOUTA0 XTAL_OUT1 PHASE CLK nCLK DETECTOR 1 VCO 10 FOUTB0 nFOUTB0 011 TEST_CLK 11 ÷M 101 SEL1 111 ÷16 ÷ SEL0 OE_B VCCO_REF MR REF_CLK OE_REF S_LOAD S_DATA TEST S_CLOCK C nP_LOAD I M8:M0 L NA2:NA0 NB2:NB0 843034AY www.icst.com/products/hiperclocks.html 2 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS843034 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 560MHz to 750MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B to program the VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 23 ≤ M ≤ 30. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and Nx output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and Nx output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and Nx output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and Nx bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The ICS843034 supports either serial or parallel programming modes to program the M feedback divider and N output divider. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on the M, NA, and NB inputs are passed directly to the M divider and both N output dividers. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M and N dividers remain loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and Nx bits can be hardwired to set the M divider and Nx output divider to a specific default state that will automatically occur during power-up. T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Output 1 0 Output of M divider 1 1 FOUTA0 same frequency SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S t T0 NB2 NB1 NB0 NA2 NA1 NA0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H nP_LOAD t S PARALLEL LOADING M0:M8, NA0:NA2, NB0:NB2 M, N nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS 843034AY www.icst.com/products/hiperclocks.html 3 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 41, 42, 43, 44, 45, 47, 48 2, 3 Name M8, M0, M1, M2, M3, M4, M6, M7 NB0, NB1 Input Pulldown Input Pullup 4 NB2 Input 5 OE_REF Input 6 OE_A Input 7 OE_B Input 8, 14 VCC Power 9, 10 NA0, NA1 Input 11 NA2 Input 12, 24 VEE Power 13 TEST Output 20 FOUTA0, nFOUTA0 VCCO_A FOUTB0, nFOUTB0 VCCO_B 21 REF_CLK 15, 16 17 18, 19 Type Description M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. Determines output divider value as defined in Table 3C, Pulldown Function Table. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of REF_CLK output. Pulldown LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTA0, Pullup nFOUTA0 outputs. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of FOUTB0, Pullup nFOUTB0 outputs. LVCMOS/LVTTL interface levels. Core supply pins. Pullup Determines output divider value as defined in Table 3C, Pulldown Function Table. LVCMOS/LVTTL interface levels. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Output Differential output for the synthesizer. LVPECL interface levels. Power Output supply pin for FOUTA0, nFOUTA0. Output Differential output for the synthesizer. LVPECL interface levels. Power Output supply pin for FOUTB0, nFOUTB0. Output Reference clock output. LVCMOS/LVTTL interface levels. 22 VCCO_REF Power 23 nc Unused 25 MR Input Pulldown 26 S_CLOCK Input Pulldown 27 S_DATA Input Pulldown 28 S_LOAD Input Pulldown 29 VCCA Power 30, 31 SEL0, SEL1 Input Pulldown Clock select inputs. LVCMOS/LVTTL interface levels. 32 TEST_CLK Input Pulldown Test clock input. LVCMOS/LVTTL interface levels. XTAL_IN0, XTAL_OUT0 XTAL_IN1, 35, 36 XTAL_OUT1 Continued on next page... 33, 34 843034AY Input Input Output supply pin for REF_CLK. No connect. Active High Master Reset. When logic HIGH, forces the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin. Cr ystal oscillator interface. XTAL_IN0 is the input, XTAL_OUT0 is the output. Cr ystal oscillator interface. XTAL_IN1 is the input, XTAL_OUT1 is the output. www.icst.com/products/hiperclocks.html 4 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. Number Name 37 CL K ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Type Description Input Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input.VCC/2 default when left floating. 38 nCLK Input Pulldown Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at NA2:NA0 and 39 nP_LOAD Input Pulldown NB2:NB0 is loaded into the N output dividers. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 40 VCO_SEL Input Pullup LVCMOS/LVTTL interface levels. M divider inputs. Data latched on LOW-to-HIGH transition 46 M5 Input Pullup of nP_LOAD input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation REF_CLK Capacitance Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance CPD 843034AY Test Conditions Minimum Typical VCC, VCCA, VCCO_REF = 3.465V REF_CLK 5 www.icst.com/products/hiperclocks.html 5 Maximum Units 4 pF TB D pF 51 kΩ 51 kΩ 7 12 Ω REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 1 0 1 1 1 • • • • • • • • • • 700 28 0 0 0 0 1 1 1 0 0 • • • • • • • • • • • VCO Frequency (MHz) M Divide 575 23 • 750 30 0 0 0 0 1 1 1 1 NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 25MHz. 0 TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs N Divider Value Output Frequency (MHz) *NX2 *NX1 *NX0 Minimum Maximum 0 0 0 1 560 750 0 0 1 2 280 375 0 1 0 3 186.66 250 0 1 1 4 140 187.5 1 0 0 5 112 150 1 0 1 6 93.33 125 1 1 0 8 70 93.75 1 1 1 16 35 46.875 *NOTE: X denotes Bank A or Bank B 843034AY www.icst.com/products/hiperclocks.html 6 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VCC VCCA VCCO_A, VCCO_B Output Supply Voltage VCCO_REF Output Supply IEE Power Supply Current 185 mA ICCA Analog Supply Current 20 mA 843034AY Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V REF_CLK www.icst.com/products/hiperclocks.html 7 3.135 3.3 3.465 V 2.375 2.5 2.625 V 3.135 3.3 3.465 V REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = VCCO_REF = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIM Input Mid Voltage VIL Input Low Voltage TEST_CLK, MR, SEL[1:0], OE_REF, S_CLOCK, S_DATA, Input S_LOAD, nP_LOAD, High Current Nx2, M1:M4, M6:M8 IIH IIL Input Low Current Test Conditions Maximum Units 2 VCC + 0.3 V VCC/2 - 0.2V VCC/2 + 0.2V V -0.3 0.8 V VCC = VIN = 3.465V 150 µA Nx0, Nx1, M5, OE_A, OE_B, VCO_SEL VCC = VIN = 3.465V 5 µA TEST_CLK, MR, SEL[1:0], OE_REF, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, Nx2, M1:M4, M6:M8 VCC = 3.465V, VIN = 0V Nx0, Nx1, M5, OE_A, OE_B, VCO_SEL VOH Output High Voltage TEST; NOTE 1 REF_CLK Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Output terminated with 50Ω to VCCO_REF/2. 843034AY VCC = 3.465V, VIN = 0V VCCO_REF = 3.3V±5% Minimum -5 µA -150 µA 2.6 V VCCO_REF - 0.3V VCCO_REF = 3.3V±5% www.icst.com/products/hiperclocks.html 8 Typical 0.4 V 0. 5 V REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions Minimum CLK VIN = VCC = 3.465V nCLK VIN = 0V, VCC = 3.465V CLK VIN = 0V, VCC = 3.465V Input Low Current VPP Peak-to-Peak Input Voltage Maximum Units 150 µA 150 µA VIN = VCC = 3.465V nCLK IIL Typical -150 µA -5 µA 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 1.3 V VCC - 0.85 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V V OL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCCO_A, VCCO_B - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fIN Input Frequency Test Conditions Minimum XTAL_IN0/XTAL_OUT0, XTAL_IN1/XTAL_OUT1 CLK/nCLK, TEST_CLK Typical Maximum Units 12 40 MHz 12 TBD MHz 50 MHz S_CLOCK TEST_CLK TBD ns S_LOAD, S_DATA, TBD ns S_CLOCK NOTE: For the input cr ystal, CLK/nCLK and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 560MHz to 750MHz range. Using the minimum input frequency of 12MHz, valid values of M are 47 ≤ M ≤ 62. Using the maximum frequency of 40MHz, valid values of M are 14 ≤ M ≤ 18. tR/tF Input Rise/Fall Time TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW 843034AY 12 www.icst.com/products/hiperclocks.html 9 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency Phase Jitter, RMS (Random); NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 3, 4 tsk(o) Output Skew; NOTE 2, 4, 5 t R / tF Output Rise/Fall Time tS Setup Time odc Hold Time Typical 35 333.33MHz, Integration Range: 12kHz - 20MHz tjit(Ø) tH Minimum Measured @ the same Output Frequency LVPECL Outputs REF_CLK 20% to 80% Maximum Units 750 MHz 0.80 ps TBD ps 50 ps 200 700 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Characterized with REF_CLK output disabled. NOTE 3: Jitter perforance using XTAL inputs. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. % 1 ms Maximum Units 750 MHz TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = VCCO_B = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions FOUT Output Frequency tjit(Ø) Phase Jitter, RMS (Random); NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 3, 4 tsk(o) Output Skew; NOTE 2, 4, 5 t R / tF Output Rise/Fall Time tS Setup Time tH Hold Time Minimum Typical 35 333.33MHz, Integration Range: 12kHz - 20MHz Measured @ the same Output Frequency LVPECL Outputs REF_CLK 20% to 80% TBD ps TBD ps 50 ps 200 700 ps M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle tLOCK PLL Lock Time 50 % 1 ms For notes, see Table 7A above. 843034AY www.icst.com/products/hiperclocks.html 10 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 7C. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_A = 3.3V±5%, VCCO_B = 2.5V±5%,TA = 0°C TO 70°C OR VCC = VCCA = 3.3V±5%, VCCO_A = 2.5V±5%, VCCO_B = 3.3V±5%,TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency 333.33MHz, Integration Range: 12kHz - 20MHz Phase Jitter, RMS (Random); NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter ; NOTE 3, 4 Output Skew; NOTE 2, 4, 5 tR / tF Output Rise/Fall Time Measured @ the same Output Frequency LVPECL Outputs REF_CLK 20% to 80% M, N to nP_LOAD tS tH odc Setup Time Hold Time Typical 35 tjit(Ø) tsk(o) Minimum Units 750 MHz TBD ps TBD ps 50 ps 200 700 ps 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Characterized with REF_CLK output disabled. NOTE 3: Jitter perforance using XTAL inputs. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 843034AY Maximum www.icst.com/products/hiperclocks.html 11 % 1 ms REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 333.33MHZ ➤ 0 -10 Filter -30 -40 -50 -60 -70 333.33MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.80ps (typical) -80 Raw Phase Noise Data -90 -100 -110 -120 ➤ -130 -140 -150 -160 -170 -180 -190 ➤ NOISE POWER dBc Hz -20 10 100 1k Phase Noise Result by adding a Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843034AY www.icst.com/products/hiperclocks.html 12 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V 2.8V±0.04V 2V VCC , VCCA, VCCO_A, VCCO__B Qx SCOPE VCC , VCCA VCCO_A, VCCO__B LVPECL Qx SCOPE LVPECL VEE nQx nQx VEE -0.5V ± 0.125V -1.3V ± 0.165V 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT FOUTA0/nFOUTA0, FOUTB0/nFOUTB0 1.65V±5% VOH VREF SCOPE VCC , VCCA, VCCO_REF Qx LVCMOS VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements VEE Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) -1.65V ± 5% 3.3VCORE/3.3V REF_CLK OUTPUT LOAD AC TEST CIRCUIT PERIOD JITTER nFOUTx nFOUTA0 FOUTx FOUTA0 t PW t nFOUTy FOUTy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD 80% 80% 80% 80% VSW I N G Clock Outputs 20% 20% tR Clock Outputs tF LVPECL OUTPUT RISE/FALL TIME 843034AY 20% 20% tR tF LVCMOS OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 13 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843034 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V, 2.5V VCC .01μF 10 Ω VCCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 843034AY www.icst.com/products/hiperclocks.html 14 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 843034AY www.icst.com/products/hiperclocks.html 15 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The ICS843034 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 5 below were determined using a 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 18p X1 18pF Parallel Crystal XTAL_IN 843034 C2 22p ICS84332 Figure 5. CRYSTAL INPUt INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 6A. LVPECL OUTPUT TERMINATION 843034AY 125Ω 84Ω FIGURE 6B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 16 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 2.5V LVPECL OUTPUT Figure 7A and Figure 7B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 7B can be eliminated and the termination is shown in Figure 7C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 7A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 7B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 7C. 2.5V LVPECL TERMINATION EXAMPLE 843034AY www.icst.com/products/hiperclocks.html 17 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION SCHEMATIC EXAMPLE Figure 8 shows a schematic example of using an ICS843034. In this example, the CLK/nCLK input is driven by a 3.3V LVPECL driver. The data sheet also shows the CLK/nCLK input driven by various types of drivers. The crystal inputs are parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are 22pF. This schematic example shows hardwired logic control input handling. The logic inputs can also be driven by 3.3V LVCMOS drivers. It is recommended to have one decouple capacitor per power pin. In general, the decoupling capacitor values are ranged from 0.01uF to 0.1uF. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R9, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible. Only two examples of 3.3V LVPECL termination are shown in this schematic example. Additional LVPECL terminations can be found in the LVPECL Termination Application Note. The data sheet also shows 2.5V LVPECL terminations. The REF_CLK is LVCMOS driver with 7Ω output impedance. Series termination for REF_CLK is shown in the example. Additional LVCMOS termination can be found in the LVCMOS Application Note. If the REF_CLK is not used, it is recommended to disable this output by setting REF_OE to logic low. To disable REF_CLK, REF_OE pin can be left floating (default logic low by internal 51K pull down) or pull down using an external 1KΩ resistor. 3. 3V Zo = 50 Zo = 50 C1 X1 C2 LVPECL 22p R11 50 CL=18pF 22p 48 47 46 45 44 43 42 41 40 39 38 37 R10 50 VCC X_OUT1 X_IN1 X_OUT0 X_IN0 TEST_CLK SEL1 SEL0 VCCA S_LOAD S_DATA S_CLOCK MR X1 22p 36 35 34 33 32 31 30 29 28 27 26 25 C4 CL=18pF 22p VCC R9 10 VCCA U1 I CS843034 13 14 15 16 17 18 19 20 21 22 23 24 C9 0. 1u M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE TEST VCC FOUTA0 nFOUTA0 VCCO_A FOUTB0 nFOUTB0 VCCO_B REF_CLK VCCO_REF P_DIV VEE 1 2 3 4 5 6 7 8 9 10 11 12 C3 M7 M6 M5 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD nCLK CLK R12 50 C11 0.01u C16 10u VCC C5 0.1u VCCO_REF VCCO C6 0.1u Zo = 50 Ohm C7 0.1u C8 0.1u + Zo = 50 Ohm - VCC=3.3V R2 50 VCCO=3.3V R1 50 VCCO_REF=3.3V R8 43 Zo = 50 Ohm R3 50 LVCMOS Logic Input Pin Examples Set Logic Input to '1' VCC VCCO Set Logic Input to '0' VCC R4 133 R6 133 Zo = 50 Ohm RU1 1K RU2 SPARE To Logic Input pins RD1 SPARE + To Logic Input pins RD2 1K Zo = 50 Ohm - Alternative Termination Exmaple R5 82.5 R7 82.5 FIGURE 8. ICS843034 APPLICATION SCHEMATIC EXAMPLE 843034AY www.icst.com/products/hiperclocks.html 18 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843034. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843034 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 185mA = 641mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 641mW + 60mW = 701mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.701W * 42.1°C/W = 99.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 843034AY www.icst.com/products/hiperclocks.html 19 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 8. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (V CCO_MAX • -V OH_MAX ) = 0.9V For logic low, VOUT = V =V OL_MAX (V CCO_MAX -V OL_MAX CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V ))/R ] * (V OH_MAX CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843034AY www.icst.com/products/hiperclocks.html 20 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS843034 is: 11,748 843034AY www.icst.com/products/hiperclocks.html 21 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER FOR 48 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 843034AY www.icst.com/products/hiperclocks.html 22 REV. A JULY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843034 FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843034AY ICS843034AY 48 Lead LQFP tray 0°C to 70°C ICS843034AYT ICS843034AY 48 Lead LQFP 1000 tape & reel 0°C to 70°C ICS843034AYLF ICS843034AYL 48 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS843034AYLFT ICS843034AYL 48 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843034AY www.icst.com/products/hiperclocks.html 23 REV. A JULY 25, 2005