ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85401 is a high performance 2:1 Differential-to-LVDS Multiplexer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85401 can also perform differential translation because the differential inputs accept LVPECL, CML as well as LVDS levels. The ICS85401 is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space constrained boards. • 2:1 LVDS MUX ICS • 1 LVDS output • 2 differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: >2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nCLK0, nCLK1 • Propagation delay: 460ps (maximum) • Part-to-part skew: 100ps (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature VDD GND 16 15 14 13 12 nCLK0 2 11 Q CLK1 3 10 nQ nCLK1 4 9 CLK_SEL 5 6 7 8 nc 1 CLK0 1 VDD Q nQ nc CLK1 nCLK1 0 CLK_SEL CLK0 nCLK0 GND PIN ASSIGNMENT nc BLOCK DIAGRAM GND GND ICS85401 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View 85401AK www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 CLK0 Input Type 2 nCLK0 Input 3 CLK1 Input 4 nCLK1 Input 5, 7, 16 nc Unused 6 CLK_SEL Input Description Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. 8, 13 VDD Power Unused pins. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. Positive supply pins. 9, 12, 14, 15 GND Power Power supply ground. 1 0, 11 nQ, Q Output Differential output pair. LVDS interface levels. Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP RPULLDOWN Test Conditions Minimum Typical Maximum Units 1 pF Input Pullup Resistor 37 kΩ Input Pulldown Resistor 37 kΩ TABLE 3. CONTROL INPUT FUNCTION TABLE Input Clock Out CLK_SEL CLK 0 CLK0, nCLK0 1 CLK1, nCLK1 85401AK www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 40 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage CLK_SEL 2 VDD + 0.3 V VIL Input Low Voltage CLK_SEL -0.3 0.8 V IIH Input High Current CLK_SEL VDD = VIN = 3.465V 150 µA IIL Input Low Current CLK_SEL VDD = 3.465V, VIN = 0V -150 µA NOTE: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, "Output Load Test Circuit". TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current Test Conditions Minimum Typical Maximum Units CLK0, CLK1 VDD = VIN = 3.465V 150 µA nCLK0, nCLK1 VDD = VIN = 3.465V 150 µA CLK0, CLK1 VDD = 3.465V, VIN = 0V -150 µA nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 µA IIL Input Low Current V PP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 0.8 1.2 1.2 V VDD V NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. 85401AK www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 200 350 500 mV 50 mV 1.05 1.15 1.25 V 50 mV Maximum Units >2.5 GHz ps TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions 20% to 80% Minimum Typical 260 360 460 100 ps 125 160 200 ps 51 % 49 MUX Isolation -55 dB All parameters measured at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85401AK www.icst.com/products/hiperclocks.html 4 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER PARAMETER MEASUREMENT INFORMATION VDD 3.3V ± 5% SCOPE Qx nCLK0, nCLK1 nQx nCLK0, nCLK1 Power Supply + Float GND V LVDS - V Cross Points PP CMR GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx nQ PART 1 Q0x Q Pulse Width t nQy PART 2 Qy odc = t sk(pp) PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PART-TO-PART SKEW nCLK0, nCLK1 CLK0, CLK1 Clock Outputs nQ 80% 80% tR tF 20% 20% Q tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY VDD LVDS ➤ DC Input out out DC Input LVDS 100 ➤ out VOS/∆ VOS ➤ VOD/∆ VOD ➤ out ➤ VDD ➤ OFFSET VOLTAGE SETUP 85401AK DIFFERENTIAL OUTPUT VOLTAGE SETUP www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver in- put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - Ω 100Ω Differential Transmission Line 100 Ohm Differiential Transmission Line FIGURE 2. TYPICAL LVDS DRIVER TERMINATION 85401AK www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V Zo = 50 Ohm 3.3V 3.3V R3 125 BY R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85401AK BY www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER APPLICATION SCHEMATIC EXAMPLE Figure 4 shows an example of ICS85401 application schematic. This device can accept different types of input signal. In this example, the input is driven by a LVDS driver. The decoupling capacitor should be located as close as possible to the power pin. 3.3V C1 0.1u 16 15 14 13 3.3V R2 100 Zo = 50 1 2 3 4 LVDS CLK0 nCLK0 CLK1 nCLK1 U1 3.3V nc CLK_SEL nc VDD nc GND GND VDD Zo = 50 Zo = 50 12 11 10 9 GND Q nQ GND + R1 Zo = 50 100 - ICS85401 3.3V 5 6 7 8 Zo = 50 R3 100 R4 1K Zo = 50 C2 0.1u LVDS FIGURE 4. ICS85401 APPLICATION SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS85401 is: 132 85401AK www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER 16 LEAD VFQFN TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 85401AK www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85401AK 401A 16 Lead VFQFN Tray -40°C to 85°C ICS85401AKT 401A 16 Lead VFQFN 2500 Tape & Reel -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85401AK www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 22, 2005 ICS85401 Integrated Circuit Systems, Inc. 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER REVISION HISTORY SHEET Rev Table A A A 85401AK T8 Page Description of Change Date 8 Add Schematic Layout. 8/23/04 10 Corrected count in Ordering Information Table 11/17/04 Pin Assignment - corrected label on pin 2. 2/22/05 1 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 22, 2005