PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS854058 is an 8:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz and HiPerClockS™ is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS854058 has 8 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects PCLK0, nPCLK0). • High speed 8:1 differential multiplexer ICS • 1 differential LVDS output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.5GHz • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input • Part-to-part skew: TBD • Propagation delay: 595ps (typical) • Supply voltage range: 3.135V to 3.465V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PCLK0 nPCLK0 000 PCLK1 nPCLK1 001 PCLK2 nPCLK2 010 PCLK3 nPCLK3 011 PCLK4 nPCLK4 100 PCLK5 nPCLK5 101 PCLK6 nPCLK6 110 PCLK7 nPCLK7 111 PIN ASSIGNMENT PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 Q0 nQ0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PCLK7 nPCLK7 PLCK6 nPCLK6 VDD Q0 nQ0 GND PCLK5 nPCLK5 PCLK4 nPCLK4 ICS854058 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View SEL2 SEL1 SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854058AG www.icst.com/products/hiperclocks.html REV. A APRIL 8, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 PCLK0 Type Input 2 nPCLK0 Input 3 PCLK1 Input Description Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VDD/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VDD/2 default when left floating. 4 nPCLK1 Input 5, 20 VDD Power 6, 7, 8 SEL0, SEL1, SEL2 Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. 9 PCLK2 Input Pulldown Non-inver ting differential LVPECL clock input. Positive supply pins. Inver ting differential LVPECL clock input. Pullup/Pulldown VDD/2 default when left floating. 10 nPCLK2 Input 11 PCLK3 Input Pulldown 12 nPCLK3 Input Pullup/Pulldown Inver ting differential LVPECL clock input. VDD/2 default when left floating. 13 nPCLK4 Input Pullup/Pulldown Inver ting differential LVPECL clock input. VDD/2 default when left floating. 14 PCLK4 Input Pulldown 15 nPCLK5 Input 16 PCLK5 Input Non-inver ting differential LVPECL clock input. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VDD/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. 17 GND Power Power supply ground. 1 8, 19 nQ0, Q0 Output Differential output pair. LVDS interface levels. 21 nPCLK6 Input Pullup/Pulldown 22 PCLK6 Input Pulldown 23 nPCLK7 Input Pullup/Pulldown 24 PCLK7 Input Pulldown Inver ting differential LVPECL clock input. VDD/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VDD/2 default when left floating. Non-inver ting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 854058AG www.icst.com/products/hiperclocks.html 2 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units KΩ RVDD/2 Pullup/Pulldown Resistors 50 KΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs SEL2 SEL1 SEL0 Q0 nQ0 0 0 0 PCLK0 nPCLK0 0 0 1 PCLK1 nPCLK1 0 1 0 PCLK2 nPCLK2 0 1 1 PCLK3 nPCLK3 1 0 0 PCLK4 nPCLK4 1 0 1 PCLK5 nPCLK5 1 1 0 PCLK6 nPCLK6 1 1 1 PCLK7 nPCLK7 854058AG www.icst.com/products/hiperclocks.html 3 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current 10mA Surge Current NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 15mA Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5% Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum 3.135 3.3 3.465 68 Units V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Test Conditions Minimum SEL0:SEL2 Typical 2 Input Low Voltage SEL0:SEL2 -0.3 IIH Input High Current SEL0:SEL2 VDD = VIN = 3.465V IIL Input Low Current SEL0:SEL2 VDD = 3.465V, VIN = 0V Maximum Units VDD + 0.3 V 0.8 V 15 0 µA -10 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V ± 5% Symbol Parameter Maximum Units PCLK0:PCLK7 VDD = VIN = 3.465V Test Conditions 150 µA nPCLK0:nPCLK7 VDD = VIN = 3.465V 150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical PCLK0:PCLK7 VDD = 3.465V, VIN = 0V -10 µA nPCLK0:nPCLK7 VDD = 3.465V, VIN = 0V -150 µA 0.15 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 1.2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V. 854058AG www.icst.com/products/hiperclocks.html 4 V REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V ± 5% Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 350 mV 50 mV 1.25 V 50 mV TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V Symbol Parameter Test Conditions Minimum Typical Maximum Units 2.5 GHz fMAX Output Frequency t PD Propagation Delay; NOTE 1 595 ps tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 TBD ps Output Rise/Fall Time 20% to 80% 180 tR / tF All parameters measured up to 1.3GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. 854058AG www.icst.com/products/hiperclocks.html 5 ps REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER PARAMETER MEASUREMENT INFORMATION V DD SCOPE Qx nPCLK0:7 3.3V±5% Power Supply Float GND + - LVDS V V Cross Points PP CMR PCLK0:7 nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nPCLK0:7 nQx PART 1 Qx PCLK0:7 nQ0 nQy PART 2 Qy Q0 tPD t sk(pp) PROPAGATION DELAY PART-TO-PART SKEW VDD out 80% VOD Clock Outputs DC Input 20% 20% tR LVDS tF ➤ 80% out ➤ VOS/∆ VOS ➤ OUTPUT RISE/FALL TIME OFFSET VOLTAGE VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE 854058AG www.icst.com/products/hiperclocks.html 6 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver in- put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 2. TYPICAL LVDS DRIVER TERMINATION 854058AG www.icst.com/products/hiperclocks.html 7 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER LVPE CL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL IN DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 nCLK Receiv er Zo = 50 Ohm HiPerClockS Input R2 84 FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 854058AG www.icst.com/products/hiperclocks.html 8 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER SCHEMATIC EXAMPLE near the receivers. It is recommended at least one decoupling capacitor per power pin. The decoupling capacitor should be low ESR and located as close as possible to the power pin. An application schematic example of ICS854058 is shown in Figure 4. The inputs can accept various types of differential signals. In this example, the inputs are driven by LVDS drivers. The transmission lines are assumed to be 100Ω differential. The 100Ω matched loads termination should be located Logic Control Input Examples Zo = 50 Set Logic Input to '1' VDD R1 100 Zo = 50 RU1 1K LVDS 100 Ohm Differential Set Logic Input to '0' VDD RU2 Not Install To Logic Input pins To Logic Input pins RD1 Not Install RD2 1K 100 Ohm Differential Zo = 50 U1 R2 100 Zo = 50 3.3V LVDS C1 0.1u 1 2 3 4 5 6 7 8 9 10 11 12 PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 PCLK7 nPCLK7 PCLK6 nPCLK6 VDD Q0 nQ0 GND PCLK5 nPCLK5 PCLK4 nPCLK4 24 23 22 21 20 19 18 17 16 15 14 13 Zo = 50 3.3V R3 100 + Zo = 50 - LVDS C2 0.1u 100 Ohm Differential ICS854058 FIGURE 4. ICS854058 SCHEMATIC EXAMPLE 854058AG www.icst.com/products/hiperclocks.html 9 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 70°C/W Multi-Layer PCB, JEDEC Standard Test Boards 200 63°C/W 500 60°C/W TRANSISTOR COUNT The transistor count for ICS854058 is: 361 854058AG www.icst.com/products/hiperclocks.html 10 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 854058AG www.icst.com/products/hiperclocks.html 11 REV. A APRIL 8, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS854058 8:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS854058AG ICS854058AG 24 Lead TSSOP 60 per tube -40°C to 85°C ICS854058AG ICS854058AG 24 Lead TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854058AG www.icst.com/products/hiperclocks.html 12 REV. A APRIL 8, 2004