TECHNICAL DATA KK74LV574 Octal D-type flip-flop; positive edge-trigger (3-State) The 74LV574 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT574. The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual Dinputs that meet the set-up and hold times requirements on the LOW-toHIGH CP transition. When OE is LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.0 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 20 1 DW SUFFIX SO 20 1 ORDERING INFORMATION KK74LV574N Plastic DIP KK74LV574DW SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Output Enable PIN 20=VCC PIN 10 = GND D Q L H H L L L X no change X Z L H Clock Output L,H, X H= high level L = low level X = don’t care Z = high impedance 1 KK74LV574 MAXIMUM RATINGS* Symbol VCC Parameter Value Unit DC supply voltage -0.5 to +7.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±35 mA ICC VCC current ±70 mA IGND GND current ±70 mA Power dissipation per package: Plastic DIP *4 SO *4 750 500 IIK * IOK * IO * 3 PD Tstg TL mW Storage Temperature -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage Min Max Unit 1.0 5.5 V VI DC Input Voltage 0 VCC V VO DC Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, tf Input Rise and Fall Time (Figure 1) 0 0 0 0 500 200 100 50 ns 0 V ≤ VCC ≤ 2.0 V 2.0 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V 3.6 V ≤ VCC ≤ 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV574 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Paramete r Test VCC conditions V Guaranteed Limit 25°C -40°C 85°C 125°C min max min max min max min max Unit VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level output voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level output voltage VI = VIH or VIL IO = -100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -8 mА 3.0 2.48 - 2.48 - 2.40 - 2.20 - V VI = VIH or VIL IO = -16 mА 4.5 3.70 - 3.70 - 3.60 - 3.50 - V LOW level VI = VIH or output VIL voltage IO = 100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 8 mА 3.0 - 0.33 - 0.33 - 0.40 - 0.50 V VI = VIH or VIL IO = 16 mА 4.5 - 0.40 - 0.40 - 0.55 - 0.65 V VOL II Input current VI = VCC or 0V 5.5 - ±0.1 - ±0.1 - ±1.0 - ±1.0 µА ICC Supply current VI =VCC or 0V IO = 0 µА 5.5 - 8.0 - 8.0 - 20 - 160 µА 3 KK74LV574 ICC1 Additional VI = VCC – supply 0.6V current per input 2.7 3.6 - 0.2 - 0.2 - 0.5 IOZ Three state 3-state output leakage VI (11) = VIH VO =VCC or current 0V 5.5 - ±0.5 - ±0.5 - ±5 - 0.85 mA ±10 µА AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=2.5 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C 125°C min max min max min max Unit tPHL, tPLH Propagation delay , Clock to Q VI = 0 V or V1 Figures 1,3 1.2 2.0 2.7 3.0 4.5 - 160 26 20 16 14 - 170 34 25 20 17 - 200 43 31 25 21 ns tPHZ, tPLZ Propagation delay, OE to Q VI = 0 V or V1 Figures 2,4 1.2 2.0 2.7 3.0 4.5 - 160 31 23 20 17 - 170 39 29 24 20 - 200 48 36 29 24 ns tPZH, tPZL Propagation delay, OE to Q VI = 0 V or V1 Figures 2,4 1.2 2.0 2.7 3.0 4.5 - 140 26 20 16 14 - 160 34 25 20 17 - 180 43 31 25 21 ns Input capacitance 5.5 - 7.0* - - - - pF Power dissipation VI = 0 V or VCC capacitance (per flip-flop) 5.5 - 50* - - - - pF CI CPD * T = 25oC TEST POINT DEVICE UNDER TEST OUTPUT * CL TEST POINT DEVICE UNDER TEST OUTPUT 1k * CL Connect to V CC when testing tPLZ and tPZL Connect to GND when testing tPHZ and tPZH * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 1. Test Circuit Figure 2. Test Circuit 4 KK74LV574 TIMING REQUIREMENTS CL=50 pF, tr=tf=2.5 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C 125°C min max min max min max tw Pulse Width, Clock (high) VI = 0 V or V1 Figures 1,3 1.2 2.0 2.7 3.0 4.5 120 29 21 17 15 - 34 25 20 - 41 30 24 - tsu Setup Time, Data to Clock VI = 0 V or V1 Figures 1,5 1.2 2.0 2.7 3.0 4.5 40 19 14 11 9 - 22 16 13 - 26 19 15 - th Hold Time, Clock to Data VI = 0 V or V1 Figures 1,5 1.2 2.0 2.7 3.0 5 5 5 5 - 5 5 5 5 - 5 5 5 5 - fc Clock Frequency 1.2 2.0 2.7 3.0 4.5 - 2 17 21 27 31 - 15 19 24 - 12 16 20 VI = 0 V or V1 Figures 1,3 Unit ns ns ns MHz VOL and VOH are the typical output voltage drop that occur with the output load. Figure 3. Switching Waveforms 5 KK74LV574 Figure 4. Switching Waveforms Figure 5. Switching Waveforms 6 KK74LV574 Temperature, °C Symbol VCC, V 85 -40°C to 25 125 Level of a signal V1 VM INPUTS VM OUTPUTS VX VY 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 V 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.32 0.4 0.55 0.6 0.85 0.88 1.5 2.1 2.3 3.45 % 50 50 56 56 50 50 50 58 52 50 12 11 12 11 12 88 88 87.5 88 88 V 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.6 0.65 0.90 0.78 1.4 2.0 2.2 3.35 % 50 50 56 56 50 50 50 60 53 50 12.5 11 12.5 11 12 86.5 87.5 87 88 88 V 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.65 0.7 1.0 0.68 1.3 1.9 2.1 3.25 % 50 50 56 56 50 50 50 62 55 50 12.5 11 12.7 11.5 11 85 86.5 86 87.5 88 EXPANDED LOGIC DIAGRAM 7 KK74LV574 N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 0.25 (0.010) M T L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 N 0.38 G K M H D NOTES: J Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° 1. Dimensions A and B do not include mold flash or protrusion. K 0.1 0.3 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side M 0.23 0.32 P 10 10.65 R 0.25 0.75 NOTES: for A; for B ‑ 0.25 mm (0.010) per side. 8