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status. Setting MODE Low puts the LXT300Z in the Hardware (H/W) mode. In the
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configuration and report status.
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RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and
RPOS outputs are Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the
rising edge of RCLK.
LXT300Z only: In the Host Mode, CLKE determines the clock edge at which these outputs are stable and valid. In the Hardware Mode both outputs are stable and valid on
the rising edge of RCLK.
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pF load) is required to enable the jitter attenuation function of the LXT300Z. These
pins may also be used to disable the jitter attenuator by connecting the XTALIN pin to
the positive supply through a resistor, and floating the XTALOUT pin.
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cable through a 1:2 step-up transformer without additional components. To drive
75 Ω coaxial cable, two 2.2 Ω resistors are required in series with the transformer.
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pins. A center-tapped, center-grounded, 2:1 step-up transformer is required on these
pins. Data and clock from the signal applied at these pins are recovered and output on
the RPOS/RNEG and RCLK pins.
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to power supply RV+ through a resistor. INT is reset by clearing the respective register
bit (LOS and/or DPM).
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this pin in the LXT300Z Host Mode. If CLKE is High, SDO is valid on the rising edge
of SCLK. If CLKE is Low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to and when CS is High.
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to Low, and remain Low.
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Loopback mode. Setting both RLOOP and LLOOP High causes a Reset.
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valid on the falling edge of SCLK.
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decoupling circuitry. Isolation between the transmit and
receive circuits is provided internally.
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The LXT300Z and LXT301Z are fully integrated PCM
transceivers for both 1.544 Mbps (DSX-1) and 2.048
Mbps (E1) applications. Both transceivers allow fullduplex transmission of digital data over existing twistedpair installations. The first page of this data sheet shows a
simplified block diagram of the LXT300Z; Figure 2
shows the LXT301Z. The LXT301Z is similar to the
LXT300Z, but does not incorporate the Jitter Attenuator
and associated Elastic Store, or the serial interface port.
The LXT300Z and LXT301Z transceivers each interface
with two twisted-pair lines (one twisted-pair for transmit,
one twisted-pair for receive) through standard pulse transformers and appropriate resistors.
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The LXT300Z and LXT301Z are low-power CMOS
devices. Each operates from a single +5 V power supply
which can be connected externally to both the transmitter
and receiver. However, the two inputs must be within ± .3V
of each other, and decoupled to their respective grounds
separately. Refer to Application Information for typical
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Upon power up, the transceiver is held static until the
power supply reaches approximately 3 V. Upon crossing
this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and receive delay lines and lock the
Phase Lock Loop to the receive line. A reference clock is
required to calibrate the delay lines. The transmitter reference is provided by TCLK. MCLK provides the receiver
reference for the LXT301Z. The crystal oscillator provides the receiver reference in the LXT300Z. If the
LXT300Z crystal oscillator is grounded, MCLK is used as
the receiver reference clock.
The transceiver can also be reset from the Host or Hardware Mode. In Host Mode, reset is commanded by simultaneously writing RLOOP and LLOOP to the register. In
Hardware Mode, reset is commanded by holding RLOOP
and LLOOP High simultaneously for 200 ns. Reset is initiated on the falling edge of the reset request. In either
mode, reset clears and sets all registers to 0 and then begins
calibration.
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The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the TTIP and
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on the transmit line, or when a reset command is received.
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The LXT300Z and LXT301Z transceivers can be controlled through hard-wired pins (Hardware Mode). Both
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LXT300Z Only: The LXT300Z can be controlled by a
microprocessor through a serial interface (Host Mode).
The mode of operation is set by the MODE pin logic level.
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Mode RPOS and RNEG outputs are valid on the rising
edge of RCLK. The LXT301Z operates in Hardware
Mode at all times.
LXT300Z Only: To operate in Hardware Mode, MODE
must be set Low. Equalizer Control signals (EC1 through
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Data Out pins. Diagnostic control for Remote Loopback
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