TM MP2101 1.6MHz Synchronous Step-Down plus 200mA LDO The Future of Analog IC Technology TM DESCRIPTION FEATURES The MP2101 is an internally compensated 1.6MHz fixed-frequency PWM step-down switcher with a 200mA low dropout (LDO) linear regulator. It is ideal for portable equipment powered by a single cell Lithium-Ion (Li+) Battery. The MP2101 can provide 800mA and 200mA of load current from a 2.5V to 6V input voltage. Both output voltages can be regulated as low as 0.6V. • • • • • The 800mA output channel features an integrated high-side switch and synchronous rectifier for high efficiency without an external Schottky diode. With peak current mode control and internal compensation, the MP2101 can be stabilized with ceramic capacitors and small inductors. The high-side switch can maintain 100% duty cycle in dropout condition. The 200mA LDO output is used to power noise sensitive circuitry. It has a separate input supply to reduce power dissipation and noise from the main switcher. Dropout voltage is 280mV under a 150mA load. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. • • • • • • • • • 0.8A Switcher Output and 0.2A LDO Output VIN1 Range for Switcher: 2.5V to 6V VIN2 Range for LDO: 1.2V to VIN1 Internal Power MOSFET Switches Stable with Low ESR Output Ceramic Capacitors Up to 93% Efficiency 0.01µA Shutdown Current 1.6MHz Fixed Switching Frequency Up to 100% Switcher Duty Cycle Thermal Shutdown Cycle-by-Cycle Over Current Protection Short Circuit Protection Power On Reset Output Available in 3x3 10-Pin QFN Packages APPLICATIONS • • • • • DVD+/-RW Drives Smart Phones PDAs Digital Cameras Portable Instruments “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. The MP2101 is available in small 3mm x 3mm 10-pin QFN packages. TYPICAL APPLICATION Efficiency vs Load Current 100 OUT1 1.8V @ 600mA 2 3 L1 4 6 1 EN1 IN1 EN2 PWROK SW1 MP2101 OUT2 IN2 FB2 FB1 GND 9 POWER OK 8 7 10 5 OUT2 1.2V @ 200mA VIN=3.3V 90 EFFICIENCY (%) OFF ON VIN 2.5V - 6V 80 VIN=4.2V 70 60 VIN=5.0V 50 40 10 MP2101 Rev. 1.0 8/18/2006 100 LOAD CURRENT (mA) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 1000 1 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE TOP VIEW FB1 1 10 FB2 EN1 2 9 EN2 IN1 3 8 PWROK SW1 4 7 OUT2 GND 5 6 IN2 IN1, OUT1/2 to GND ................. –0.3V to + 6.5V IN2 to GND ......................... –0.3V to VIN1 + 0.3V SW1 to GND....................... –0.3V to VIN1 + 0.3V PWROK to GND ......................... –0.3V to +6.5V FB1/2, EN1/2 to GND ................. –0.3V to +6.5V Operating Temperature .............–40°C to +85°C Junction Temperature...............................150°C Lead Temperature ....................................260°C Storage Temperature .............–65°C to +150°C Recommended Operating Conditions Supply Voltage VIN1 ........................... 2.5V to 6V Supply Voltage VIN2 ..........................1.2V to VIN1 Output Voltage VOUT1/2 ....................... 0.6V to 6V Operating Temperature .............–40°C to +85°C EXPOSED PAD ON BACKSIDE Thermal Resistance Part Number* MP2101DQ * Package QFN10 (3mm x 3mm) (2) Temperature –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP2101DQ–Z) For RoHS compliant packaging, add suffix –LF (eg. MP2101DQ–LF–Z) (3) θJA θJC QFN10 (3mm x 3mm) ............. 50 ...... 12... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. ELECTRICAL CHARACTERISTICS (4) VIN1/2 = VEN1/2 = 3.6V, TA = +25°C, unless otherwise noted. Parameters Condition No Load Supply Current VFB1/2 = 0.62V VEN1 = 0V, VEN2 = 3.6V VEN1 = 3.6V, VEN2 = 0V VEN1/2 = 0V, VIN1/2 = 6V Hysteresis = 20°C FB1/2 with respect to the Nominal Value FB1/2 with respect to the Nominal Value ISINK = 5mA Switching Regulator LDO –40°C ≤ TA ≤ +85°C Shutdown Current Thermal Shutdown Trip Threshold PWROK Upper-Trip Threshold PWROK Lower-Trip Threshold PWROK Output Lower Voltage PWROK Deglitch Timer (FB1) PWROK Deglitch Timer (FB2) EN1/2 Trip Threshold EN1/2 Pull-Down Resistor Switching Regulator IN1 Under Voltage Lockout Threshold Rising Edge IN1 Under Voltage Lockout Hysteresis TA = +25°C Regulated FB1Voltage –40°C ≤ TA ≤ +85°C FB1 Input Bias Current VFB1 = 0.62V MP2101 Rev. 1.0 8/18/2006 Min Typ Max Units 400 80 300 0.01 150 10 –10 550 100 400 1 µA µA µA µA °C % % V 0.3 0.3 1.5 0.588 0.582 –50 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 50 150 0.96 900 2.0 100 0.600 –2 µs 1.5 V kΩ 2.5 V mV 0.612 0.618 +50 V nA 2 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO ELECTRICAL CHARACTERISTICS (4) (continued) VIN1/2 = VEN1/2 = 3.6V, TA = +25°C, unless otherwise noted. Parameters SW1 PFET On Resistance SW1 NFET On Resistance SW1 Leakage Current SW1 PFET Peak Current Limit Oscillator Frequency Linear Regulator LDO IN2 Input Range Regulated FB2 Voltage FB2 Input Bias Current OUT2 Short Circuit Foldback OUT2 Output Current Dropout Voltage (5) Condition ISW1 = 100mA ISW1 = –100mA VEN1 = 0V, VIN = 6V VSW1 = 0V or 6V Duty Cycle = 100%, Current Pulse Width < 1ms ILOAD = 10mA, VOUT2=VFB2 TA = +25°C –40°C ≤ TA ≤ +85°C VFB2 = 0.6V VOUT2 = 0V VOUT = 1.2V ILOAD = 150mA, VOUT2 = 1.2V Min Typ 0.35 0.25 –2 Max Units Ω Ω +2 µA 0.9 1.4 2.0 A 1.2 1.6 2.0 MHz VIN1 0.612 0.618 +50 V 1.2 0.588 0.582 –50 0.600 –2 180 200 280 V nA mA mA mV Notes: 4) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization. 5) The dropout voltage is equal to VIN2 – VOUT2 when VOUT2 is 100mV below the nominal value. PIN FUNCTIONS Pin # Name 1 2 FB1 EN1 3 4 5 6 7 8 9 10 Description Feedback 1. Feedback Input for the switcher output (OUT1). Enable 1. Enable input for the switcher. Pull high to turn on the switcher; low to turn it off. Input 1. Main input supply for both the switcher and the auxiliary low dropout (LDO) linear IN1 regulator. SW1 Switcher Switch Node. Output for the 800mA switcher channel. GND Ground. IN2 Input 2. Input supply for the auxiliary linear regulator LDO output power device. Output 2. Output of the 200mA LDO. The LDO is designed to be stable with an external OUT2 minimum 1µF ceramic capacitor at 200mA of load current. Power On Reset Open Drain Output. A high output indicates that both outputs are within ±10% of the regulation value. A low output indicates that the output is outside of the ±10% PWROK window. PWROK is pulled down if EN1 and/or EN2 is low. The PWROK window comparators have a 50µs deglitch timer for the switcher and 150µs deglitch timer for the linear regulator LDO to avoid a false trigger during load transient. Enable 2. Enable input for the linear regulator LDO. Pull high to turn on the LDO; low to turn it EN2 off. FB2 Feedback 2. Feedback input for the linear regulator output (OUT2). MP2101 Rev. 1.0 8/18/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 3 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V, CIN1 = 4.7µF, CIN2 = 1µF, CO1 = 10µF, CO2 = 1µF, L = 2.2µH, TA = +25°C, unless otherwise noted. Efficiency vs Load Current 95 80 85 70 VIN=3.3V 60 VIN=4.2V 50 40 VIN=5.0V 30 65 VIN=4.2V 55 VIN=5.0V 45 100 LOAD CURRENT (mA) 1000 65 45 35 25 10 100 LOAD CURRENT (mA) 1000 10 Efficiency vs Load Current VIN=4.2V 55 VIN=5.0V 45 60 25 40 VIN=5.0V VIN=4.2V 1.80 VIN=3.3V 1.79 VIN=5.0V 1.78 1.77 0 200 400 600 800 LOAD CURRENT (mA) MP2101 Rev. 1.0 8/18/2006 1000 OUTPUT VOLTAGE (V) 2.52 1.81 100 LOAD CURRENT (mA) 60 50 30 1000 10 100 LOAD CURRENT (mA) 1000 Output Voltage vs Load Current 3.33 VIN=4.2V 2.50 VIN=3.3V 2.48 VIN=5.0V 2.46 2.44 2.42 2.40 VIN=5.0V 70 Output Voltage vs Load Current 1.82 VIN=4.2V 80 40 10 1000 Output Voltage vs Load Current 1.76 VIN=4.2V 70 50 100 LOAD CURRENT (mA) 90 80 35 10 VIN=3.3V 3.32 OUTPUT VOLTAGE (V) 65 1000 Efficiency vs Load Current EFFICIENCY (%) EFFICIENCY (%) 75 100 LOAD CURRENT (mA) 100 90 VIN=3.3V VIN=5.0V 55 100 85 VIN=4.2V 75 25 10 95 EFFICIENCY (%) 85 VIN=3.3V 75 Efficiency vs Load Current OUTPUT VOLTAGE (V) 95 35 20 10 Efficiency vs Load Current EFFICIENCY (%) 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current 3.31 VIN=4.2V 3.30 VIN=5.0V 3.29 3.28 3.27 3.26 0 200 400 600 800 LOAD CURRENT (mA) 1000 3.25 0 200 400 600 800 LOAD CURRENT (mA) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 1000 4 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V, CIN1 = 4.7µF, CIN2 = 1µF, CO1 = 10µF, CO2 = 1µF, L = 2.2µH, TA = +25°C, unless otherwise noted. Output Voltage vs Load Current VOUT2 = 1.5V VOUT2 = 2.5V 1.54 1.52 VIN=3.3V 1.50 LDO 1.48 0 40 80 120 160 LOAD CURRENT (mA) 200 Output Voltage vs Load Current 1.206 OUTPUT VOLTAGE (V) 2.53 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.56 Output Voltage vs Load Current 2.52 2.51 VIN=3.3V 2.50 LDO 2.49 PSRR vs Frequency 0 40 80 120 160 LOAD CURRENT (mA) 200 LDO 1.202 1.8 70 60 50 40 30 20 1.7 1.6 1.5 1.4 10 10 100 1K 10K 100K FREQUENCY (Hz) 1M 1.3 4.0 LDO Dropout vs Load Current 0 40 80 120 160 LOAD CURRENT (mA) 200 0.62 FEEDBACK VOLTAGE (V) FREQUENCY (MHz) 80 VIN=1.8V 1.203 Feedback Voltage vs Temperature 90 PSRR (dB) 1.204 Frequency vs Input Voltage 100 0 1.205 4.4 4.8 5.2 5.6 INPUT VOLTAGE (V) 6.0 0.61 0.60 FB2 FB1 0.59 0.58 -40 -10 +20 +50 +80 +110 +140 TEMPERATURE (°C) Enable Turn On Enable Turn Off EN = 3.6V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load EN = 3.6V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load DROPOUT VOLTAGE (V) 0.5 EN 2V/div. PWROK 2V/div. 0.4 0.3 0.2 VOUT1 1V/div. 0.1 0.0 VOUT2 1V/div. 0 50 100 150 200 LOAD CURRENT (mA) MP2101 Rev. 1.0 8/18/2006 EN 5V/div. PWROK 5V/div. VOUT1 1V/div. VOUT2 1V/div. 250 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 5 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V, CIN1 = 4.7 µF, CIN2 = 1µF, CO1 = 10µF, CO2 = 1µF, L = 2.2µH, TA = +25°C, unless otherwise noted. Input Ramp Up Input Ramp Down EN = 4V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load EN = 4V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load Heavy Load Ripple EN1 = VIN = 5V, IOUT1 = 0.8A Resistive Load VOUT1 10mV/div. VIN 2V/div. VIN 2V/div. VOUT1 2V/div. VOUT1 1V/div. VOUT2 1V/div. VOUT2 1V/div. VSW 2V/div. IL 0.5A/div. 1ms/div. PWROK Off vs VOUT1 Shorted PWROK Off vs VOUT2 Shorted EN = 4V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load PWROK 2V/div. IL 0.5A/div. Switcher Load Transient LDO Load Transients IOUT1 = 0.8A Resistive Load VIN2 = 3.3V, VOUT2 = 1.2V, IOUT2 = 0.02A to 0.15A Resistive Load IL 0.5A/div. MP2101 Rev. 1.0 8/18/2006 IOUT1 = 0.3A Resistive Load VOUT1 2V/div. VSW 5V/div. VOUT2 1V/div. VOUT1 0.1V/div. Over Current Protection EN = 4V, IOUT1 = 0.3A, IOUT2 = 0.1A Resistive Load PWROK 2V/div. VOUT1 1V/div. VOUT1 1V/div. VOUT2 1V/div. 400ns/div. VOUT2 50mV/div. IOUT2 0.1A/div. LDO Over Current Protection VIN2 = 3.3V, VOUT2 = 2.5V VOUT2 1V/div. IOUT2 0.1A/div. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 6 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO OPERATION The MP2101 uses an external resistor divider to set both the switcher and LDO output voltage from 0.6V to 6V. The MP2101 is a fixed-frequency 1.6MHz, 800mA current mode PWM step-down switcher with a 200mA low dropout (LDO) linear regulator. The MP2101 is optimized for low voltage, Li-Ion battery powered applications where high efficiency and small size are critical. IN1 3 EN1/2 2/9 ICS 0.6V + SLOPE COMP FB1 1 + IAMP 10X -CURRENT SENSE AMP BIAS & VOLTAGE REFERENCE + FEEDBACK ERROR EAMP1 AMP -- + PWMCMP EAO1 DH MAIN SWITCH (PCH) -- 1.6MHz OSCILLATOR CC 17pF PWM OSC PWM CONTROL LOGIC 4 SW1 SYNCHRONOUS RECTIFIER (NCH) DL 5 GND 6 + FB2 10 EAMP2 0.6V FB1/2 0.66V EAO2 -- + 7 OUT2 OUT_Hi -POWER ON RESET WINDOW COMPARATORS 0.54V + IN2 8 PWROK NO GOOD OUT_Lo -- Figure 1—MP2101 Function Diagram MP2101 Rev. 1.0 8/18/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 7 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO 800mA Step-Down Switcher The switcher integrates both a main switch and a synchronous rectifier, which provides high efficiency and eliminates the need for an external Schottky diode. This switcher can achieve 100% duty cycle. The duty cycle (D) of a step-down switcher is defined as: D = TON × fOSC × 100% ≈ VOUT × 100% VIN Where TON is the main switch on time and fOSC is the oscillator frequency (1.6MHz). Current Mode PWM Control Slope compensated current mode PWM control provides stable switching and cycle-by-cycle current limiting for superior load and line response in addition to protection of the internal main switch and synchronous rectifier. During each cycle, the PWM comparator modulates the power transferred to the load by changing the inductor peak current based on the feedback error voltage. During normal operation, the main switch is turned on to ramp the inductor current at each rising edge of the internal oscillator, then switched off when the peak inductor current is above the error voltage. When the main switch is turned off, the synchronous rectifier is immediately turned on and stays on until the next cycle begins. Dropout Operation The MP2101 allows the main switch to remain on for more than one switching cycle and increases the duty cycle while the input voltage is dropping close to the output voltage. When the duty cycle reaches 100%, the main switch is held on to deliver current to the output up to the PFET current limit. The output voltage then becomes the input voltage minus the voltage drop across the main switch and the inductor. MP2101 Rev. 1.0 8/18/2006 Short Circuit Protection When the output is shorted to ground, the oscillator frequency is reduced to prevent the inductor current from increasing beyond the PFET current limit, which is also reduced to lower the short circuit current. The frequency and current limit will return to the normal values once the short circuit condition is removed and the feedback voltage reaches 0.6V. Maximum Load Current The MP2101 can operate down to a 2.5V input voltage. However the maximum load current decreases at lower inputs due to a large IR drop on the main switch and synchronous rectifier. The slope compensation signal reduces the peak inductor current as a function of the duty cycle to prevent sub-harmonic oscillations at duty cycles greater than 50%. Conversely, the current limit increases as the duty cycle decreases. Power OK The MP2101 provides an open-drain PWROK output that goes high after both channels reach regulation during startup. PWROK goes low after one of the output channels goes out of regulation by ±10% or when the device enters shutdown. There is a built-in deglitch timer to avoid a false PWROK trigger during load transients (50µs for the switcher and 150µs for the LDO). When the output is disabled, Power OK remains low. 200mA Linear Regulator The 200mA low dropout (LDO) linear regulator has separate input (IN2) and output (OUT2) pins for the internal power device. The control circuitry of the LDO takes power from the main input supply (IN1). Both IN1 and IN2 input supplies must be present for the LDO to work properly. The LDO power device input (IN2) can be connected to the switcher output or directly to the main supply (Figure 2). If IN2 is tied to IN1, an optional RC filter can be inserted between IN1 and IN2. The RC filter reduces switching noise coupling from IN1 to IN2 and power dissipation inside the MP2101. The switcher guarantees 800mA output current, but output current to the switcher load will be reduced if the LDO draws current from the switcher output. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 8 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO APPLICATION INFORMATION Output Voltage Setting The external resistor divider sets the output voltage. The feedback resistor R1 of the switcher also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). R1 of the switcher should be 300kΩ for optimal transient response. R2 is then given by: R2 = R1 Inductor Selection A 1µH to 10µH inductor with a DC current rating of at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance should be <200mΩ. See Table 2 for recommended inductors and manufacturers. For most designs, the inductance value can be derived from the following equation: VOUT1 −1 0 .6 V L= R4 of the LDO should be 60kΩ for good loop response. R3 is then given by: R3 = R4 × ( VOUT2 − 1) 0. 6 V Table 1—Resistor Selection vs. Output Voltage Setting VOUT × (VIN − VOUT ) VIN × ∆IL × fOSC Where ∆IL is inductor ripple current. Choose the inductor ripple current to be approximately 30% of the maximum load current (800mA). The maximum inductor peak current is: IL(MAX ) = ILOAD + VOUT R1 R2 R3 R4 1.2V 300kΩ (1%) 300kΩ (1%) 1.5V 300kΩ (1%) 200kΩ (1%) 1.8V 300kΩ (1%) 150kΩ (1%) 2.5V 300kΩ (1%) 95.3kΩ (1%) 60kΩ (1%) 90kΩ (1%) 120kΩ (1%) 190kΩ (1%) 60kΩ (1%) 60kΩ (1%) 60kΩ (1%) 60kΩ (1%) ∆IL 2 Under light load conditions below 100mA, larger inductance is recommended for improved efficiency. Table 3 lists inductors recommended for this purpose. Table 2—Suggested Surface Mount Inductors Manufacturer Part Number Inductance (µH) Max DCR (Ω) Saturation Current (A) Dimensions LxWxH (mm3) Sumida Toko Sumida CDRH2D11 D521C CDRH3D16 2.2 2.2 2.2 0.098 0.059 0.072 1.27 1.63 1.20 3.2 x 3.2 x 1.2 5 x 5 x 1.5 4 x 4 x 1.8 Table 3—Inductors for Improved Efficiency at 25mA, 50mA, under 100mA Load. Manufacturer Part Number Inductance (µH) Max DCR (Ω) Saturation Current (A) IRMS (A) Coilcraft Murata Sumida Sumida DO1605T-103MX LQH4C100K04 CR32-100 CR54-100 10 10 10 10 0.3 0.2 0.2 0.1 1.0 1.2 1.0 1.2 0.9 0.8 0.7 1.4 MP2101 Rev. 1.0 8/18/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 9 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO Switcher Input Capacitor Selection The input capacitor (CIN1) reduces the surge current drawn from the input and switching noise from the device. The input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high frequency switching current passing to the input. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 4.7µF capacitor is sufficient. Switcher Output Capacitor Selection The output capacitor (CO1) keeps the output voltage ripple small and ensures regulation loop stability. The output capacitor impedance should be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. The output ripple ∆VOUT is approximately: ∆VOUT1 × (VIN1 − VOUT1 ) V ≤ OUT1 × VIN1 × f OSC × L ⎛ ⎞ 1 ⎜ ESR + ⎟ ⎜ 8 × fOSC × C O1 ⎟⎠ ⎝ Thermal Dissipation Power dissipation should be considered when both channels of the MP2101 provide maximum output current at high ambient temperatures. If the junction temperature rises above 150°C, the two channels will shut down. Start-Up Consideration To ensure a smooth start-up of OUT1 and OUT2, it is recommended that the enable signals (EN1 and EN2) be asserted only after the input power rails have been stabilized. If EN1 and EN2 are tied to input rails directly, the UVLO of the MP2101 will dictate when the part starts switching. Since for certain systems, the input supply may have relatively high impedance during ramp up, therefore depending solely on UVLO to start the part may cause input rail dip and output bounce. If the system designer can not provide the enable signal after input power rail is fully established, it is recommended that EN1 and EN2 are connected to the input power rail through a RC delay network (as shown in Figure 2). The RC time constant needs to be significantly large compare to the ramp-up time of the input power rail, which is usually of a few ms. PC Board Layout The high current paths (GND, IN1/IN2 and SW1) should be placed very close to the device with short, direct and wide traces. Input capacitors should be placed as close as possible to the respective IN and GND pins. The external feedback resistors should be placed next to the FB pins. Keep the switching nodes SW1 short and away from the feedback network. The junction-to-ambient thermal resistance of the 10-pin QFN (3mm x 3mm) RΘJA is 50°C/W. The maximum power dissipation is about 1.6W when the MP2101 is operating in a 70°C ambient temperature environment. PD MAX = MP2101 Rev. 1.0 8/18/2006 150 o C − 70 o C 50 o C / W = 1 .6 W www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 10 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO TYPICAL APPLICATION CIRCUIT OPTIONAL VIN 3.3V - 6V 2 OPTIONAL RIN3 OUT1 1.8V @ 800mA CIN3 3 4 6 1 EN1 IN1 SW1 EN2 PWROK MP2101 OUT2 IN2 FB2 FB1 GND 9 POWER OK 8 7 10 OUT2 2.5V @ 200mA 5 Figure 2—Optional RC Delay on EN1 and EN2 Circuit MP2101 Rev. 1.0 8/18/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 11 TM MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO PACKAGE INFORMATION 3mm x 3mm QFN10 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2101 Rev. 1.0 8/18/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 12