Agilent HSDL-3209 IrDA Data Compliant Low Power 115.2 kbit/s Infrared Transceiver Description Specifications version 1.4 Low Power from 9.6 kbit/s to 115.2 kbit/s with extended link distance and it is IEC 825Class 1 eye safe. The HSDL-3209 is an ultrasmall low cost infrared transceiver module that provides the interface between logic and infrared (IR) signals for through air, serial, halfduplex IR data link. It is designed to interface to input/ output logic circuits as low as 1.5V. The module is compliant to IrDA Physical Layer The HSDL-3209 can be shutdown completely to achieve very low power consumption. In the shutdown mode, the PIN diode will be inactive and thus producing very little photocurrent even under very bright ambient light. Such features are ideal for battery operated handheld products. Functional Block Diagram CX1 GND (7) Receiver RXD (2) HSDL-3209 CX4 TXD (3) R1 Vled LEDA (1) CX3 Figure 1. Functional Block Diagram • Guaranteed Temperature Performance, -25 to +70 °C - Critical parameters are guaranteed over temperature & supply voltage • Low Power Consumption - Complete shutdown of TXD, RXD, and PIN diode • LED Stuck-High Protection • Designed to Accommodate Light Loss with Cosmetic Windows • IEC 825-Class 1 Eye Safe SD (4) IOVcc (5) • Miniature Package - Height : 1.60 mm - Width : 7.00 mm - Depth : 2.80 mm • Interface to Input/Output Logic Circuits as Low as 1.5V CX2 IOVcc • Fully Compliant to IrDA 1.4 Low Power Specification from 9.6 kbit/s to 115.2 kbit/s • Vcc Supply 2.4 to 3.6 Volts Vcc Vcc (6) Features Transmitter Applications • Mobile Telecom - Mobile Phones - Pagers - Smart Phone • Data Communication - PDAs - Portable Printers • Digital Imaging - Digital Cameras - Photo-Imaging Printers • Electronic Wallet Order Information Part Number Packaging Type Package Quantity HSDL-3209-021 Tape and Reel Front View 2500 I/O Pins Configuration Table Pin Symbol Description I/O Type Function 1 LED A LED Anode Input Tied through external resistor, R1, to VLED from 2.4V to 4.5V. Please refer to Table 1 for VLED versus Series Resistor, R1. 2 RXD Receive Data Output, Active Low This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull down resistor is required. It is in tri-state mode when the transceiver is in shutdown mode. 3 TXD Transmit Data Input, Active High This pin is used to transmit serial data when SD pin is low. If held high longer than ~ 50µs, the LED will be turned off. 4 SD Shutdown Input, Active High The transceiver is in shutdown mode if this pin is high 5 IOVcc Input/Output ASIC Vcc Input/Output Active High Connect to ASIC logic controller Vcc Voltage as low as 1.5V. 6 Vcc Supply Voltage Supply Voltage Regulated, 2.4 to 3.6 Volts. 7 GND Ground Ground Connect to system ground. Recommended Application Circuit Components Component Recommended Value Note R1 15Ω±5%, 0.0625 Watt for 2.4 ≤ Vled ≤ 2.7V 27Ω±5%, 0.0625 Watt for 2.7 < Vled ≤ 3.6V 36Ω±5%, 0.0625 Watt for 3.6 < Vled ≤ 4.5V CX1, CX4 0.47 µF ± 20%, X7R Ceramic 1 CX2, CX3 6.8 µF ± 20%, X7R Ceramic or Tantalum 1 Notes: 1. CX1, CX2, CX3 and CX4 must be placed within 0.7 cm of the HSDL-3209 to obtain optimum noise immunity. CAUTIONS: The CMOS inherent to the design of this component increases the component’s susceptibility to damage from the electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD 2 Absolute Maximum Ratings For implementations where case to ambient thermal resistance is ≤ 50°C/W. Parameter Symbol Min. Max. Units Storage Temperature TS -40 +100 °C Operating Temperature TA -25 85 °C LED Anode Voltage VLEDA 0 6.5 V Supply Voltage VCC 0 6.5 V Input/Output Voltage IOVCC 0 VCC V Input Voltage : SD VI(SD) 0 IOVCC V Input Voltage : TXD VI(TXD) 0 IOVCC V DC LED Transmit Current ILED (DC) 50 mA Peak LED Transmit Current ILED (PK) 250 mA Notes 2 Notes: 2. ≤ 20% duty cycle, ≤ 90 ms pulse width. Recommended Operating Conditions Parameter Symbol Min. Operating Temperature TA Supply Voltage Input/Output Voltage Logic Input Voltage for TXD/SD Receiver Input Irradiance LED (Logic High) Current Pulse Amplitude Receiver Data Rate Ambient Light Max. Units -25 70 °C VCC 2.4 3.6 V IOVCC 1.5 VCC V Logic High VIH IOVcc-0.2 IOVcc V Logic Low VIL 0 0.4 V Logic High EIH 0.0081 500 mW/cm2 For in-band signals ≤ 115.2kbit/s [3] Logic Low EIL 1.0 µW/cm2 For in-band signals ILEDA Typ. 50 9.6 Conditions The minimum input logic voltage should not be lower than 1.5V [3] mA 115.2 kbit/s See IrDA Serial Infrared Physical Layer Link Specification, Appendix A for ambient levels Notes: 3. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4. 3 Electrical & Optical Specifications Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C with Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Conditions Viewing Angle 2θ½ 30 Peak Sensitivity Wavelength λp RXD Output Voltage Logic High VOH IOVcc-0.2 IOVcc V IOH = -200 µA, EI ≤ 1.0 µW/cm2 Logic Low VOL 0 0.4 V IOL = 200 µA, EI ≥ 8.1 µW/cm2 tPW (SIR) 1 4.0 µs θ½ ≤ 15°, CL =9 pF CL =9 pF Receiver RXD Pulse Width (SIR) [4] RXD Rise and Fall Times Receiver Latency Time [5] Receiver Wake Up Time [6] ° 880 nm tr, tf 60 ns tL 50 µs tW 100 µs 14 mW/sr ILEDA= 50 mA, θ½ ≤ 15°, VTXD ≥ VIH TA=25 °C, IOVcc = 1.8V Transmitter Radiant Intensity IEH 4 Viewing Angle 2θ½ 30 Peak Wavelength λp 875 nm Spectral Line Half Width ∆λ½ 35 nm High IH 0.02 10 µA VI ≥ VIH Low IL -0.02 10 µA 0 ≤ VI ≤ VIL On IVLED mA VI(TXD) ≥ VIH Shutdown IVLED 200 nA VI(SD) ≥ VIH 1.8 µs tPW (TXD) = 1.6 µs at 115.2 kbit/s TXD Input Current LED Current -10 60 50 1.4 1.6 ° Optical Pulse Width (SIR) tPW (SIR) Maximum Optical PW [7] tPW(max.) 100 µs TXD Rise and fall Time (Optical) tr, tf 600 ns tpw(TXD) = 1.6 µs LED Anode On State Voltage VON(LEDA) 1.8 V ILEDA=50mA, VI(TXD) ≥ VIH 1 µA VSD ≥ VIH, TA=25°C µA VI(TXD) ≤ VIL, EI = 0 1.55 Transceiver Supply Current Shutdown Idle [8] ICC1 ICC2 100 Notes: 4. For in-band signals from 9.6kbit/s to 115.2 kbit/s, where 9µW/cm 2 ≤ EI ≤ 500mW/cm2. 5. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity 6. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 7. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection. 8. For Vcc > 3V and IOVcc < 1.8V, ICC1 can exceed 15uA. 4 t pw VOH t pw 90% LED ON 90% 50% 50% 10% VOL LED OFF tf 10% tr tr tf Figure 2. RXD output waveform. Figure 3. LED optical waveform. TXD SD RX LIGHT LED RXD t pw (MAX.) t RW Figure 4. TXD “stuck on” protection waveform. Figure 5. Receiver wakeup time waveform. SD TXD TX LIGHT t TW Figure 6. TXD wakeup time waveform. Average LOP vs Average ILED 35 1.70 30 Average LOP (mW/Sr) Average VLED_A (V) Average VLED_A vs Average ILED 1.75 1.65 1.60 1.55 1.50 20 15 10 5 1.45 1.40 10.0E-3 25 30.0E-3 50.0E-3 70.0E-3 90.0E-3 110.0E-3 0 10.0E-3 30.0E-3 5 70.0E-3 Average ILED (A) Average ILED (A) Figure 7. VLED vs. ILED 50.0E-3 Figure 8. VLOP vs. ILED 90.0E-3 110.0E-3 2.80 0.80 HSDL-3209 Package Outline with Mechanical Dimensions Mounting Centre 1.60 0.80 3.50 7.00 0.95 5.10 R1.10 0.95 0.80 R1.10 PCB solder pad length SD IOVcc Vcc 0.34 (5x) 0.95 ± 0.05 (6x) 0.60 ± 0.05 (7x) Notes : 1. ALL DIMENSIONS IN MILLIMETERS (mm). 2. DIMENSION TOLERANCE IS 0.2mm UNLESS OTHERWISE SPECIFIED. 6 PCB GND 1.60 TXD 0.80 RXD 0.40 (2x) LEDA HSDL-3209 Tape and Reel Dimensions 4.0 ± 0.1 Unit: mm 1.75 ± 0.1 2.0 ± 0.1 ∅1.5 +0.1 0 POLARITY Pin 7: GND 7.5 ± 0.1 16.0 ± 0.2 Pin 1: LEDA 0.3 ± 0.05 7.35 ± 0.1 2.93 ± 0.1 1.78 ± 0.1 4.0 ± 0.1 Progressive Direction Empty Parts Mounted Leader (400mm min) (40mm min) Empty (40mm min) Option # 021 "C" 80 "B" 330 Quantity 2500 Unit: mm Detail A 2.0 ± 0.5 B C ∅13.0 ± 0.5 R1.0 LABEL 21 ± 0.8 Detail A 16.4 +2 0 2.0 ± 0.5 7 Moisture Proof Packaging Baking Conditions: All HSDL-3209 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 4. If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Baking should only be done once. Package Temperature Units in A Sealed Mositure-Proof Package Time In Reel 60°C ≥ 48 hours In Bulk 100°C ≥ 4 hours 125°C ≥ 2 hours 150°C ≥ 1 hours Package Is Opened (Unsealed) Recommended Storage Conditions: Time from unsealing to soldering: Environment less than 30 deg C, and less than 60% RH ? After removal from the bag, the parts should be soldered within 72 hours if stored at the recommended storage conditions. If times longer than 72 hours are needed, the parts must be stored in a dry box. Yes No Baking Is Necessary Yes Package Is Opened less than 72 hours ? No Perform Recommended Baking Conditions 8 No Storage Temperature 10°C to 30°C Relative Humidity below 60% RH Recommended Reflow Profile MAX 260C T - TEMPERATURE (˚C) 255 R3 230 220 200 180 R2 R4 60 sec MAX Above 220 C 160 R1 120 R5 80 25 0 100 50 P1 HEAT UP P2 SOLDER PASTE DRY 150 200 P3 SOLDER REFLOW 250 P4 COOL DOWN 300 t-TIME (SECONDS) Maximum ∆T/∆time Process Zone Symbol DT Heat Up P1, R1 25°C to 160°C 4°C/s Solder Paste Dry P2, R2 160°C to 200°C 0.5°C/s Solder Reflow P3, R3 P3, R4 200°C to 255°C (260°C at 10 seconds max) 255°C to 200°C 4°C/s -6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. The DT/Dtime rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3209 castellation pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-3209 castellations. 9 Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and HSDL-3209 castellations to change dimensions evenly, putting minimal stresses on the HSDL3209 transceiver. Appendix A: SMT Assembly Application Note 1.0 Solder Pad, Mask and Metal Stencil Aperture METAL STENCIL FOR SOLDER PASTE PRINTING STENCIL APERTURE SOLDER MASK PCBA Stencil and PCBA 1.1 Recommended Land Pattern CL Mounting Center 0.10 1.75 0.775 fiducial 0.60 0.95 1.9 Unit: mm 2.85 10 1.2 Recommended Metal Solder Stencil Aperture Apertures as per land Dimensions It is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern. w l Aperture size (mm) Stencil Thickness, t (mm) Length, l (mm) Width, w (mm) 0.152 mm 2.60 ± 0.05 0.55 ± 0.05 0.127 mm 3.00 ± 0.05 0.55 ± 0.05 1.3 Adjacent Land Keepout and Solder Mask Areas Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be place at midlength of the pads for unit alignment. Note: Wet/Liquid PhotoImageable solder resist/mask is recommended. 11 t 7.2 0.2 2.6 3.0 Solder mask Units: mm Appendix B: PCB Layout Suggestion The HSDL 3209 is a shieldless part and hence does not contain a shield trace unlike the other transceivers. The following PCB layout guidelines should be followed to obtain a good PSRR and EM immunity resulting in good electrical performance. Things to note: Top layer Connect the metal shield & module ground pin to bottom ground layer Layer 2 Critical ground plane zone. Do not connect directly to the module ground pin Layer 3 Keep data bus away from critical ground plane zone Bottom layer (GND) 1. The ground plane should be continuous under the part. 2. VLED can be connected to either unfiltered or unregulated power supply. If VLED and Vcc share the same power supply, CX3 need not be used and the connections for CX1 and CX2 should be before the current limiting resistor R1. CX1 is generally a ceramic capacitor of low inductance providing a wide frequency response while CX2 and CX3 are tantalum capacitors of big volume and fast frequency response. The use of a tantalum capacitor is more critical on the VLED line, which carries a high current. CX4 is an optional ceramic capacitor, similar to CX1, for the IOVcc line. 3. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver module as Vcc, and sandwich that layer between ground connected board layers. Refer to the diagram below for an example of a 4 layer board, 12 The area underneath the module at the second layer, and 3cm in all direction around the module is defined as the critical ground plane zone. The ground plane should Top View be maximized in this zone. Refer to application note AN1114 or the Agilent IrDA Data Link Design Guide for details. The layout below is based on a 2-layer PCB. Bottom View Appendix C: General Application Guide for the HSDL-3209 Description The HSDL-3209, a low-cost and ultra-small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.4 low power specification from 9.6 kb/s to 115.2 kb/s, and supports HP-SIR and TV Remotes modes. The design of the HSDL-3209 also includes the following unique features: Speaker Audio Interface Microphone Selection of Resistor R1 Resistor R1 should be selected to provide the appropriate peak pulse LED current over different ranges of Vcc as shown on page 2 under “Recommended Application Circuit Components”. Interface to Recommended I/O chips The HSDL-3209’s TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kb/s up to 115.2 kb/s is available at the RXD pin. Figure 10 shows how the IrDA port fits into a mobile phone and PDA platform. The link distance testing was done using typical HSDL-3209 units with SMC’s FDC37C669 and FDC37N769 Super I/O controllers. An IrDA link distance of up to 50 cm was demonstrated. 13 ASIC Controller RF Interface Transceiver Mod /DeModulator IR Microcontroller User Interface Mobile Phone Platform Figure 9. Mobile phone platform LCD Panel - Low passive component count. - Shutdown mode for low power consumption requirement. DSP Core RAM ROM IR CPU for embedded application HSDL-3209 Touch Panel PCMCIA Controller RS232C Driver COM Port PDA Platform Figure 10. PDA platform HSDL-3209 Appendix D: Window Designs for HSDL-3209 Optical Port Dimensions for HSDL3209 To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30° and the maximum size corresponds to a cone angle of 60°. In the figure above, X is the width of the window, Y is the height of the window and Z is the distance from the HSDL3208 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens, K, is 5.1mm. The equations for computing the window dimensions are as follows: X = K + 2*(Z+D)*tanA IR Transparent Window OPAQUE MATERIAL Y ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;; IR Transparent Window OPAQUE MATERIAL X K ;;;;;;;;;;;;;;;;;;;;;;; Z A D The depth of the LED image inside the HSDL-3208, D, is 3.17mm. ‘A’ is the required half angle for viewing. For IrDA compliance, the minimum is 15° and the maximum is 30°. Assuming the thickness of the window to be negligible, the equations result in the following tables and graphs: Y = 2*(Z+D)*tanA The above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (Z). If they are comparable, Z’ replaces Z in the above equation. Z’ is defined as Module Depth (z) mm Aperture Width (x, mm) Aperture height (y, mm) Max min Max Min 0 8.76 6.80 3.66 1.70 1 9.92 7.33 4.82 2.33 2 11.07 7.87 5.97 2.77 3 12.22 8.41 7.12 3.31 Z’=Z+t/n 4 13.38 8.94 8.28 3.84 where ‘t’ is the thickness of the window and ‘n’ is the refractive index of the window material. 5 14.53 9.48 9.43 4.38 6 15.69 10.01 10.59 4.91 7 16.84 10.55 11.74 5.45 8 18.00 11.09 12.90 5.99 9 19.15 11.62 14.05 6.52 Aperture Width (X) vs Module Depth 25 Aperture Width (x) mm 20 15 10 5 Xmax Xmin 0 0 1 2 3 4 5 6 7 8 9 Module Depth (z) mm Aperture Height(Y) vs Module Depth 16 14 Aperture Height (Y) mm 12 10 8 6 4 Ymax Ymin 2 0 0 1 2 3 4 5 6 Module Depth (z) mm Window Material Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. 7 8 9 The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics. Recommended Plastic Materials: Material # Light Transmission Haze Refractive Index Lexan 141 88% 1% 1.586 Lexan 920A 85% 1% 1.586 Lexan 940A 85% 1% 1.586 Note: 920A and 940A are more flame retardant than 141. Recommended Dye: Violet #21051 (IR transmissant above 625 nm) Shape of the Window If the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. Flat Window Curved Front and Back Curved Front, Flat Back (First choice) (Second choice) (Do not use) From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. www.agilent.com/ semiconductors For product information and a complete list of distributors, please go to our web site. Data subject to change. Copyright © 2004 Agilent Technologies, Inc. August 19, 2004 5989-1520EN