SCBS702H − AUGUST 1997 − REVISED MARCH 2004
D Compatible With IEEE Std 1194.1-1991
D
D
D
D High-Impedance State During Power Up
(BTL)
LVTTL A Port, Backplane Transceiver Logic
(BTL) B Port
Open-Collector B-Port Outputs Sink
100 mA
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
D
D
D
and Power Down
Selectable Clock Delay
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
BIAS VCC Minimizes Signal Distortion
During Live Insertion/Withdrawal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1B2
GND
1B3
1B4
GND
1B5
1B6
GND
1B7
1B8
GND
1B9
2SEL2
2CLKAB
GND
2B2
2B3
GND
2B4
2B5
GND
2B6
2B7
GND
2B8
2AO5
2AI5
2AO6
2AI6
GND
2AO7
2AI7
2AO8
2AI8
GND
2AO9
2AI9
VCC (5 V)
2OEA
2OEA
2LEBA
2CLKBA
2CLKAB
2LEAB
2OEB
2OEB
BIAS VCC
2SEL1
GND
2B9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC(3.3 V)
VCC(5 V)
GND
1AO6
1AI6
1AO7
1AI7
GND
1AO8
1AI8
1AO9
1AI9
GND
2CLK
VCC(3.3 V)
2AO2
2AI2
GND
2AO3
2AI3
2AO4
2AI4
GND
VCC(5 V)
VCC(3.3 V)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1AI5
1AO5
1AI4
1AO4
GND
1AI3
1AO3
1AI2
1AO2
GND
1AI1
1AO1
VCC (5 V)
1OEA
1OEA
1LEBA
1CLKBA
1CLKAB
1LEAB
1OEB
1OEB
VREF
BG V CC
BG GND/GND
1B1
PCA PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
description/ordering information
The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers
are designed to translate signals between LVTTL and BTL environments. The device is designed specifically
to be compatible with IEEE Std 1194.1-1991 (BTL).
The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs
are in the high-impedance state.
The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC(5 V) typically
is less than 2.5 V, the B port is turned off.
The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer
to the MUX-MODE DELAY table).
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.
BG VCC and BG GND are the supply inputs for the bias generator.
VREF is an internally generated voltage source. It is recommended that VREF be decoupled with an external
0.1-µF capacitor.
Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies
greater than 50 MHz, or from AI to B or B to A0 at frequencies greater than 100 MHz.
ORDERING INFORMATION
PACKAGE†
TA
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C
TQFP − PCA
Tube
SN74FB1653PCA
FB1653
† Package drawings, standard packing quantities, thermal data, symbolization, and
PCB design guidelines are available at www.ti.com/sc/package.
Function Tables
TRANSCEIVER
INPUTS
FUNCTION
OEA
OEA
OEB
OEB
X
X
H
L
L
H
X
X
B data to A bus
L
H
H
L
A data to B bus, B data to A bus
X
X
L
X
X
X
X
H
H
X
X
X
X
L
X
X
A data to B bus
B-bus isolation
A-bus isolation
STORAGE MODE
INPUTS
2
FUNCTION
LE
CLK
H
X
Transparent
L
↑
Store data
L
L
Storage
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• DALLAS, TEXAS 75265
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
functional block diagram
1OEB
1OEB
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEA
1OEA
1AI1
81
80
83
82
85
84
87
86
90
1D
C2
76
1B1
C1
1D
1AO1
89
C2
C1
To Eight Other Channels
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3
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
functional block diagram (continued)
2OEB
2OEB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEA
2OEA
2SEL2
2SEL1
2CLK
2AI2
45
46
43
44
41
42
39
Delay3
40
M
U
X
63
Delay2
62
14
M
U
X
17
Delay1
1D
60
C2
C1
2AO2
1D
16
C2
C1
To Seven Other Channels
MUX-MODE DELAY
DELAY PATH†
INPUTS
2SEL1
2SEL2
2CLKAB TO 2CLKAB
2CLKAB TO 2CLK
L
L
No delay
No delay
L
H
No delay
Delay1
H
L
Delay2
Delay1
H
H
Delay3
Delay1
† Refer to delay1 through delay3 in the functional block diagram.
4
2CLKAB
48
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2B2
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: VCC(5 V), BIAS VCC, BG VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
VCC(3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 3.5 V
Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Voltage range applied to any B output in the disabled or power-off state . . . . . . . . . . . . . . . . . . −0.5 V to 3.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Current applied to any single output in the low state: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
VCC,
BG VCC,
BIAS VCC
VCC(3.3 V)
Supply voltage
Supply voltage
B port
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
IOH
Input clamp current
Except B port
B port
IOL
Except B port
High-level output current
Low-level output current
MIN
NOM
MAX
4.5
5
5.5
V
3
3.3
3.6
V
1.62
2.3
V
2
0.75
UNIT
1.47
0.8
V
−18
mA
AO port
−3
mA
AO port
24
B port
100
mA
TA
Operating free-air temperature
0
70
°C
NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to VCC(5 V) or GND, and
B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range
PARAMETER
B port
TEST CONDITIONS
MIN
TYP†
UNIT
VCC(5 V) = 4.5 V,
VCC(3.3 V) = 3.3 V
II = −18 mA
II = −40 mA
AO port
VCC(5 V) = 4.5 V,
VCC(3.3 V) = 3 V
IOH = −3 mA
AO port
VCC(5 V) = 4.5 V,
VCC(3.3 V) = 3 V
IOL = 24 mA
B port
VCC(5 V) = 4.5 V,
VCC(3.3 V) = 3 V
IOL = 80 mA
IOL = 100 mA
II
Except B port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VI = 5.5 V
50
µA
IIH‡
Except B port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VI = 2.7 V
50
µA
Except B port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VI = 0.5 V
−50
B port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VI = 0.75 V
−100
IOH
B port
VCC(5 V) = 0 to 5.5 V,
VCC(3.3 V) = 3.6 V
VO = 2.1 V
100
µA
IOZH
AO port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VO = 2.7 V
50
µA
IOZL
AO port
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.6 V
VO = 0.5 V
−50
µA
IOZPU
IOZPD
AO port
VCC = 0 to 2.1 V,
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V
VO = 0.5 V to 2.7 V
−50
µA
−50
µA
VIK
Except B port
VOH
VOL
IIL‡
AO port
−1.2
−0.5
2.5
ICC(5 V)
B port to AO port
Outputs disabled
V
V
0.35
0.75
0.5
1.1
V
1.15
A
µA
AI port to B port
145
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.3 V
IO = 0
VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.3 V
IO = 0
ICC(3.3 V)
B port to AO port
Ci
Control and AI inputs
Co
AO port
VI = 0.5 V or 2.5 V
VO = 0.5 V or 2.5 V
Cio
B port per
IEEE Std 1194.1-1991
VCC(5 V) = 0 to 5.5 V,
POST OFFICE BOX 655303
130
mA
120
VCC(3.3 V) = 3.3 V
† All typical values are at VCC(5 V) = 5 V and VCC(3.3 V) = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
6
MAX
• DALLAS, TEXAS 75265
1
mA
6.5
pF
3.5
pF
6.5
pF
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
live-insertion specifications over recommended operating free-air temperature range
PARAMETER
ICC (BIAS VCC)
VO
IO
B port
B port
TEST CONDITIONS
VCC(5 V) = 0 to 4.5 V,
VCC(3.3 V) = 3.3 V
MAX
UNIT
450
VCC(5 V) = 4.5 V to 5.5 V,
VCC(3.3 V) = 3.3 V
VB = 0 to 2 V,
A
µA
VI (BIAS VCC) = 4.5 V to 5.5 V
10
VCC(5 V) = 0,
VCC(3.3 V)= 0 V
VI (BIAS VCC) = 5 V
VCC(5 V) = 0,
VCC(3.3 V) = 0 V
VB = 1 V,
VCC(5 V) = 0 to 2.2 V,
VCC(3.3 V) = 3.3 V
VCC(5 V) = 0 to 5.5 V,
VCC(3.3 V) = 3.3 V
MIN
1.62
VI (BIAS VCC) = 4.5 V to 5.5 V
2.1
V
−1
A
µA
OEB = 0 to 5 V
100
OEB = 0 to 0.8 V
1
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
th
Hold time
LE high
3
CLK high or low
3
AI or B before LE↓
3.5
AI or B before CLK↑
3.5
AI or B after LE↓
AI or B after CLK↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
0.7
MAX
UNIT
90
MHz
ns
ns
ns
7
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
switching characteristics over recommended operating free-air temperature range,
VCC(5 V) = 5 V ± 0.5 V and VCC(3.3 V) = 3.3 V (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(p)†
FROM
(INPUT)
TO
(OUTPUT)
MAX
90
AI
B
LEAB
B
CLKAB
B
2CLKAB
(no delay)
2CLKAB
2CLKAB
(delay2)
2CLKAB
2CLKAB
(delay3)
2CLKAB
B
AO
LEBA
AO
CLKBA
AO
2CLKAB
(delay1)
2CLK
2CLKAB
(no delay)
2CLK
OEB or OEB
B
OEA or OEA
AO
OEA or OEA
AO
1.8
6.2
2.9
6.6
2.7
6.9
3.5
7.3
2.3
6.4
2.9
6.7
2.3
6
2.9
6.7
4.5
9.5
4.5
9.5
9.3
15.4
9.3
15.4
2
6.5
2
6.5
1.8
6.3
1.8
6.3
1.8
6.3
1.8
6.3
5.7
12.3
5.7
12.3
2
6.5
2
6.5
2.6
7
2.6
7
1.4
5.5
1.4
5.5
1.4
6.5
1.4
5.8
Pulse skew, AI to B or B to AO
1.6
Pulse skew, 2CLKAB to 2CLK
1.8
Pulse skew, CLKAB to B or CLKBA to AO
1.5
Pulse skew, CLKAB to 2CLKAB
1.4
tsk(HL), tsk(LH)†
Output skew, AI to B or B to AO
1
Output skew, nondelayed mode for 2CLKAB, CLKAB to AO
1
Output skew, nondelayed mode for 2CLKAB, CLKAB to B and 2CLKAB
1
tsk(o)‡
tt
Output skew, nondelayed mode for 2CLKAB, CLKAB to B and 2CLKAB
1.5
Transition time, B outputs (1.3 V to 1.8 V)
0.5
4.6
Transition time, AO outputs (10% to 90%)
0.4
4.2
tPR
B-port input pulse rejection
† Skew values are applicable for through mode only, with single-output switching.
‡ Skew values are applicable for CLK mode only, with all outputs simultaneously switching high-to-low or low-to-high.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
UNIT
MHz
tsk(p)
tsk(o)‡
8
MIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCBS702H − AUGUST 1997 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
2.1 V
500 Ω
From Output
Under Test
6V
Open
S1
GND
CL = 50 pF
(see Note A)
16.5 Ω
From Output
Under Test
500 Ω
S1
Open
6V
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR A OUTPUTS
tw
3V
1.5 V
Input
3V
1.5 V
Timing Input
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
1.5 V
Data Input
1.5 V
3V
1.5 V
Input
0V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0V
tPHL
tPLH
VOH
1.55 V
Output
1.55 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A to B)
3V
Output
Control
(see Note B)
1.5 V
0V
tPZL
2V
Input
1.55 V
1.55 V
1V
tPHL
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
tPLZ
3V
1.5 V
tPZH
tPLH
VOH
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
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9
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74FB1653PCA
ACTIVE
HLQFP
PCA
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74FB1653PCAG4
ACTIVE
HLQFP
PCA
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MHTQ003A – JANUARY 1995 – REVISED DECEMBER 1996
PCA (S-PQFP-G100)
PLASTIC QUAD FLATPACK (DIE DOWN)
0,27
0,17
0,50
75
0,08 M
51
Heat Slug
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040288 / B 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Thermally enhanced molded plastic package with a heat slug (HSL)
Falls within JEDEC MS-026
POST OFFICE BOX 655303
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