NSC 74F652SC

54F/74F651 # 54F/74F652
Transceivers/Registers
General Description
Features
These devices consist of bus transceiver circuits with
D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or
from internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
Y
Commercial
Package
Number
Military
74F651SPC
54F651SDM (Note 2)
74F651SC (Note 1)
54F651FM (Note 2)
54F651LM (Note 2)
Y
Y
Y
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Ð ’F651 inverting
Ð ’F652 non-inverting
Guaranteed 4000V minimum ESD protection
Package Description
N24C
24-Lead (0.300× Wide) Molded Dual-In-Line
J24F
24-Lead (0.300× Wide) Ceramic Dual-In-Line
M24B
24-Lead (0.300× Wide) Molded Small Outline, JEDEC
W24C
24-Lead Cerpack
E28A
24-Lead Ceramic Leadless Chip Carrier, Type C
N24C
24-Lead (0.300× Wide) Molded Dual-In-Line
J24F
24-Lead (0.300× Wide) Ceramic Dual-In-Line
M24B
24-Lead (0.300× Wide) Molded Small Outline, JEDEC
54F652FM (Note 2)
W24C
24-Lead Cerpack
54F652LM (Note 2)
E28A
24-Lead Ceramic Leadless Chip Carrier, Type C
74F652SPC
54F652SDM (Note 2)
74F652SC (Note 1)
Note 1:Devices also available in 13× reel. Use suffix e SCX
Note 2:Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB
Connection Diagrams
Pin Assignment
for LCC
Pin Assignment
DIP, SOIC and Flatpak
TL/F/9581 – 3
TL/F/9581 – 4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/9581
RRD-B30M75/Printed in U. S. A.
54F/74F651 # 54F/74F652 Transceivers/Registers
December 1994
Logic Symbols
IEEE/IEC
’F651
IEEE/IEC
’F652
TL/F/9581–1
TL/F/9581 – 10
’F651
’F652
TL/F/9581 – 11
TL/F/9581–2
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
HIGH/LOW
Input IIH/IIL
Output IOH/IOL
A0 – A7, B0 – B7 A and B Inputs/
1.0/1.0
20 mA/b0.6 mA
TRI-STATEÉ Outputs 600/106.6 (80) b12 mA/64 mA (48 mA)
CPAB, CPBA Clock Inputs
1.0/1.0
20 mA/b0.6 mA
SAB, SBA
Select Inputs
1.0/1.0
20 mA/b0.6 mA
OEAB, OEBA Output Enable Inputs
1.0/1.0
20 mA/b0.6 mA
2
Logic Diagrams
’F652
TL/F/9581 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
’F651
TL/F/9581 – 12
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
Functional Description
priate Clock Inputs (CPAB, CPBA) regardless of the Select
or Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceivers and receivers.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the approNote A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
Note C: Storage
Note D: Transfer Storage
Data to A or B
TL/F/9581 – 8
TL/F/9581–6
TL/F/9581– 7
OEAB
OEBA
CPAB
CPBA
TL/F/9581 – 9
SAB
SBA
OEAB
OEBA
CPAB
CPBA
SAB
SBA
OEAB
OEBA
CPAB
CPBA
SAB
SBA
X
H
L
X
X
X
OEAB
OEBA
CPAB
CPBA
SAB
SBA
L
L
X
X
X
L
H
H
X
X
L
X
L
X
X
L
X
X
H
L
H or L
H or L
H
X
L
H
L
L
X
X
FIGURE 1
Inputs
Inputs/Outputs (Note 1)
OEAB
OEBA
CPAB
CPBA
SAB
SBA
L
H
H or L
H or L
X
X
L
H
L
L
X
X
X
H
L
H or L
X
H
H
L
L
L
X
H or L
L
L
L
L
L
L
A0 thru A7
Operating Mode
B0 thru B7
Isolation
Input
Input
X
Input
Not Specified
Store A, Hold B
X
X
Input
Output
Store A in Both Registers
L
X
X
Not Specified
Input
Hold A, Store B
L
X
X
Output
Input
X
X
X
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
Stored A Data to B Bus and
Stored B Data to A Bus
H
L
H or L
H or L
H
Store A and B Data
Output
Input
Output
Input
Output
Output
Store B in Both Registers
Real-Time B Data to A Bus
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the
bus pins will be stored on every LOW to HIGH transition on the clock inputs.
4
Absolute Maximum Ratings (Note 1)
Voltage Applied to Output
in HIGH State (with VCC e 0V)
b 0.5V to VCC
Standard Output
b 0.5V to a 5.5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b 65§ C to a 150§ C
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
VCC Pin Potential to
Ground Pin
b 55§ C to a 125§ C
b 55§ C to a 175§ C
ESD Last Passing Voltage (Min)
b 55§ C to a 150§ C
Recommended Operating
Conditions
b 0.5V to a 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
4000V
b 0.5V to a 7.0V
Free Air Ambient Temperature
Military
Commercial
b 30 mA to a 5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
b 55§ C to a 125§ C
0§ C to a 70§ C
Supply Voltage
Military
Commercial
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
a 4.5V to a 5.5V
a 4.5V to a 5.5V
DC Electrical Characteristics
Symbol
54F/74F
Parameter
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
VOH
Output HIGH
Voltage
54F 10% VCC
74F 10% VCC
VOL
Output LOW
Voltage
54F 10% VCC
74F 10% VCC
IIH
Input HIGH
Current
IBVI
Typ
Units
VCC
Conditions
Max
2.0
V
Recognized as a HIGH Signal
0.8
V
b 1.2
V
Min
IIN e b18 mA (Non I/O Pins)
V
Min
IOH e b12 mA (An, Bn)
IOH e b15 mA (An, Bn)
0.55
0.55
V
Min
IOL e 48 mA (An, Bn)
IOL e 64 mA (An, Bn)
54F
74F
20.0
5.0
mA
Max
VIN e 2.7V
(Non I/O Pins)
Input HIGH Current
Breakdown Test
54F
74F
100
7.0
mA
Max
IBVIT
Input HIGH Current
Breakdown (I/O)
54F
74F
1.0
0.5
mA
Max
ICEX
Output HIGH
Leakage Current
54F
74F
250
50
mA
Max
VID
Input Leakage
Test
74F
V
0.0
IID e 1.9 mA
All Other Pins Grounded
IOD
Output Leakage
Circuit Current
74F
3.75
mA
0.0
VIIOD e 150 mV
All Other Pins Grounded
IIL
Input LOW Current
b 0.6
mA
Max
VIN e 0.5V (Non I/O Pins)
IIH a IOZH
Output Leakage Current
70
mA
Max
VOUT e 2.7V (An, Bn)
IIL a IOZL
Output Leakage Current
b 650
mA
Max
VOUT e 0.5V (An, Bn)
IOS
Output Short-Circuit Current
b 225
mA
Max
VOUT e 0V
IZZ
Bus Drainage Test
500
mA
0.0V
VOUT e 5.25V
ICCH
Power Supply Current
105
135
mA
Max
VO e HIGH
ICCL
Power Supply Current
118
150
mA
Max
VO e LOW
ICCZ
Power Supply Current
115
150
mA
Max
VO e HIGH Z
2.0
2.0
4.75
b 100
5
Recognized as a LOW Signal
VIN e 7.0V
VIN e 5.5V
(An, Bn)
VOUT e VCC
AC Electrical Characteristics
Symbol
Parameter
74F
54F
74F
TA e a 25§ C
VCC e a 5.0V
CL e 50 pF
TA, VCC e Mil
CL e 50 pF
TA, VCC e Com
CL e 50 pF
Min
Max
Min
Max
75
Min
Units
Max
fmax
Max. Clock Frequency
90
90
tPLH
tPHL
Propagation Delay
Clock to Bus
2.0
2.0
7.0
8.0
2.0
2.0
8.5
9.5
2.0
2.0
8.0
9.0
MHz
ns
tPLH
tPHL
Propagation Delay
Bus to Bus (’F651)
2.0
1.0
8.5
7.5
1.0
1.0
9.0
8.0
2.0
1.0
9.0
8.0
ns
tPLH
tPHL
Propagation Delay
Bus to Bus (’F652)
1.0
1.0
7.0
6.5
1.0
1.0
8.0
8.0
1.0
1.0
7.5
7.0
ns
tPLH
tPHL
Propagation Delay
SBA or SAB to A or B
2.0
2.0
8.5
8.0
2.0
2.0
11.0
10.0
2.0
2.0
9.5
9.0
ns
AC Operating Requirements
Symbol
Parameter
74F
54F
74F
TA e a 25§ C
VCC e a 5.0V
TA, VCC e Mil
TA, VCC e Com
Min
Max
Min
Max
Min
Max
Units
tPZH
tPZL
Enable Time
*OEBA to A
2.0
2.0
9.5
12.0
2.0
2.0
10.0
10.0
2.0
2.0
10.0
12.5
tPHZ
tPLZ
Disable Time
*OEBA to A
1.0
2.0
7.5
8.5
1.0
1.0
9.0
9.0
1.0
2.0
8.0
9.0
tPZH
tPZL
Enable Time
OEAB to B
2.0
3.0
9.5
13.0
2.0
2.0
10.0
12.0
2.0
3.0
10.0
14.0
tPHZ
tPLZ
Disable Time
OEAB to B
2.0
2.0
9.0
10.5
1.0
1.0
9.0
12.0
2.0
2.0
10.0
11.0
ts(H)
ts(L)
Setup Time, HIGH or
LOW, Bus to Clock
5.0
5.0
5.0
5.0
5.0
5.0
ns
th(H)
th(L)
Hold Time, HIGH or
LOW, Bus to Clock
2.0
2.0
2.5
2.5
2.0
2.0
ns
tw(H)
tw(L)
Clock Pulse Width
HIGH or LOW
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F
651/652
Temperature Range Family
74F e Commercial
54F e Military
S
C
X
Special Variations
QB e Military grade device with
environmental and burn-in
processing
X e Devices shipped in 13× reel
Device Type
Package Code
SP e Slim Plastic DIP
SD e Slim Ceramic DIP
S e Small Outline (SOIC)
Temperature Range
C e Commercial (0§ C to a 70§ C)
M e Military (b55§ C to a 125§ C)
6
7
Physical Dimensions inches (millimeters)
28 Lead Ceramic Leadless Chip Carrier, Type C
NS Package Number E28A
24 Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD)
NS Package Number J24F
8
Physical Dimensions inches (millimeters) (Continued)
24 Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M24B
24 Lead (0.300× Wide) Molded Dual-In-Line Package (SP)
NS Package Number N24C
9
54F/74F651 # 54F/74F652 Transceivers/Registers
Physical Dimensions inches (millimeters) (Continued)
24 Lead Cerpack
NS Package Number W24C
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