54F/74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Y Commercial Package Number Military 74F273PC 54F273DM (Note 2) Y Y Y Y Y Y Y Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered, asynchronous Master Reset See ’F377 for clock enable version See ’F373 for transparent latch version See ’F374 for TRI-STATEÉ version Guaranteed 4000V minimum ESD protection Package Description N20A 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F273SC (Note 1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F273SJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F273FM (Note 2) W20A 20-Lead Cerpack 54F273LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9511 – 3 TL/F/9511 – 5 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9511 RRD-B30M75/Printed in U. S. A. 54F/74F273 Octal D Flip-Flop May 1995 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9511 – 2 TL/F/9511–1 Unit Loading/Fan Out 54F/74F Pin Names D 0 – D7 MR CP Q0 – Q7 Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA Mode Select-Function Table Inputs Operating Mode Output MR CP Dn Qn Reset (Clear) L X X L Load ‘1’ H L h H Load ‘0’ H L l L H e HIGH Voltage Level steady state h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L e LOW Voltage Level steady state I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial L e LOW-to-HIGH clock transition Logic Diagram TL/F/9511 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Mil 10% VCC 5% VCC Output LOW Voltage Mil 10% VCC 5% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V 2.5 2.5 2.7 Min IIN e b18 mA IOH e b1 mA V Min 0.5 0.5 0.5 V Min 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All other pins grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All other pins grounded IIL Input LOW Current VOL IOS Output Short-Circuit Current ICCH ICCL Power Supply Current 4.75 b 60 3 IOL e 20 mA b 0.6 mA Max VIN e 0.5V b 150 mA Max VOUT e 0V 44 56 mA Max CP e L Dn e MR e HIGH AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Typ Max Min Max 95 Min Units Max fmax Maximum Clock Frequency 160 130 tPLH tPHL Propagation Delay Clock to Output 3.0 4.0 7.0 9.00 2.5 3.0 9.5 11.0 2.5 3.5 7.5 9.0 MHz ns tPLH tPHL Propagation Delay MR to Output 4.5 9.5 3.0 11.0 4.0 10.0 ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW Data to CP 3.0 3.5 3.5 4.0 3.0 3.5 th(H) th(L) Hold Time, HIGH or LOW Data to CP 0.5 1.0 1.0 1.0 0.5 1.0 tw(L) MR Pulse Width, LOW 6.0 4.0 6.0 ns tw(H) tw(L) CP Pulse Width HIGH or LOW 6.0 6.0 5.0 5.0 6.0 6.0 ns trec Recovery Time, MR to CP 3.0 4.5 3.5 ns ns Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 74F 273 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13× reels QB e Military grade with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ F e Flatpak L e Leadless Chip Carrier (LCC) Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) 4 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (LCC) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M20B 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M20D 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 Lit. Ý 114645 54F/74F273 Octal D Flip-Flop Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. 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Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.