54F/74F534 Octal D-Type Flip-Flop with TRI-STATEÉ Outputs General Description Features The ’F534 is a high speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The ’F534 is the same as the ’F374 except that the outputs are inverted. Y Commercial Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock TRI-STATE outputs for bus-oriented applications Guaranteed 4000V minimum ESD protection Package Number Military 74F534PC N20A 54F534DM (Note 2) Package Description 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F534SC (Note 1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F534SJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F534FM (Note 2) W20A 20-Lead Cerpack 54F534LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SCX, and SJX Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB Logic Symbols IEEE/IEC TL/F/9549 – 1 TL/F/9549 – 5 Unit Loading/Fan Out 54F/74F Pin Names D0 – D7 CP OE O0 – O 7 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs 1.0/1.0 20 mA/b0.6 mA Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA TRI-STATE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA Complementary TRI-STATE Outputs 150/40(33.3) b3 mA/24 mA (20 mA) TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9549 RRD-B30M75/Printed in U. S. A. 54F/74F534 Octal D-Type Flip-Flop with TRI-STATE Outputs May 1995 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9549 – 3 TL/F/9549–2 Functional Description The ’F534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs Output CP OE D O L L L X L L L H H L X X L H O0 Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition Z e High Impedance O0 e Value stored from previous clock cycle Logic Diagram TL/F/9549 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Current Applied to Output in LOW State (Max) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin twice the rated IOL (mA) ESD Last Passing Voltage (Min) Free Air Ambient Temperature Military Commercial b 30 mA to a 5.0 mA b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 0.5V to VCC b 0.5V to a 5.5V a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Units 2.0 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max V 0.8 V b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IOL e 20 mA IOL e 24 mA IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 1.50 mA All Other Pins Grounded IIL Input LOW Current b 0.6 mA Max VIN e 0.5V IOZH Output Leakage Current 50 mA Max VOUT e 2.7V IOZL Output Leakage Current b 50 mA Max VOUT e 0.5V IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V IZZ Bus Drainage Test 500 mA 0.0V VOUT e 5.25V ICCZ Power Supply Current 86 mA Max VO e HIGH Z 4.75 b 60 55 3 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Typ Max Min Max 60 Min Units Max fmax Maximum Clock Frequency 100 70 tPLH tPHL Propagation Delay CP to On 4.0 4.0 6.5 6.5 8.5 8.5 4.0 4.0 10.5 11.0 4.0 4.0 10.0 10.0 MHz tPZH tPZL Output Enable Time 2.0 2.0 9.0 5.8 11.5 7.5 2.0 2.0 14.0 10.0 2.0 2.0 12.5 8.5 tPHZ tPLZ Output Disable Time 1.5 1.5 5.3 4.3 7.0 5.5 1.5 1.5 8.0 7.5 1.5 1.5 8.0 6.5 ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to CP 2.0 2.0 2.0 2.5 2.0 2.0 th(H) th(L) Hold Time, HIGH or LOW Dn to CP 2.0 2.0 2.0 2.5 2.0 2.0 tw(H) tw(L) CP Pulse Width HIGH or LOW 7.0 6.0 7.0 6.0 7.0 6.0 Units Max ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 534 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing Device Type Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 4 Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC NS Package Number M20B 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M20D 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 54F/74F534 Octal D-Type Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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