54F/74F574 Octal D-Type Flip-Flop with TRI-STATEÉ Outputs General Description Features The ’F574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identical to the ’F374 except for the pinouts. Y Commercial Y Y Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F374 TRI-STATE outputs for bus-oriented applications Package Number Military Package Description N20A 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F574SC (Note 1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F574SJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F574FM (Note 2) W20A 20-Lead Cerpack 54F574LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F574PC 54F574DM (Note 2) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9567 – 1 TL/F/9567 – 4 Unit Loading/Fan Out 54F/74F Pin Names D0 – D7 CP OE O0 – O7 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs Clock Pulse Input (Active LOW) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs 1.0/1.0 1.0/1.0 1.0/1.0 150/40 (33.3) 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 3 mA/24 mA (20 mA) TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9567 RRD-B30M75/Printed in U. S. A. 54F/74F574 Octal D-Type Flip-Flop with TRI-STATE Outputs May 1995 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9567 – 3 TL/F/9567–2 Functional Description Function Table The ’F574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Inputs Internal Outputs OE CP D Q O H H H H L L L L H H L L L L H H L H L H L H L H NC NC L H L H NC NC Z Z Z Z L H NC NC Function Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TL/F/9567 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Units 2.0 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH IOL e 20 mA IOL e 24 mA e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 mA Max VIN e 0.5V IOZH Output Leakage Current 50 mA Max VOUT e 2.7V IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCZ Power Supply Current 4.75 b 60 55 3 b 50 mA Max VOUT e 0.5V b 150 mA Max VOUT e 0V 500 mA 0.0V VOUT e 5.25V 86 mA Max VO e HIGH Z AC Electrical Characteristics Symbol Parameter Min 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Typ Max Min Max 60 Min Units Max fmax Maximum Clock Frequency 100 70 tPLH tPHL Propagation Delay CP to On 2.5 2.5 5.3 5.3 8.5 8.5 2.5 2.5 9.5 9.5 2.5 2.5 8.5 8.5 MHz tPZH tPZL Output Enable Time 3.0 3.0 5.5 6.0 9.0 9.0 2.5 2.5 10.5 10.5 2.5 2.5 10.0 10.0 tPHZ tPLZ Output Disable Time 1.5 1.5 3.3 2.8 5.5 5.5 1.5 1.5 7.0 7.0 1.5 1.5 6.5 6.5 ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Set-up Time, HIGH or LOW Dn to CP 2.5 2.0 3.0 2.5 2.5 2.0 th(H) th(L) Hold Time, HIGH or LOW Dn to CP 2.0 2.0 2.0 2.0 2.0 2.0 tw(H) tw(L) CP Pulse Width HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 4 Units Max ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 574 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing Device Type Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline JEDEC SJ e Small Outline SOIC EIAJ Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 5 Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M20B 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ NS Package Number M20D 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 7 54F/74F574 Octal D-Type Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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