LM4852 Integrated Audio Amplifier System General Description Key Specifications The LM4852 is an audio power amplifier system capable of delivering 1.1W (typ) of continuous average power into a mono 8Ω bridged-tied load (BTL) with 1% THD+N and 60mW (typ) per channel of continuous average power into stereo 32Ω single-ended (SE) loads with 0.5% THD+N, using a 5V power supply. n THD+N at 1kHz, 1.1W into 8Ω BTL n THD+N at 1kHz, 60mW into 32Ω SE n Single Supply Operation The LM4852 features a 32 step digital volume control and eight distinct output modes. The digital volume control and output modes are programmed through a two-wire I2C compatible control interface, that allows flexibility in routing and mixing audio channels. The LM4852 has 3 channels: one pair for a two-channel stereo signal and the third for a single-channel mono input. The LM4852 is designed for cellular phone, PDA, and other portable handheld applications. It delivers high quality output power from a surface-mount package and requires only seven external components. The industry leading micro SMD package only utilizes 2mm x 2.3mm of PCB space, making the LM4852 the most space efficient audio sub system available today. 1.0% (typ) 0.5% (typ) 2.6 to 5.0V Features n 1.1W (typ) output power with 8Ω mono BTL load n 60mW (typ) output power with stereo 32Ω SE loads n I2C programmable 32 step digital volume control (-40.5dB to +6dB) n Eight distinct output modes n micro-SMD and LLP surface mount packaging n "Click and Pop" suppression circuitry n Thermal shutdown protection n Low shutdown current (0.1uA, typ) Applications n Moblie Phones n PDAs Typical Application 20060632 FIGURE 1. Typical Audio Amplifier Application Circuit Boomer ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200606 www.national.com LM4852 Integrated Audio Amplifier System May 2004 LM4852 Connection Diagrams 18-Bump micro SMD Marking (ITL) 200606E4 Top View X - Date Code T - Die Traceability G - Boomer Family B7 - LM4852ITL 200606A9 Top View (Bump-side down) Order Number LM4852ITL See NS Package Number TLA18AAA LLP Package 24 Lead LLP Marking 20060611 NS: Standard NS Logo U: Wafer Fab Code Z: Assembly Plant Code XY: Date Code TT: Die Traceability L4852LQ: LM4852LQ 200606D3 Top View Order Number LM4852LQ See NS Package Number LQA24A for Exposed-DAP LLP www.national.com 2 Thermal Resistance If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 6.0V Storage Temperature 42˚C/W 3.0˚C/W θJA (typ) - TLA18AAA 48˚C/W (Note 9) θJC (typ) - TLA18AAA 23˚C/W (Note 9) −65˚C to +150˚C ESD Susceptibility (Note 4) 2.0kV ESD Machine model (Note 7) 200V Junction Temperature (TJ) θJA (typ) - LQA24A θJC (typ) - LQA24A Operating Ratings (Note 3) 150˚C Solder Information (Note 1) Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C Temperature Range −40˚C to 85˚C Supply Voltage VDD 2.6V ≤ VDD ≤ 5.5V Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices. Electrical Characteristics 5.0 V (Notes 3, 8) The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified. Symbol IDD Parameter Supply Current Conditions LM4852 Units (Limits) Typical (Note 5) Limits (Notes 6, 11) Output modes 2, 4, 6 VIN = 0V; No loads 5 9 mA (max) Output modes 2, 4, 6 VIN = 0V; Loaded (Figure 1) 6 10 mA (max) Output modes 1, 3, 5, 7 VIN = 0V; No loads 7.5 11 mA (max) Output modes 1, 3, 5, 7 VIN = 0V; Loaded (Figure 1) 8.5 12 mA (max) ISD Shutdown Current Output mode 0 0.1 2.0 µA (max) VOS Output Offset Voltage VIN = 0V 5.0 40 mV (max) SPKROUT; RL = 4Ω THD+N = 1%; f = 1kHz, LM4852LQ 1.5 SPKROUT; RL = 8Ω THD+N = 1%; f = 1kHz 1.1 0.8 W (min) ROUT and LOUT; RL = 32Ω THD+N = 0.5%; f = 1kHz 60 45 mW (min) SPKROUT f = 20Hz to 20kHz POUT = 400mW; RL = 8Ω 0.5 % ROUT and LOUT f = 20Hz to 20kHz POUT = 15mW; RL = 32Ω 0.5 % A-weighted (Note 10) 26 µV PO THD+N NOUT Output Power Total Harmonic Distortion Plus Noise Output Noise 3 W www.national.com LM4852 Absolute Maximum Ratings (Note 2) LM4852 Electrical Characteristics 5.0 V (Notes 3, 8) (Continued) The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified. Symbol Parameter Power Supply Rejection Ratio SPKROUT PSRR Power Supply Rejection Ratio ROUTand LOUT Conditions LM4852 Units (Limits) Typical (Note 5) Limits (Notes 6, 11) Output Mode 1,7 64 57 Output Mode 3 58 dB Output Mode 5 55 dB VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF All audio inputs terminated into 50Ω; Output referred Gain (BTL) = 6dB dB (min) VRIPPLE = 200mVPP; f = 217Hz CB = 1.0µF All audio inputs terminated into 50Ω; Output referred Maximum gain setting Output Mode 2 68 59 Output Mode 4 60 54 dB (min) dB (min) Output Mode 6, 7 56 51 dB (min) VIH Logic High Input Voltage 0.7 x VDD VDD V (min) V (max) VIL Logic Low Input Voltage 0.4 GND V (max) V (min) Digital Volume Range (RIN and LIN) Input referred minimum gain -40.5 -41.1 -39.9 dB (min) dB (max) Input referred maximum gain 6.0 5.4 6.6 dB (min) dB (max) ± 0.1 ± 0.6 dB ( max) 6 5.4 6.6 dB (min) dB (max) 20 15 25 kΩ (min) kΩ (max) Maximum gain setting 30 22.5 37.5 kΩ (min) kΩ (max) Mininum gain setting 100 75 125 kΩ (min) kΩ (max) 170 Digital Volume Stepsize 1.5 Digital Volume Stepsize Error Phone In Volume BTL gain from Phone In to SPKROUT Mute Attenuation Output Mode 1, 3, 5 Phone In Input Impedance dB 100 RIN and LIN Input Impedance dB TSD Thermal Shutdown Temperature 150 ˚C (min) t1 SCL (Clock) Period 2.5 µs (min) t2 SDA to SCL Set-up Time 100 ns (min) t3 Data Out Stable Time 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) www.national.com 4 LM4852 Electrical Characteristics 3.0V (Notes 2, 8) The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified. Symbol IDD Parameter Supply Current Conditions LM4852 Units (Limits) Typical (Note 5) Limits (Notes 6, 11) Output modes 2, 4, 6 VIN = 0V; No loads 4 7 mA (max) Output modes 2, 4, 6 VIN = 0V; Loaded (Figure 1) 5 8 mA (max) 6.5 10 mA (max) 7 11 mA (max) Output modes 1, 3, 5, 7 VIN = 0V; No loads Output modes 1, 3, 5, 7 VIN = 0V; Loaded (Figure 1) ISD Shutdown Current Output mode 0 0.1 2.0 µA (max) VOS Output Offset Voltage VIN = 0V 5.0 40 mV (max) SPKROUT; RL = 4Ω THD+N = 1%; f = 1kHz, LM4852LQ 430 SPKROUT; RL = 8Ω THD+N = 1%; f = 1kHz 340 300 mW (min) ROUT and LOUT; RL = 32Ω THD+N = 0.5%; f = 1kHz 22 18 mW (min) SPKROUT f = 20Hz to 20kHz POUT = 150mW; RL = 8Ω 0.5 % ROUT and LOUT f = 20Hz to 20kHz POUT = 10mW; RL = 32Ω 0.5 % A-weighted (Note 10) 26 µV PO THD+N NOUT Output Power Total Harmonic Distortion Plus Noise Output Noise PSRR Power Supply Rejection Ratio SPKROUT Power Supply Rejection Ratio ROUTand LOUT mW VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF All audio inputs terminated into 50Ω; Output referred Gain (BTL) = 6dB Output Mode 1, 7 64 Output Mode 3 58 57 dB (min) dB Output Mode 5 55 dB VRIPPLE = 200mVPP; f = 217Hz, CB = 1.0µF All audio inputs terminated into 50Ω; Output referred Maximum gain setting Output Mode 2 68 60 Output Mode 4 60 55 dB (min) dB (min) Output Mode 6, 7 56 52 dB (min) VIH Logic High Input Voltage 0.7 x VDD VDD V (min) V (max) VIL Logic Low Input Voltage 0.4 GND V (max) V (min) 5 www.national.com LM4852 Electrical Characteristics 3.0V (Notes 2, 8) (Continued) The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified. Symbol Parameter Conditions LM4852 Typical (Note 5) Digital Volume Range (RIN and LIN) Limits (Notes 6, 11) Units (Limits) Input referred minimum gain -40.5 -41.1 -39.9 dB (min) dB (max) Input referred maximum gain 6.0 5.4 6.6 dB (min) dB (max) ± 0.1 ± 0.6 dB ( max) 6 5.4 6.6 dB (min) dB (max) 20 15 25 kΩ (min) kΩ (max) Maximum gain setting 30 22.5 37.5 kΩ (min) kΩ (max) Mininum gain setting 100 75 125 kΩ (min) kΩ (max) 170 Digital Volume Stepsize 1.5 Digital Volume Stepsize Error Phone In Volume BTL gain from Phone In to SPKROUT Mute Attenuation Output Mode 1, 3, 5 Phone In Input Impedance dB 100 RIN and LIN Input Impedance dB TSD Thermal Shutdown Temperature 150 ˚C (min) t1 SCL (Clock) Period 2.5 µs (min) t2 SDA to SCL Set-up Time 100 ns (min) t3 Data Out Stable Time 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) Note 2: Absolute Maximum Rating indicate limits beyond which damage to the device may occur. Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 5: Typical specifications are specified at +25˚C and represent the most likely parametric norm. Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 7: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω). Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 9: The given θJA and θJC are for an LM4852 mounted on a demonstration board with a 4in2 area of 1oz printed circuit board copper ground plane. Note 10: Please refer to the Output Noise vs Output Mode table in the Typical Performance Characteristics section for more details. Note 11: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis. www.national.com 6 LM4852 External Components Description Components Functional Description 1. CIN This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier’s input terminals. CIN also creates a highpass filter with the internal resistor Ri (Input Impedance) at fc = 1/(2πRiCIN). 2. CS This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps maintain the LM4852’s PSRR. 3. CB This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4852’s PSRR. Typical Performance Characteristics THD+N vs Frequency LM4852LQ THD+N vs Frequency LM4852LQ 200606I2 200606I3 THD+N vs Frequency THD+N vs Frequency 200606I4 20060612 7 www.national.com LM4852 Typical Performance Characteristics (Continued) THD+N vs Frequency THD+N vs Frequency 20060613 20060614 THD+N vs Frequency THD+N vs Frequency 200606I6 20060615 THD+N vs Frequency THD+N vs Frequency 20060616 www.national.com 20060617 8 LM4852 Typical Performance Characteristics (Continued) THD+N vs Output Power LM4852LQ THD+N vs Output Power LM4852LQ 200606I7 200606I8 THD+N vs Output Power THD+N vs Output Power 200606I9 200606H2 THD+N vs Output Power THD+N vs Output Power 200606J0 200606H3 9 www.national.com LM4852 Typical Performance Characteristics (Continued) Power Supply Rejection Ratio Power Supply Rejection Ratio 200606J1 200606J2 Power Supply Rejection Ratio Power Supply Rejection Ratio 200606J3 200606J4 Power Supply Rejection Ratio Power Supply Rejection Ratio 200606J5 www.national.com 200606J6 10 LM4852 Typical Performance Characteristics (Continued) Output Power vs Supply Voltage Output Power vs Supply Voltage 200606H7 200606D7 Output Power vs Load Resistance Output Power vs Load Resistance 200606D9 200606H8 Power Dissipation vs Output Power Power Dissipation vs Output Power 200606E1 200606H9 11 www.national.com LM4852 Typical Performance Characteristics (Continued) Supply Current vs Supply Voltage Channel Separation 20060618 20060619 Frequency Response Frequency Response 200606J7 200606I0 Output Noise vs Output Mode (VDD = 3V, 5V) Output Mode SPKROUT Output Noise (µV) LOUT/ROUT Output Noise (µV) 1 26 X 2 X 15 (G = 6dB) 3 30 15 (G = 6dB) 4 X 20 (G = 6dB) 5 40 20 (G = 6dB) 6 X 25 (G = 6dB) 7 26 25 (G = 6dB) G = LIN / RIN gain setting A - weighted filter used www.national.com 12 I2C PIN DESCRIPTION The “start” signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. SDA: This is the serial data input pin. SCL: This is the clock input pin. ADR: This is the address select input pin. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the clock level is high. After the last bit of the address is sent, the master checks for the LM4852’s acknowledge. The master releases the data line high (through a pullup resistor). Then the master sends a clock pulse. If the LM4852 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not low, then the master should send a “stop” signal (discussed later) and abort the transfer. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. After the data byte is sent, the master must generate another acknowledge to see if the LM4852 received the data. If the master has more data bytes to send to the LM4852, then the master can repeat the previous two steps until all data bytes have been sent. The “stop” signal ends the transfer. To signal “stop”, the data signal goes high while the clock signal is high. 2 I C INTERFACE The LM4852 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: clock and data. The clock line is uni-directional. The data line is bi-directional (open-collector) with a pullup resistor (typically 10kΩ).The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4852. The I2C address for the LM4852 is determined using the ADR pin. The LM4852’s two possible I2C chip addresses are of the form 110110X10 (binary), where the X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high. If the I2C interface is used to address a number of chips in a system and the LM4852’s chip address can be changed to avoid address conflicts. The timing diagram for the I2C is shown in Figure 2. The data is latched in on the stable high level of the clock and the data line should be held high when not in use. The timing diagram is broken up into six major sections: 200606F5 FIGURE 2. I2C Bus Format 200606F4 FIGURE 3. I2C Timing Diagram 13 www.national.com LM4852 Application Information LM4852 Application Information (Continued) TABLE 1. Data Register DATA BIT D7 D6 Function D5 D4 D3 D2 Volume Control D1 D0 Output Mode Control Name V4 V3 V2 V1 V0 M2 M1 M0 Default 0 0 0 0 0 0 0 0 TABLE 2. Output Mode Selection M2 M1 M0 Handsfree Speaker Output Right Headphone Output Left Headphone Output Output Mode Number 0 0 0 SD 0 0 1 6dB x P SD SD 0 MUTE MUTE 0 1 0 SD 1 P P 0 1 1 G (R+L) 2 MUTE MUTE 3 1 0 0 SD GxR Gx L 4 1 0 1 G (R+L) + 6dB x P MUTE MUTE 5 1 1 0 SD (GxR) + P (G x L) + P 6 1 1 1 6dB x P (GxR) + P (G x L) + P 7 P = Phone In R = RIN L = LIN SD = Shutdown MUTE = Mute Mode G = LIN and RIN gain setting www.national.com 14 LM4852 Application Information (Continued) TABLE 3. Volume Control Gain (dB) V4 V3 V2 V1 V0 0 0 0 0 0 -40.5 0 0 0 0 1 -39.0 0 0 0 1 0 -37.5 0 0 0 1 1 -36.0 0 0 1 0 0 -34.5 0 0 1 0 1 -33.0 0 0 1 1 0 -31.5 0 0 1 1 1 -30.0 0 1 0 0 0 -28.5 0 1 0 0 1 -27.0 0 1 0 1 0 -25.5 0 1 0 1 1 -24.0 0 1 1 0 0 -22.5 0 1 1 0 1 -21.0 0 1 1 1 0 -19.5 0 1 1 1 1 -18.0 1 0 0 0 0 -16.5 1 0 0 0 1 -15.0 1 0 0 1 0 -13.5 1 0 0 1 1 -12.0 1 0 1 0 0 -10.5 1 0 1 0 1 -9.0 1 0 1 1 0 -7.5 1 0 1 1 1 -6.0 1 1 0 0 0 -4.5 1 1 0 0 1 -3.0 1 1 0 1 0 -1.5 1 1 0 1 1 0.0 1 1 1 0 0 1.5 1 1 1 0 1 3.0 1 1 1 1 0 4.5 1 1 1 1 1 6.0 EXPOSED-DAP MOUNTING CONSIDERATIONS The LM4852’s exposed-DAP (die attach paddle) package (LD) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a low voltage audio power amplifier that produces 1.1W dissipation in a 8Ω load at ≤ 1% THD+N. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4852’s high power performance and activate unwanted, though necessary, thermal shutdown protection. The LD package must have its DAP soldered to a copper pad on the PCB. The DAP’s PCB copper pad is then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the G case of a two-sided or multi-layer PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance, however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with 6 (3 X 2) (LD) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plugging and tenting the vias with plating and solder mask, respectively. Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load. Heatsink areas not placed on the same PCB layer as the LM4852 should be 5in2 (min) for the same supply voltage and load resistance. The last two area recommendations apply for 25˚C ambient temperature. Increase the area to compensate for ambient temperatures above 25˚C. In all circumstances and under all conditions, the junction temperature must be held below 15 www.national.com LM4852 Application Information pacitor in a typical single-ended configuration forces a single-supply amplifier’s half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. (Continued) 150˚C to prevent activating the LM4852’s thermal shutdown protection. Further detailed and specific information concerning PCB layout and fabrication and mounting an LD (LLP) is found in National Semiconductor’s AN1187. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4852 has a pair of bridged-tied amplifiers driving a handsfree speaker, SPKROUT. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation (2), assuming a 5V power supply and an 8Ω load, the maximum SPKROUT power dissipation is 634mW. Power dissipated by a load is a function of the voltage swing across the load and the load’s impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load’s connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω trace resistance reduces the output power dissipated by a 4Ω load from 1.7W to 1.6W. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply’s output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. PDMAX-SPKROUT = 4(VDD)2 / (2π2 RL): Bridge Mode (2) The LM4852 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum internal power dissipation for ROUT and LOUT is given by equation (3) and (4). From Equations (3) and (4), assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW, or 80mW total. PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode (3) PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode (4) BRIDGE CONFIGURATION EXPLANATION As shown in Figure 1, the LM4852 consists of three pairs of output amplifier blocks (A4-A6). Amplifier block A6 consists of a bridged-tied amplifier pair that drives SPKROUT. The LM4852 drives a load, such as a speaker, connected between outputs, SPKROUT+ and SPKROUT-. In the amplifier block A6, the output of the amplifier that drives SPKROUTserves as the input to the unity gain inverting amplifier that drives SPKROUT+. The maximum internal power dissipation of the LM4852 occurs when all 3 amplifiers pairs are simultaneously on; and is given by Equation (5). PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT The maximum power dissipation point given by Equation (5) must not exceed the power dissipation given by Equation (6): This results in both amplifiers producing signals identical in magnitude, but 180˚ out of phase. Taking advantage of this phase difference, a load is placed between SPKROUT- and SPKROUT+ and driven differentially (commonly referred to as ’bridge mode’). This results in a differential or BTL gain of: AVD = 2(Rf / Ri) = 2 PDMAX’ = (TJMAX - TA) / θJA (6) The LM4852’s TJMAX = 150˚C. In the ITL package, the LM4852’s θJA is 48˚C/W. In the LD package soldered to a DAP pad that expands to a copper area of 2.5in2 on a PCB, the LM4852’s θJA is 42˚C/W. At any given ambient temperature TA, use Equation (6) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (6) and substituting PDMAX-TOTAL for PDMAX’ results in Equation (7). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4852’s maximum junction temperature. (1) Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier’s output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing SPKROUT- and SPKROUT+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling cawww.national.com (5) TA = TJMAX - PDMAX-TOTAL θJA (7) For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows maxi- 16 large, however, increases turn-on time and can compromise the amplifier’s click and pop performance. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints. (Continued) mum stereo power dissipation without exceeding the maximum junction temperature is approximately 104˚C for the IBL package. TJMAX = PDMAX-TOTAL θJA + TA (8) SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 3). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation (9). Equation (8) gives the maximum junction temperature TJMAX. If the result violates the LM4852’s 150˚C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (5) is greater than that of Equation (6), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and θSA is the sink-toambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. fc = 1 / (2πRiCi) (9) As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation (9) is 0.063µF. The 0.22µF Ci shown in Figure 1 allows the LM4852 to drive high efficiency, full range speaker whose response extends below 40Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM4852 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4852’s outputs ramp to their quiescent DC voltage (nominally VDD/ 2), the smaller the turn-on pop. Choosing CB equal to 1.0µF along with a small value of Ci (in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB’s value should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated when power is first applied or the LM4852 resumes operation after shutdown. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator’s output, reduce noise on the supply line, and improve the supply’s transient response. However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected between the LM4852’s supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4852’s power supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage’s stability and improves the amplifier’s PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too 17 www.national.com LM4852 Application Information LM4852 Demonstration ITL Board Layout 20060605 20060604 Recommended ITL PC Board Layout: Top Overlay Layer Recommended ITL PC Board Layout: Top Layer 20060603 20060602 Recommended ITL PC Board Layout: Middle 1 Layer Recommended ITL PC Board Layout: Middle 2 Layer 20060601 Recommended ITL PC Board Layout: Bottom Layer www.national.com 18 LM4852 Demonstration LQ Board Layout 20060610 20060609 Recommended LQ PC Board Layout: Top Overlay Layer Recommended LQ PC Board Layout: Top Layer 20060608 20060607 Recommended LQ PC Board Layout: Middle 1 Layer Recommended LQ PC Board Layout: Middle 2 Layer 20060606 Recommended LQ PC Board Layout: Bottom Layer 19 www.national.com LM4852 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead MOLDED PKG, Leadless Leadframe Package LLP Order Number LM4852LQ NS Package Number LQA24A www.national.com 20 LM4852 Integrated Audio Amplifier System Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 18-Bump micro SMD Order Number LM4852ITL NS Package Number TLA18AAA X1 = 1.996 X2 = 2.225 X3 = 0.600 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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