HI-8040 September 1999 GENERAL DESCRIPTION APPLICATIONS The HI-8040 is a CMOS integrated circuit designed for high voltage LCD display drive applications. It can drive 85 segments at voltages between +5 and -30 volts. An optional negative converter can generate the negative display drive voltage. Test inputs facilitate opens and shorts testing. The backplane frequency is checked and, as long as power is available, the segments are shut "Off" if the frequency becomes too low. The HI-8040 is part of a family of display drivers which control segment information in the same way. Data is serially clocked into the device and the data for all segment outputs are latched in parallel when the Load input transitions from high to low. With the Data Out from the shift register available, devices may be cascaded to obtain more segment outputs. The shift register is 85 bits long. The die is metal mask programmable to provide for various package and/or cascade tap options. Consult your Holt Sales representative to explore the possibilities. ! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays PIN CONFIGURATION (Top View) S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100 PIN QUAD CERPACK 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 See page 3-19 for magnified view FEATURES FUNCTIONAL BLOCK DIAGRAM ! 4 MHz serial input data rate DIN CL ! 85 segment outputs ! Cascadable Þ Þ DATA IN 85 Stage Shift Register CLK CS ! 5 Volt inputs translated to 35 Volts Þ LE ! Test pins allow hardware all "ON", all "OFF" or alternating ! Monitors backplane oscillation and forces all segments to "OFF" condition if below 10Hz LD BPOSC BPIN Þ Þ Þ Oscillator Divider Voltage Translator ! Negative voltage converter available on-chip ! CMOS low power ! Military processing available 85 Bit Latch Voltage Translators H i g h Voltage Drivers H i g h Voltage Buffer Þ BP (DS8040 Rev. NEW) DOUT 85 HOLT INTEGRATED CIRCUITS 3-15 85 SEGMENTS 9/99 HI-8040 FUNCTIONAL DESCRIPTION INPUT LOGIC DOUT CS must be held low to enter data into the shift register. The data is clocked on the negative edge of CL. LD is normally held low and only pulsed high when new data is ready for display. When LD is high the latch is transparent. All four logic inputs are TTL compatible. A logic "1" at DIN that is eventually latched to the segment drivers will cause the segment to be at the opposite voltage level of the BP pin (out of phase). The DOUT pin is available from segment 85 for cascading devices to drive more segments and for verifying the data integrity. This output can drive 2 TTL loads. It changes on the positive edge of CL. BPOSC and BPIN The user can either make an oscillator to create the backplane frequency or drive a signal into BPIN leaving BPOSC open. To make an oscillator, pins BPOSC and BPIN must be connected together and the appropriate R and C combination applied (See Figure 1). If the oscillator is used, the backplane frequency is approximately 1 fBP = . (for R = 180KW & C = 220pF, fBP » 100Hz). 256 RC AUTOMATIC SEGMENTS OFF The internal backplane signal is tested continuously to be at least 10Hz. If the detector senses f<10Hz, then the segments are forced to the same voltage as the backplane (all segments in "OFF" state). However, the detector is only functional while VDD is above the minimum operating voltage specification. TEST INPUTS The test functions available are: T2 T1 Display 0 0 Normal 0 1 All Off 1 0 All On 1 1 Alternating On/Off Segments VEE & NEGATIVE VOLTAGE CONVERTER VEE may be externally driven to a maximum -30V. Alternatively, there is a voltage converter that will provide -21.4 volts (See Figure 2). If the converter pins are left open circuit, an on-chip sense resistor will cause shut down of all current consumption associated with the converter. The converter will survive a shorted segment condition and continue to maintain VEE at -20 volts. The test inputs must be tied to the appropriate logic level for correct circuit operation. VDD R 330KW OSC RSENSE Control IN5818, IN5819 VDD 330µh VSS 10µF VSS HOLT INTEGRATED CIRCUITS 3-16 HI-8040 LD CL CS DIN BP CS CL LD CS CL LD CS CL LD DIN DO DIN DO DIN DO BPIN BP BPIN BP BPIN BP 1MΩ 1MΩ 1µF 1µF 1500pF R C BPOSC BPOSC V os BPOSC 1MΩ 1MΩ SEGMENTS SEGMENTS BACK PLANE SEGMENTS SEG n 1µF 360pF VALID HOLT INTEGRATED CIRCUITS 3-17 1 µF Voltages referenced to VSS = 0V Supply Voltage VDD........................ 0V to 7V VEE................VDD-35V to 0V Voltage at any input, except BPIN....-0.3 to VDD+0.3V Voltage at BPIN input.................VDD-35 to VDD+0.3V DC Current any input pin...................................10 mA Power Dissipation......................................................300 mW Operating Temperature Range - Industrial...... -40° to +85°C Operating Temperature Range - Hi-Temp/Mil...-55° to +125°C Storage Temperature Range............................-65° to +150°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD = 5V ±5%, VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified). PARAMETER Operating Voltage Supply Current: SYMBOL (Converter Off, fBP = 100Hz) Input Low Voltage (excluding BPIN) Input High Voltage (excluding BPIN) Input Low Voltage (BPIN) Input High Voltage (BPIN) Input Current Input Capacitance (Guaranteed, not tested) Segment Output Impedance Backplane Output Impedance Data Out Current: Source Current Sink Current Voltage Converter: @ No Load (VDD - VSS = 5V, TA = 25°C) @ 0.1mA Load @ 10KW Load Offset Voltage (Guaranteed, not tested) VDD IDD IEE VIL VIH VILX VIHX IIN CI RSEG RBP IDOH IDOL VEEC IDD VEEC VOS CONDITION MIN TYP 3.0 Static, No Load Static, No Load 0 2 VEE 0.8 VDD VIN = 0 to 5V IL = 10µA IL = 10µA VOH = 4.5 VOL = 0.4 See Fig. 2 See Fig. 2 See Fig. 2 See Fig. 4 3.2 -22 -21.5 MAX UNITS 7.0 300 120 0.8 VDD 0.6 VDD VDD 100 5 15,000 600 -3.0 25 V µA µA V V V V nA pF W W mA mA V mA V mV MAX UNITS 170 ns ns ns ns ns ns ns ns ns ns ns ns ns -21 1.8 -20 VDD = 5V , VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified). PARAMETER Clock Period Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock non-cascaded cascaded non-cascaded cascaded SYMBOL VDD MIN tCL tCL tCW tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 250 500 125 250 80 80 100 120 120 0 130 120 HOLT INTEGRATED CIRCUITS 3-18 TYP HI-8040 ORDERING INFORMATION PART NUMBER PACKAGE DESCRIPTION TEMPERATURE RANGE FLOW BURN IN LEAD FINISH HI-8040Q 100-PIN CERAMIC QUAD FLAT PACK (CQFP) -40°C to +85°C I NO SOLDER HI-8040QT 100-PIN CERAMIC QUAD FLAT PACK (CQFP) -55°C to +125°C T NO SOLDER HI-8040QM-01 100-PIN CERAMIC QUAD FLAT PACK (CQFP) -55°C to +125°C M YES SOLDER MAGNIFIED VIEW OF PIN ASSIGNMENTS S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100 PIN QUAD CERPACK Pin 1 HOLT INTEGRATED CIRCUITS 3-19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 HI-8040 PACKAGE DIMENSIONS inches (millimeters) 100-PIN CERAMIC QUAD FLAT PACK Package Type: 100 CQR .014 ± .002 TYP (.356 ± .051 TYP) .0256 ± .002 TYP (.6502 ± .051 TYP) .654 ± .012 (16.612 ± .305) .551 ± .006 (13.995 ± .152) .718 ± .014 (18.237 ± .356) Pin 1 .890 ± .012 (22.606 ± .305) .008 TYP (.203 TYP) .787 ± .007 (19.99 ± .178) Detail A .170 MAX (4.318 MAX) .032 ± .008 (.813 ± .203) .954 ± .014 (24.23 ± .356) HOLT INTEGRATED CIRCUITS 1 .0065 ± .0015 (.165 ± .038) 0° ΤΟ 7° Detail A