54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The ’F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fallthrough stack has self-contained control logic. Y Commercial Package Number Military 74F413PC 54F413DM (Note 1) Y Y Y Y Y Separate input and output clocks Parallel input and output Expandable without external logic 15 MHz data rate Supply current 160 mA max Available in SOIC, (300 mil only) Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line Note 1: Military grade device with environmental and burn-in processing. Use suffix e DMQB. Logic Symbol Connection Diagram Pin Assignment for DIP TL/F/9541 – 1 TL/F/9541 – 2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9541 RRD-B30M105/Printed in U. S. A. 54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O January 1995 Unit Loading/Fan Out 54F/74F Pin Names D0 – D3 O 0 – O3 IR SI SO OR MR Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Data Inputs Data Outputs Input Ready Shift In Shift Out Output Ready Master Reset 1.0/0.667 50/13.3 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 20 mA/b0.4 mA b 1 mA/8 mA 20 mA/b0.4 mA 20 mA/b0.4 mA 20 mA/b0.4 mA 20 mA/b0.4 mA 20 mA/b0.4 mA Functional Description Data OutputÐData is read from the O0 –O3 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and O0 –O3 remains as before, i.e., data does not change if FIFO is empty. Input Ready and Output Ready may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least tPT) or completely empty (Output Ready stays LOW for at least tPT). Data InputÐData is entered into the FIFO on D0 – D3 inputs. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IR will remain LOW. Data TransferÐOnce data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will ‘‘bubble’’ to the front. The tPT parameter defines the time required for the first data to travel from input to the output of a previously empty device. Block Diagram TL/F/9541 – 4 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.5 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IOL e 8 mA IOL e 8 mA IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current 54F Breakdown Test 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current 2.4 2.4 2.7 4.75 b 20 115 3 b 0.4 mA Max VIN e 0.5V b 130 mA Max VOUT e 0V 160 mA Max VO e HIGH AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Typ Max Min Max Min Units Max fmax Shift In Rate 10 8.0 10 fmax Shift Out Rate 10 8.0 10 MHz tPLH tPHL Propagation Delay Shift In to IR 1.5 1.5 44.0 31.0 1.5 1.5 50.0 37.0 1.5 1.5 48.0 35.0 ns tPLH tPHL Propagation Delay Shift Out to OR 1.5 1.5 52.0 31.0 1.5 1.5 57.0 37.0 1.5 1.5 55.0 35.0 ns tPLH tPHL Propagation Delay Output Data Delay 1.5 1.5 46.0 34.0 1.5 1.5 52.0 39.0 1.5 1.5 50.0 37.0 ns tPLH Propagation Delay Master Reset to IR 1.5 27.0 1.5 33.0 1.5 31.0 ns tPLH Propagation Delay Master Reset to OR 1.5 30.0 1.5 34.0 1.5 32.0 ns MHz AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Max Max Min Units Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to SI 1.0 1.0 1.0 1.0 1.0 1.0 th(H) th(L) Hold Time, HIGH or LOW Dn to SI 10.0 10.0 10.0 10.0 10.0 10.0 tw(H) tw(L) Shift In Pulse Width HIGH or LOW 5.0 10.0 5.0 10.0 5.0 10.0 tw(H) tw(L) Shift Out Pulse Width HIGH or LOW 7.5 10.0 8.5 10.0 7.5 10.0 tw(H) Input Ready Pulse Width, HIGH 7.5 8.5 7.5 ns tw(L) Output Ready Pulse Width, LOW 5.0 5.0 5.0 ns tw(L) Master Reset Pulse Width, LOW 10.0 10.0 10.0 ns trec Recovery Time, MR to SI 32.0 tPT Data Throughput Time 35.0 0.9 ns 35.0 1.0 4 ns ns 1.0 ms Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 413 P Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing Device Type Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Package Code P e Plastic DIP D e Ceramic DIP Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 5 54F/74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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