Revised August 1999 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description Features The F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fall-through stack has self-contained control logic. ■ Separate input and output clocks ■ Parallel input and output ■ Expandable without external logic ■ 15 MHz data rate ■ Supply current 160 mA max ■ Available in SOIC, (300 mil only) Ordering Code: Order Number Package Number 74F413PC N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/0.667 20 µA/−0.4 mA D0–D3 Data Inputs O0–O3 Data Outputs 50/13.3 −1 mA/8 mA IR Input Ready 1.0/0.667 20 µA/−0.4 mA SI Shift In 1.0/0.667 20 µA/−0.4 mA SO Shift Out 1.0/0.667 20 µA/−0.4 mA OR Output Ready 1.0/0.667 20 µA/−0.4 mA MR Master Reset 1.0/0.667 20 µA/−0.4 mA © 1999 Fairchild Semiconductor Corporation DS009541 www.fairchildsemi.com 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O April 1988 74F413 Functional Description defines the time required for the first data to travel from input to the output of a previously empty device. Data Input— Data is entered into the FIFO on D0–D3 inputs. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IR will remain LOW. Data Output— Data is read from the O0–O3 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and O0–O3 remains as before, i.e., data does not change if FIFO is empty. Data Transfer— Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will “bubble” to the front. The tPT parameter Input Ready and Output Ready— may also be used as status signals indicating that the FIFO is completely full (Input Ready stays LOW for at least tPT) or completely empty (Output Ready stays LOW for at least tPT). Block Diagram www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.5 V VOH Output HIGH 10% VCC 2.4 Voltage 5% VCC 2.7 VOL Output LOW Voltage 10% VCC IIH Input HIGH Current IBVI 2.0 Units VIH Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Output Leakage Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current 115 3 Recognized as a LOW Signal Min IIN = −18 mA IOH = −1 mA Min 0.5 V Min IOL = 8 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 3.75 −20 Conditions Recognized as a HIGH Signal V 4.75 Circuit Current IIL VCC V IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −0.4 mA Max VIN = 0.5V −130 mA Max VOUT = 0V 160 mA Max VO = HIGH www.fairchildsemi.com 74F413 Absolute Maximum Ratings(Note 1) 74F413 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = −55°C to +125°C TA = 0° to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Typ Max Min Max Min Units Max fMAX Shift In Rate 10 8.0 10 MHz fMAX Shift Out Rate 10 8.0 10 MHz tPLH Propagation Delay 1.5 44.0 1.5 50.0 1.5 48.0 tPHL Shift In to IR 1.5 31.0 1.5 37.0 1.5 35.0 tPLH Propagation Delay 1.5 52.0 1.5 57.0 1.5 55.0 tPHL Shift Out to OR 1.5 31.0 1.5 37.0 1.5 35.0 ns ns tPLH Propagation Delay 1.5 46.0 1.5 52.0 1.5 50.0 tPHL Output Data Delay 1.5 34.0 1.5 39.0 1.5 37.0 tPLH Propagation Delay 1.5 27.0 1.5 33.0 1.5 31.0 ns 1.5 30.0 1.5 34.0 1.5 32.0 ns ns Master Reset to IR tPLH Propagation Delay Master Reset to OR AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0° to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 1.0 1.0 1.0 tS(L) Dn to SI 1.0 1.0 1.0 tH(H) Hold Time, HIGH or LOW 10.0 10.0 10.0 tH(L) Dn to SI 10.0 10.0 10.0 tW(H) Shift In Pulse Width 5.0 5.0 5.0 tW(L) HIGH or LOW 10.0 10.0 10.0 Units Max ns ns tW(H) Shift Out Pulse Width 7.5 8.5 7.5 tW(L) HIGH or LOW 10.0 10.0 10.0 tW(H) Input Ready Pulse Width, 7.5 8.5 7.5 ns 5.0 5.0 5.0 ns 10.0 10.0 10.0 ns HIGH tW(L) Output Ready Pulse Width, LOW tW(L) Master Reset Pulse Width, LOW tREC Recovery Time, MR to SI tPT Data Throughput Time www.fairchildsemi.com 32.0 35.0 0.9 4 35.0 1.0 ns 1.0 µs 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com