Revised March 2000 DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register General Description These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design. The load mode is established by the shift/load input. When HIGH, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When LOW, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the LOW-to-HIGH level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking; holding either LOW enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. Ordering Code: Order Number Package Number Package Description DM74LS166M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS166WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS166N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006400 www.fairchildsemi.com DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register August 1986 DM74LS166 Function Table Inputs Internal Output QH Clock Load Inhibit L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L ↑ X a…h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 Clock Serial Parallel Outputs Shift/ Clear A…H QA QB H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a…h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, Q B, QH, respectively, before the indicated steady-state input conditions were established QAn, QGn, = The level of QA, QG, respectively, before the most recent ↑ transition of the clock Logic Diagram Timing Diagram Typical Clear, Shift, Load, Inhibit and Shift Sequences www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency (Note 2) Clock Frequency (Note 3) tW tSU V 2 Pulse Width (Note 4) Setup Time (Note 4) V 8 mA 0 25 MHz 0 20 MHz Clock 20 Clear 20 Mode 30 Data 20 tH Hold Time (Note 4) 0 TA Free Air Operating Temperature 0 ns ns ns °C 70 Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min Typ (Note 5) Max −1.5 2.7 IOL = 4 mA, VCC = Min 3.4 Units V V 0.35 0.5 0.25 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA IOS Short Circuit Output Current VCC = Max (Note 6) −100 mA ICC Supply Current VCC = Max (Note 7) 38 mA −20 22 mA Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs OPEN, 4.5V applied to the serial input, all other inputs except the CLOCK grounded, ICC is measured after a momentary ground, then 4.5V is applied to the CLOCK. 3 www.fairchildsemi.com DM74LS166 Absolute Maximum Ratings(Note 1) DM74LS166 Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time 25 LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Max Propagation Delay Time HIGH-to-LOW Level Output CL = 50 pF Min 20 MHz Clock to Output 8 35 38 ns Clock to Output 8 35 41 ns Clear to Output 6 30 36 ns Parameter Measurement Information Voltage Waveforms Test Table for Synchronous Inputs Data Input Shift/Load for Test Output Tested (See Note C) H 0V QH at TN+1 Serial Input 4.5V QH at TN+8 Note A: The clock pulse has the following characteristics: tW(clock) ≥ 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tW(clear) ≥ 20 ns and tHOLD = 0 ns. When testing fMAX, vary the clock PRR. Note B: A clear pulse is applied prior to each test. Note C: Propagation delay times (tPLHand tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test. Note D: tn = bit time before clocking transition tn+1 = bit time after one clocking transition tn+8 = bit time after eight clocking transitions Note E: VREF = 1.3V. www.fairchildsemi.com Units Max 4 DM74LS166 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B 5 www.fairchildsemi.com DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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