DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description Features The DS90CR287 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 85 MHZ, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHZ clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec). This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. n n n n n n n n n n n n n 20 to 85 MHZ shift clock support 50% duty cycle on receiver output clock Best–in–Class Set & Hold Times on TxINPUTs Low power consumption ± 1V common mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package Block Diagrams DS90CR287 DS90CR288A DS101087-27 DS101087-1 Order Number DS90CR287MTD See NS Package Number MTD56 Order Number DS90CR288AMTD See NS Package Number MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101087 www.national.com DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ October 1999 DS90CR287/DS90CR288A Pin Diagrams DS90CR287 DS90CR288A DS101087-21 DS101087-22 Typical Application DS101087-23 www.national.com 2 DS90CR288A Package Derating: DS90CR287 Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage 1.61 W 12.5 mW/˚C above +25˚C 12.4 mW/˚C above +25˚C DS90CR288A −0.3V to +4V −0.5V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) ESD Rating (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) Latch Up Tolerance @ +25˚C > 7kV > 700V > ± 300mA Recommended Operating Conditions LVDS Output Short Circuit Duration Continuous Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) +260˚C Maximum Package Power Dissipation @ +25˚C MTD56 (TSSOP) Package: DS90CR287 1.63 W Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 3.0 Nom 3.3 Max 3.6 Units V −10 0 +25 +70 2.4 100 ˚C V mVPP Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 VOH High Level Output Voltage IOH = −0.4 mA VOL Low Level Output Voltage IOL = 2 mA VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0.4V, 2.5V or VCC IOS Output Short Circuit Current VIN = GND 2.7 −10 VOUT = 0V 3.3 V V V 0.06 0.3 −0.79 −1.5 V +1.8 +15 µA −60 −120 mA 290 450 mV 35 mV 0 V µA LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage ∆VOD Change in VOD between Complimentary Output States VOS Offset Voltage (Note 4) ∆VOS Change in VOS between Complimentary Output States IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω IOZ Output TRI-STATE ® Current PWR DWN = 0V, RL = 100Ω 250 1.125 1.25 1.375 V 35 mV −3.5 −5 mA ±1 ± 10 µA VOUT = 0V or VCC LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V +100 −100 VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V 3 mV mV ± 10 ± 10 µA µA www.national.com DS90CR287/DS90CR288A Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. DS90CR287/DS90CR288A Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units f = 33 MHz 31 45 mA f = 40 MHz 32 50 mA f = 66 MHz 37 55 mA f = 85 MHz 42 60 mA 10 55 µA f = 33 MHz 49 70 mA f = 40 MHz 53 75 mA f = 66 MHz 81 114 mA f = 85 MHz 96 135 mA PWR DWN = Low Receiver Outputs Stay Low during Powerdown Mode 140 400 µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTZ Transmitter Supply Current Worst Case (with Loads) RL = 100Ω, CL = 5 pF, Worst Case Pattern (Figures 1, 2) Transmitter Supply Current Power Down PWR DWN = Low Driver Outputs in TRI-STATE under Powerdown Mode RECEIVER SUPPLY CURRENT ICCRW ICCRZ Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern (Figures 1, 3) Receiver Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD). Note 4: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 2) Parameter Min 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 2) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 4) TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 15) TPPos1 TPPos2 1.0 f = 85 MHz 6.0 ns −0.20 0 0.20 ns Transmitter Output Pulse Position for Bit1 1.48 1 . 68 1.88 ns Transmitter Output Pulse Position for Bit2 3.16 3 . 36 3.56 ns TPPos3 Transmitter Output Pulse Position for Bit3 4.51 5 . 04 5.24 ns TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6 . 72 6.92 ns TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8 . 40 8.60 ns TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10 . 08 10.28 ns ns TCIP TxCLK IN Period (Figure 6 ) 11.76 T 50 TCIH TxCLK IN High Time (Figure 6) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 6) THTC TxIN Hold to TxCLK IN (Figure 6) f = 85 MHz 2.5 ns 0 ns TCCD TxCLK IN to TxCLK OUT Delay @ 25˚C,VCC=3.3V (Figure 8) 6.3 ns TPLLS Transmitter Phase Lock Loop Set (Figure 10) 10 ms TPDD Transmitter Powerdown Delay (Figure 13) 100 ns TJIT TxCLK IN Cycle-toCycle Jitter (Figure TBD) 2 ns www.national.com 4 3.8 Typ Max Units CLHT Symbol CMOS/TTL Low-to-High Transition Time (Figure 3) Parameter Min 2 3.5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) 1.8 3.5 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 16) 0.49 0.84 1.19 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns RSKM RxIN Skew Margin (Note 5) (Figure 17) RCOP RxCLK OUT Period (Figure 7) 11.76 T 50 ns RCOH RxCLK OUT High Time (Figure 7) 4 5 6.5 ns 5 6 f = 85 MHz f = 85 MHz f = 85 MHz 290 RCOL RxCLK OUT Low Time (Figure 7) 3.5 RSRC RxOUT Setup to RxCLK OUT (Figure 7) 3.5 RHRC RxOUT Hold to RxCLK OUT (Figure 7) 3.5 RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 3.3V (Note 6)(Figure 9) 5.5 RPLLS RPDD ps ns ns ns 7 9.5 ns Receiver Phase Lock Loop Set (Figure 11) 10 ms Receiver Powerdown Delay (Figure 14) 1 µs Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and source clock (less than 150 ps). Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. AC Timing Diagrams DS101087-2 FIGURE 1. “Worst Case” Test Pattern DS101087-3 DS101087-4 FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times 5 www.national.com DS90CR287/DS90CR288A Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-5 DS101087-6 FIGURE 3. DS90CR288A (Receiver) CMOS/TTL Output Load and Transition Times DS101087-7 FIGURE 4. DS90CR287 (Transmitter) Input Clock Transition Time DS101087-8 Note 7: Measurements at VDIFF = 0V Note 8: TCCS measured between earliest and latest LVDS edges. Note 9: TxCLK Differential Low→High Edge FIGURE 5. DS90CR287 (Transmitter) Channel-to-Channel Skew DS101087-9 FIGURE 6. DS90CR287 (Transmitter) Setup/Hold and High/Low Times www.national.com 6 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-10 FIGURE 7. DS90CR288A (Receiver) Setup/Hold and High/Low Times DS101087-11 FIGURE 8. DS90CR287 (Transmitter) Clock In to Clock Out Delay DS101087-12 FIGURE 9. DS90CR288A (Receiver) Clock In to Clock Out Delay DS101087-13 FIGURE 10. DS90CR287 (Transmitter) Phase Lock Loop Set Time 7 www.national.com DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-14 FIGURE 11. DS90CR288A (Receiver) Phase Lock Loop Set Time DS101087-16 FIGURE 12. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs DS101087-17 FIGURE 13. Transmitter Powerdown DeIay www.national.com 8 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-18 FIGURE 14. Receiver Powerdown Delay DS101087-19 FIGURE 15. Transmitter LVDS Output Pulse Position Measurement 9 www.national.com DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-28 FIGURE 16. Receiver LVDS Input Strobe Position www.national.com 10 DS90CR287/DS90CR288A AC Timing Diagrams (Continued) DS101087-20 C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 10) + ISI (Inter-symbol interference)(Note 11) Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 150ps at 85MHZ. Note 11: ISI is dependent on interconnect length; may be zero FIGURE 17. Receiver LVDS Input Skew Margin 2. Applications Information The DS90CR287 and DS90CR288A are backward compatible with the existing 5V Channel Link transmitter/receiver pair (DS90CR283, DS90CR284). To upgrade from a 5V to a 3.3V system the following must be addressed: 1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL VCC. 3. Transmitter input and control inputs except 3.3V TTL/ CMOS levels. They are not 5V tolerant. The receiver powerdown feature when enabled will lock receiver output to a logic low. However, the 5V/66 MHz receiver maintain the outputs in the previous state when powerdown occurred. DS90CR287 Pin Description — Channel Link Transmitter I/O No. TxIN Pin Name I 28 TTL level input. Description TxOUT+ O 4 Positive LVDS differential data output. TxOUT− O 4 Negative LVDS differential data output. TxCLK IN I 1 TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. PWR DWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. VCC I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. DS90CR288A Pin Description — Channel Link Receiver Pin Name RxIN+ I/O No. I 4 Description Positive LVDS differential data inputs. RxIN− I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. 11 www.national.com DS90CR287/DS90CR288A Applications Information (Continued) DS90CR288A Pin Description — Channel Link Receiver Pin Name (Continued) I/O No. PWR DWN I 1 TTL level input.When asserted (low input) the receiver outputs are low. Description VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. RECEIVER FAILSAFE FEATURE: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, data outputs will all be HIGH; if the clock input is also floating/terminated, data outputs will remain in the last valid state. A floating/terminated clock input will result in a HIGH clock output. BOARD LAYOUT: To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input). Finally, the location of the CHANNEL LINK TxOUT/ RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI. The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths ( < 2m), the media electrical performance is less critical. For higher speed/long distance applications the media’s performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as TBD meters and with the maximum data transfer of TBD Gbit/s. Additional applications information can be found in the following National Interface Application Notes: AN = #### Topic AN-1041 Introduction to Channel Link AN-1108 Channel Link PCB and Interconnect Design-In Guidelines AN-806 Transmission Line Theory AN-905 Transmission Line Calculations and Differential Impedance AN-916 Cable Information CABLES: A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21bit CHANNEL LINK chipset (DS90CR217/218A) requires four pairs of signal wires and the 28-bit CHANNEL LINK chipset (DS90CR287/288A) requires five pairs of signal wires. The ideal cable/connector interface would have a constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below 140ps ( 85 MHZ clock rate) to maintain a sufficient data sampling window at the receiver. In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground provides a common mode return path for the two devices. Some of the more commonly used cable types for point-to-point applications include flat ribbon, flex, twisted pair and TwinCoax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while TwinCoax is good for short and long applications. When using ribbon cable, it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the www.national.com UNUSED INPUTS: All unused inputs at the TxIN inputs of the transmitter may be tied to ground or left no connect. All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION: Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL 12 DECOUPLING CAPACITORS: Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example is shown in Figure 19. The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins. (Continued) LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 18 shows an example. No additional pull-up or pulldown resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines. DS101087-24 FIGURE 18. LVDS Serialized Link Termination creating a low jitter LVDS clock. These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget. COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN: The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differential noise margin. Common mode protection is of more importance to the system’s operation due to the differential data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows for a ± 1.0V shifting of the center point due to ground potential differences and common mode noise. POWER SEQUENCING AND POWERDOWN MODE: Outputs of the CNANNEL LINK transmitter remain in TRISTATE ® until the power supply reaches 2V. Clock and data outputs will begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 µW (typical). DS101087-25 FIGURE 19. CHANNEL LINK Decoupling Configuration CLOCK JITTER: The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 85 MHZ clock has a period of 11.76 ns which results in a data bit width of 1.68 ns. Differential skew (∆t within one differential pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise passed on to the PLL, thus The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the receiver inputs are shorted to V CC through an internal diode. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the potential for latchup when powering the device. 13 www.national.com DS90CR287/DS90CR288A Applications Information DS90CR287/DS90CR288A Applications Information (Continued) DS101087-26 FIGURE 20. Single-Ended and Differential Waveforms www.national.com 14 inches (millimeters) unless otherwise noted Order Number DS90CR287MTD or DS90CR288AMTD Dimensions in millimeters only NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ Physical Dimensions