LP3883 3A Fast-Response Ultra Low Dropout Linear Regulators General Description Features The LP3883 is a high-current, fast-response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220 and TO-263 packages. Dropout Voltage: 210 mV (typ) @ 3A load current. Ground Pin Current: 3 mA (typ) at full load. Shutdown Current: 60 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. n n n n n n n n Ultra low dropout voltage (210 mV @ 3A typ) Low ground pin current Load regulation of 0.04%/A 60 nA typical quiescent current in shutdown 1.5% output accuracy (25˚C) TO-220, TO-263 packages Over temperature/over current protection −40˚C to +125˚C junction temperature range Applications n n n n n n n DSP Power Supplies Server Core and I/O Supplies Linear Power Supplies for PC Add-in-Cards Set-Top Box Power Supplies Microprocessor Power Supplies High Efficiency Linear Power Supplies SMPS Post-Regulators Typical Application Circuit 20062401 At least 4.7 µF of input and output capacitance is required for stability. Connection Diagrams 20062402 TO-220, Top View © 2003 National Semiconductor Corporation 20062403 TO-263, Top View DS200624 www.national.com LP3883 3A Fast-Response Ultra Low Dropout Linear Regulators August 2003 LP3883 Ordering Information Order Number Package Type Package Drawing Supplied As LP3883ES-1.2 TO263-5 TS5B Rail LP3883ESX-1.2 TO263-5 TS5B Tape and Reel LP3883ET-1.2 TO220-5 T05D Rail LP3883ES-1.5 TO263-5 TS5B Rail LP3883ESX-1.5 TO263-5 TS5B Tape and Reel LP3883ET-1.5 TO220-5 T05D Rail LP3883ES-1.8 TO263-5 TS5B Rail LP3883ESX-1.8 TO263-5 TS5B Tape and Reel LP3883ET-1.8 TO220-5 T05D Rail Block Diagram 20062424 www.national.com 2 IOUT (Survival) (Note 1) Output Voltage (Survival) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range −40˚C to +150˚C Operating Ratings 260˚C VIN Supply Voltage ESD Rating Human Body Model (Note 3) Machine Model (Note 10) (VOUT + VDO) to 5.5V Shutdown Input Voltage 2 kV 200V 0 to +6V IOUT 3A VIN Supply Voltage (Survival) −0.3V to +6V Operating Junction Temperature Range VBIAS Supply Voltage (Survival) −0.3V to +7V VBIAS Supply Voltage Shutdown Input Voltage (Survival) −0.3V to +7V Power Dissipation (Note 2) −0.3V to +6V Junction Temperature −65˚C to +150˚C Lead Temp. (Soldering, 5 seconds) Internally Limited Internally Limited −40˚C to +125˚C 4.5V to 6V Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS. Symbol VO Parameter Output Voltage Tolerance Conditions 10 mA < IL < 3A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 6V Typical (Note 4) MIN (Note 5) MAX (Note 5) 1.198 1.234 1.186 1.246 1.478 1.522 1.455 1.545 1.773 1.827 1.746 1.854 Units 1.216 1.5 V 1.8 ∆VO/∆VIN Output Voltage Line Regulation (Note 7) VO(NOM) + 1V ≤ VIN ≤ 5.5V ∆VO/∆IL Output Voltage Load Regulation (Note 8) 10 mA < IL < 3A VDO Dropout Voltage (Note 9) IL = 3A IQ(VIN) Quiescent Current Drawn from VIN Supply 10 mA < IL < 3A V IQ(VBIAS) Quiescent Current Drawn from VBIAS Supply Short-Circuit Current ≤ 0.3V 10 mA < IL < 3A V ISC S/D S/D ≤ 0.3V VOUT = 0V 0.01 %/V 0.04 0.06 %/A 210 270 420 mV 3 7 8 mA 0.03 1 30 µA 1 2 3 mA 0.03 1 30 µA 6 A Shutdown Input VSDT Output Turn-off Threshold Output = ON 0.7 Output = OFF 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current V S/D =1.3V 1 ≤ 0.3V −1 V S/D 3 1.3 0.3 V µs µA www.national.com LP3883 Absolute Maximum Ratings LP3883 Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS. (Continued) Symbol Parameter Conditions Typical (Note 4) MIN (Note 5) MAX (Note 5) Units AC Parameters PSRR (VIN) Ripple Rejection for VIN Input Voltage PSRR (VBIAS) Ripple Rejection for VBIAS Voltage VIN = VOUT +1V, f = 120 Hz VIN = VOUT + 1V, f = 1 kHz VBIAS = VOUT + 3V, f = 120 Hz VBIAS = VOUT + 3V, f = 1 kHz en 80 65 dB 70 65 Output Noise Density f = 120 Hz Output Noise Voltage VOUT = 1.8V BW = 10 Hz − 100 kHz 150 1 BW = 300 Hz − 300 kHz 90 µV/root−Hz µV (rms) Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220 devices is 65˚C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4˚C/W can be assumed. θJ-A for TO-263 devices is approximately 40˚C/W if soldered down to a copper plane which is at least 1.5 square inches in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation. Note 5: Limits are guaranteed through testing, statistical correlation, or design. Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. Note 7: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Note 8: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Note 9: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Note 10: The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V. www.national.com 4 LP3883 Typical Performance Characteristics Unless otherwise specified: TA = 25˚C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. Dropout vs IL IGND vs VSD 20062405 20062404 VOUT vs Temperature DC Load Regulation 20062406 20062407 Line Regulation vs VIN Line Regulation vs VBIAS 20062408 20062409 5 www.national.com LP3883 Typical Performance Characteristics Unless otherwise specified: TA = 25˚C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. (Continued) IBIAS vs IL IBIAS vs VBIAS 20062411 20062410 IGND vs VSD Noise Measurement 20062412 20062414 VOUTStartup Waveform VOUTStartup Waveform 20062415 www.national.com 20062416 6 VOUTStartup Waveform Line Regulation vs VBIAS 20062418 20062417 Line Regulation vs VBIAS VIN PSRR 20062419 20062420 VIN PSRR VBIAS PSRR 20062423 20062422 7 www.national.com LP3883 Typical Performance Characteristics Unless otherwise specified: TA = 25˚C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. (Continued) LP3883 Typical Performance Characteristics Unless otherwise specified: TA = 25˚C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. (Continued) VBIAS PSRR 20062431 Minimum ESR vs Output Load Current Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part’s requirements and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR increases very rapidly at temperatures below 10C. Aluminum caps can only be used in applications where lower temperature operation is not required. A second problem with Al caps is that many have ESR’s which are only specified at low frequencies. The typical loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap, it must be one whose ESR is specified at a frequency of 100 kHz or more. Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output capacitors on LP388X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the amount of Tantalum capacitance connected from the output to ground. 20062421 Application Hints VBIAS RESTRICTIONS FOR PROPER START-UP To prevent misoperation, ensure that VBIAS is below 50mV before start-up is initiated. This scenario can occur in systems with a backup battery using reverse-biased "blocking" diodes which may allow enough leakage current to flow into the VBIAS node to raise it’s voltage slightly above ground when the main power is removed. Using low leakage diodes or a resistive pull down can prevent the voltage at VBIAS from rising above 50mV. Large bulk capacitors connected to VBIAS may also cause a start-up problem if they do not discharge fully before re-start is initiated (but only if VBIAS is allowed to fall below 1V). A resistor connected across the capacitor will allow it to discharge more quickly. It should be noted that the probability of a "false start" caused by incorrect logic states is extremely low. OUTPUT "BYPASS" CAPACITORS Many designers place small value "bypass" capacitors at various circuit points to reduce noise. Ceramic capacitors in the value range of about 1000pF to 0.1µF placed directly on the output of a PNP or P-FET LDO regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output capacitor is in parallel with it. This is not unique to National Semiconductor LDO regulators, it is true of any P-type LDO regulator. The reason for this is that PNP or P-FET regulators have a higher output impedance (compared to an NPN regulator), which results in a pole-zero pair being formed by every different capacitor connected to the output. The zero frequency is approximately: Fz = 1 / (2 X π X ESR X C) Where ESR is the equivalent series resistance of the capacitor, and C is the value of capacitance. The pole frequency is: Fp = 1 / (2 X π X RL X C) Where RL is the load resistance connected to the regulator output. To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of 1MHz, which is delivering 0.5A of current from a 2.5V output (which means RL is 5 Ohms). We then place a .047 µF capacitor on the output. This creates a pole whose frequency is: EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR At least 4.7µF of output capacitance is required for stability (the amount of capacitance can be increased without limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range as shown in the graph below over the full operating temperature range for stable operation. www.national.com 8 TRmax = TJmax− TAmax The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD These parts are available in TO-220 and TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 ˚C/W for TO-220 package and ≥ 60 ˚C/W for TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. (Continued) Fp = 1 / (2 X π X 5 X .047 X 10E-6) = 677 kHz This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to "decouple" them from the regulator output. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263 package. INPUT CAPACITOR The input capacitor must be at least 4.7 µF, but can be increased without limit. It’s purpose is to provide a low source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application where temperatures go below about 10˚C. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3˚C/W for a TO220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown, 2˚C/W can be assumed. BIAS CAPACITOR The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 6V to assure proper operation of the part. HEATSINKING TO-263 PACKAGE The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND 20062425 FIGURE 1. θJA vs Copper (1 Ounce) Area for TO-263 package where IGND is the operating ground current of the device. The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): 9 www.national.com LP3883 Application Hints LP3883 Application Hints (Continued) As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a PCB is 32˚C/W. Figure 2 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35˚C/W and the maximum junction temperature is 125˚C. 20062426 FIGURE 2. Maximum power dissipation vs ambient temperature for TO-263 package www.national.com 10 LP3883 Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package (TO220-5) NS Package Number T05D 11 www.national.com LP3883 3A Fast-Response Ultra Low Dropout Linear Regulators Physical Dimensions inches (millimeters) unless otherwise noted (Continued) TO263 5-Lead, Molded, Surface Mount Package (TO263-5) NS Package Number TS5B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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