3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
FEATURES
Works with 1.25V ~ 5.5V VIN
Ultra Low Dropout Voltage
Low Quiescent Current
Excellent Line and Load Regulation
Guaranteed Output Current of 3.0A
Adjustable Output Voltage Down to 0.8V
VOUT Power OK Signal
Logic Controlled Shutdown Option
Over-Temperature/Over-Current Protection
-40℃ to 125℃ Junction Temperature Range
SOP‐8‐PP APPLICATION
Motherboards and Graphic Cards
Microprocessor and Chipset Power Supplies
Peripheral Cards
Low Voltage Digital ICs
High Efficiency Linear Regulators
DESCRIPSION
The TJ47300 is a 3.0A high performance ultra lowdropout linear regulator ideal for powering core voltages
of low-power microprocessors. The TJ47300 implements
a dual supply configuration allowing for very low output
impedance. The TJ47300 requires a bias input supply
and a main input supply, allowing for ultra-low input
voltages on the main supply rail. The input supply
operates from 1.25V to 5.5V and the bias supply requires
between 3V and 5.5V for proper operation. The TJ47300
delivers high current and ultra-low-dropout output
voltage as low as 0.8V for applications where VOUT is very
close to VIN. The TJ47300 is developed on a CMOS
technology which allows low quiescent current operation
independent of output current. This technology also
allows the TJ47300 to operate under extremely low
dropout conditions.
ORDERING INFORMATION
Device
Package
TJ47300GDP
SOP8-PP
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC
SYMBOL
MIN.
MAX.
UNIT
Input Supply Voltage (Survival)
VIN
-0.3
6
V
Enable Input Voltage (Survival)
VEN
-0.3
6
V
Bias Supply Voltage (Survival)
VBIAS
-0.3
6
V
Output Voltage (Survival)
VOUT
-0.3
VIN +0.3
V
Lead Temperature (Soldering, 5 sec)
TSOL
260
℃
Storage Temperature Range
TSTG
-65
150
℃
Operating Junction Temperature Range
TJOPR
-40
125
℃
Package Thermal Resistance *
ΘJA-SOP8-PP
68
ºC/W
* Calculated from package in still air, mounted to 2.6mm X 3.5mm(minimum foot print) 2 layer PCB without thermal vias per JESD51 standards.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
ORDERING INFORMATION
Package
SOP8-PP
Order No.
TJ47300GDP
Description
Package Marking
Compliance
Supplied As
3.0A, Enable,
Adjustable, Power OK
TJ47300G
RoHS, Halogen Free
Reel
ORDERING INFORMATION (Continued)
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
PIN CONFIGURATION
SOP8-PP
PIN DESCRIPTION
Pin No.
Pin Name
Pin Function
1
POK
Power OK Indication. This pin is an Open-drain output and is set high impedance
once VOUT reaches 92% of its rating voltage.
2
EN
Enable Input. Pulling this pin below 0.4V turns the regulator off.
Do not float
3
IN
Power Input. This pin is the drain input to the power device that supply current
to output pin.
4
BIAS
Supply Input for Internal Circuit. Input Bias Voltage for powering all circuitry on
the regulator except the output power TR.
5
NC
6
OUT
7
FB
8
GND
-
Thermal Exposed
PAD
2011 Preliminary
No Connection.
Power Output. This pin is power output of the device.
Feedback Voltage. A resistor divider from the output to GND is used to set the
regulation voltage as VOUT= 0.8V x (1+R2/R1)
Ground
Connect to Ground.
3
HTC
3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
BLOCK DIAGRAM
TYPICAL APPLICATION
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VBIAS = 5V, VIN = VO(NOM) + 1V, VEN=VBIAS, IL = 10 mA, TA=25℃.
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Power Input Voltage
VIN
VOUT=VREF
1.25
-
5.5
V
Bias Input Voltage
VBIAS
VOUT=VREF
3.0
-
5.5
V
Reference Voltage
VREF
VBIAS=VIN=VEN=5.0V, IOUT=10mA,
VOUT=VREF
0.784
0.8
0.816
V
VIN Line Regulation(Note 1)
ΔVLINE(IN)
VOUT+1V<VIN<5.5V, IOUT=10mA
-
0.02
0.10
%/V
VBIAS Line Regulation(Note 2)
ΔVLINE(BIAS) VIN=3.3V, IOUT=10mA, VOUT=VREF
-
0.02
0.10
%/V
Load Regulation(Note 1, 3)
ΔVLOAD
-
0.20
0.75
%
IL = 1.0A, VBIAS=VEN=5.0V, VOUT=VREF
-
120
150
IL = 2.0A, VBIAS=VEN=5.0V, VOUT=VREF
-
240
300
IL = 3.0A, VBIAS=VEN=5.0V, VOUT=VREF
-
380
450
IL = 10mA
-
0.1
1.0
mA
IL = 3.0 A
-
0.1
1.0
mA
-
-
150
uA
Dropout Voltage
VDROP
Ground Pin Current(Note 4)
10mA < IL <3A,
VOUT=VREF
VCNTL=VIN=VEN=5.0V,
mV
IGND1
(Note5)
IGND2
VEN < 0.4 V, POK=open
Logic High
VIH
Output=High
2.0
-
-
V
Logic Low
VIL
Output=Low
-
-
0.4
V
EN Input Current
IEN
VEN=VCNTL=5.0V
-
-
0.5
uA
FB Power OK Threshold
VPOKTH
IOUT=0A, VCNTL=VIN=VEN=5.0V, VOUT=VREF
-
90
-
%
Power OK Hysteresis
VPOKHYS
IOUT=0A, VCNTL=VIN=VEN=5.0V, VOUT=VREF
-
10
-
%
OCP Threshold Level
IOCP
VCNTL=VIN=VEN=5.0V, VOUT=VREF
-
4.5
-
A
Thermal Shutdown Temperature
TSD
-
165
-
℃
Thermal Shutdown Hysteresis
ΔTSD
-
10
-
℃
Enable Threshold
Note 1. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the
input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value
due to change in load current.
Note 2. Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the
bias line voltage.
Note 3. Regulation is measured at constant junction temperature by using a 10ms current pulse. Devices are tested for load
regulation in the load range from 10mA to 3.0A
Note 4. IGND = IBIAS + (IIN – IOUT). The total current drawn from the supply is the sum of the load current plus the ground
current.
Note 5. When POK pin is applied to VBIAS through the resistor R3, IGND2 should be added to the bias current (VBIAS - VPOK ) / R3.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
TYPICAL OPERATING CHARACTERISTICS
- TEST Circuit
Circuit #1
Circuit #2
VBIAS
R2
10K
VIN
C1
0.1uF
Circuit #3
BIAS
IN
CIN
10uF
POK
EN
TJ47300
VOUT
OUT
Cff
GND
FB
R2
COUT
10uF
R1
Circuit #4
Circuit #5
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3.0A Low Output Voltage Ultra LDO Regulator
VEN
VEN
VOUT
VOUT
VEN: 5V/div, VOUT: 2V/div, 200us/div
VEN: 5V/div, VOUT: 2V/div, 200us/div
TJ47300
Start Up @ Iout=10mA, Circuit #1
Start Up @ Iout=3.0A, Circuit #1
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
VIN
VIN
VBIAS
VBIAS
VOUT
VOUT
VPOK
VIN: 5V/div, VBIAS: 5V/div, VOUT: 2V/div, 500us/div
VIN: 5V/div, VBIAS: 5V/div, VOUT: 2V/div, VPOK: 5V/div, 500us/div
Start Up with VBIAS @ Iout=10mA, Circuit #2
Start Up with VIN @ Iout=10mA, Circuit #2
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V)
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VBIAS=5.0V)
VEN
VEN
VOUT
VOUT
VEN: 5V/div, VOUT: 2V/div, 200us/div
VEN: 5V/div, VOUT: 2V/div, 200us/div
Start Up @ Iout=10mA, Circuit #3
Start Up @ Iout=3.0A, Circuit #3
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
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3.0A Low Output Voltage Ultra LDO Regulator
VIN
TJ47300
VIN
VBIAS
VBIAS
VOUT
VOUT
VIN: 5V/div, VBIAS: 5V/div, VOUT: 2V/div, 500us/div
VIN: 5V/div, VBIAS: 5V/div, VOUT: 2V/div, 500us/div
Start Up with VBIAS @ Iout=10mA, Circuit #4
Start Up with VIN @ Iout=10mA, Circuit #4
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V)
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VBIAS=5.0V)
VBIAS
VBIAS
VEN
VEN
10nF
VOUT
10nF
100nF
100nF
330nF
VOUT
VBIAS: 5V/div, VEN: 5V/div, OUT: 2V/div, 2ms/div
VBIAS: 5V/div, VEN: 5V/div, OUT: 2V/div, 2ms/div
Start Up @ Iout=10mA, Circuit #1
Start Up @ Iout=10mA, Circuit #5
(Cff is varied, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
(Cdelay is varied, R2=10kΩ, R1=4.7kΩ, VIN=3.5V)
VOUT
VOUT
IOUT
IOUT
VOUT: 20mV/div, IOUT: 2A/div, 100us/div
VOUT: 20mV/div, IOUT: 2A/div, 100us/div
Load Transient Response
Load Transient Response
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
(Cff=10nF, R2=10kΩ, R1=4.7kΩ, VIN=3.5V, VBIAS=5.0V)
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0.86
0.86
0.83
0.83
VREF [V]
VREF [V]
3.0A Low Output Voltage Ultra LDO Regulator
0.80
0.77
TJ47300
0.80
0.77
0.74
0.74
1
2
3
4
5
6
2.5
VIN [V]
3
3.5
4
4.5
5
5.5
6
VBIAS [V]
VREF vs. VIN @ VBIAS=5.5V
VREF vs. VBIAS @ VIN=5.5V
700
600
VOUT = 3.3V
VDROP [mV]
500
VOUT = 3.0V
400
VOUT = 2.5V
300
200
VOUT = 1.5V
100
0
0
0.5
1
1.5
2
2.5
3
Iout [A]
Dropout Voltage
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
APPLICATION INFORMATION
The TJ47300 is a high performance, low dropout linear regulator, designed for high current application that
requires fast transient response. The TJ47300 operates from two input supply voltages, significantly reducing
dropout voltage. The TJ47300 is designed so that a minimum of external component are necessary.
Bias Supply Voltage
The TJ47300 control circuitry is supplied by the BIAS pin which requires a very low bias current even at
the maximum output current level. A bypass capacitor on the bias pin is recommended to improve the
performance of the TJ47300 during line and load transient. A small ceramic capacitor from BIAS pin to
ground reduces high frequency noise that could be injected into the control circuitry from the bias rail.
In practical applications, a 1uF capacitor and smaller valued capacitors such as 0.01uF or 0.001uF in
parallel with that larger capacitor may be used to decouple the bias supply. The BIAS input voltage must
be 2.1V above the output voltage, with a minimum BIAS input voltage of 3.0V.
Adjustable Regulator Design
An adjustable output device has output voltage range of 0.8V to 3.3V. To obtain a desired output
voltage, the following equation can be used two external resistors as presented in the typical application
circuit. The resistor values are given by;
V
R 1 R 2 OUT 1
0.8
It is suggested to use R1 values lower than 10kΩ to obtain better load transient performances. Even,
higher values up to 100 kΩ are suitable.
Enable
The TJ47300 feature an active high Enable input (EN) that allows on/off control of the regulator. The
enable function of TJ47300 has hysteresis characteristics. Pulling VEN lower than 0.4V disables the chip.
Pulling VEN higher than 2.0V enables the output voltage.
Supply Power Sequencing
In common applications where the power on transient of VIN and VBIAS voltages are not particularly fast
(Tr > 100us), no power sequencing is required. Where voltage transient input is very fast(Tr<100us), it
is recommended to have the VIN voltage present before or, at least, at the same time as the VBIAS voltage
in order to avoid over voltage spikes during the power on transient.
Output Capacitors
The TJ47300 requires an of output capacitance to maintain stability. The output capacitor must meet
both requirements for minimum amount of capacitance and ESR in all LDOs application. The TJ47300 is
designed specifically to work with low ESR ceramic output capacitor in space-saving and performance
consideration. Using a ceramic capacitor which value is at least 10uF on the TJ47300 output ensures
stability. Output capacitor of larger capacitance can reduce noise and improve load transient response,
stability, and PSRR. A minimum ceramic capacitor over than 10uF should be very closely placed to the
output voltage pin of the TJ47300.
Input Capacitor
A large bulk capacitance over than 10uF should be closely placed to the input supply pin of the
TJ47300 to ensure that the input supply voltage does not sag. Also a minimum of 10uF ceramic capacitor
is recommended to be placed directly next to the IN pin. It allows for the device being some distance
from any bulk capacitor on the rail. Additionally, input droop due to load transients is reduced, improving
load transient response. Additional capacitance may be added if required by the application.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
Decoupling (Bypass) Capacitor
In very electrically noisy environments, it is recommended that additional ceramic capacitors be placed
from VIN to GND. The use of multiple lower value ceramic capacitors in parallel with output capacitor also
allows to achieve better transient performance and stability if required by the application. (See Fig.1)
Feed-Forward Capacitor
To get the higher PSRR than the inherent performance of TJ47300, it is recommended that additional
ceramic feed-forward capacitor be placed from OUT pin to FB pin. The capacitance of feed-forward
capacitor with range of 10pF to 1uF allows to achieve better PSRR performance when required by the
application. (See Fig.1)
Fig. 1 Application with Decoupling & Feed-Forward Capacitor
Maximum Output Current Capability
The TJ47300 can deliver a continuous current of 3.0A over the full operating junction temperature range.
However, the output current is limited by the restriction of power dissipation which differs from packages.
A heat sink may be required depending on the maximum power dissipation and maximum ambient
temperature of application. With respect to the applied package, the maximum output current of 3.0A
may be still undeliverable due to the restriction of the power dissipation of TJ47300. Under all possible
conditions, the junction temperature must be within the range specified under operating conditions.
The temperatures over the device are given by:
TC = TA + PD X θCA / TJ = TC + PD X θJC / TJ = TA + PD X θJA
where TJ is the junction temperature, TC is the case temperature, TA is the ambient temperature, PD is the
total power dissipation of the device, θCA is the thermal resistance of case-to-ambient, θJC is the thermal
resistance of junction-to-case, and θJA is the thermal resistance of junction to ambient.
The total power dissipation of the device is given by:
PD = PIN – POUT = {(VIN X IIN) + (VBIAS X IBIAS)} – (VOUT X IOUT)
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature
(TAmax) of the application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax – TAmax
The maximum allowable value for junction-to-ambient thermal resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD = (TJmax – TAmax) / PD
TJ47300 is available in SOP8-PP package. The thermal resistance depends on amount of copper area
or heat sink, and on air flow.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
If proper cooling solution such as heat sink, copper plane area, air flow is applied, the maximum
allowable power dissipation could be increased. However, if the ambient temperature is increased, the
allowable power dissipation would be decreased.
The θJA could be decreased with respect to the copper plane area. So, the specification of maximum
power dissipation for an application is fixed, the proper copper plane area could be estimated by
following graphs. Wider copper plane area leads lower θJA.
The maximum allowable power dissipation is also influenced by the ambient temperature. With the
above θJA-Copper plane area relationship, the maximum allowable power dissipation could be evaluated
with respect to the ambient temperature. As shown in graph, the higher copper plane area leads θJA.
And the higher ambient temperature leads lower maximum allowable power dissipation.
The graph above is valid for the thermal impedance specified in the Absolute Maximum Ratings section
on page 1.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
The θJA could be decreased with respect to the copper plane area. So, the specification of maximum
power dissipation for an application is fixed, the proper plane area could be estimated by following graphs.
Wider copper plane area leads lower θJA.
The maximum allowable power dissipation is also influenced by the ambient temperature. With the θJACopper plane area relationship, the maximum allowable power dissipation could be evaluated with
respect to the ambient temperature. As shown in graph, the higher copper plane area leads θJA. And
the higher ambient temperature leads lower maximum allowable power dissipation.
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3.0A Low Output Voltage Ultra LDO Regulator
TJ47300
PRELIMINARY REVISION NOTICE
The information in this datasheet can be revised without any notice.
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