ICHAUS IC

iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 1/23
FEATURES
APPLICATIONS
♦
♦
♦
♦
♦
♦ Digital angular sensor
technology, 0–360°
♦ Incremental angular encoder
♦ Absolute angular encoder
♦ Brushless motors
♦ Motor feedback
♦ Rotational speed control
♦
♦
♦
♦
♦
♦
♦
♦
♦
Real-time system for rotation speed up to 120,000 rpm
Integrated Hall sensors with automatic offset compensation
4x sensor arrangement for fault-tolerant adjustment
Amplitude control for optimum operating point
Interpolator with 4096 angular increments/resolution better
than 0.1°
Programmable resolution, hysteresis, edge spacing, zero
position and rotating direction
Incremental output of sensor position up to 8 MHz edge rate
RS422-compatible AB encoder signals with index Z
UVW commutation signals for EC motor applications
Serial interface for data output and configuration
SSI-compatible output mode
Integrated ZAP diodes for module setup and OEM data,
programmable via serial interface
Signal error (e.g. magnet loss) can also be read out via serial
interface
Extended temperature range from -40 to +125 °C
PACKAGES
QFN28 5 x 5 mm²
BLOCK DIAGRAM
+ 5V
+ 5V
VPA
VPD
A
B
B
B
B
PTE
B
TEST
HALL SENSOR
CONVERSION
LOGIC
Z
SINE-TO-DIG
RS422
2
SIN + COS
U
2
NERR
V
AMPLITUDE
CORRECTION
ERROR MONITOR
AMPL CONTROL
0x00
MA
PHASE
SHIFT
SINE-TO-COM
INCR INTERFACE
iC-MH
0x0F
0x10
SLO
W
16 Byte ZROM
0x1F
SLI
SERIAL
INTERFACE
Copyright © 2008 iC-Haus
0x77
0x7F
ZAP CONTROL
RAM
BIAS/VREF
VNA
VND
VZAP
ZAPROM
C301107-2
http://www.ichaus.com
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 2/23
DESCRIPTION
The iC-MH 12-bit angular encoder is a position sensor with integrated Hall sensors for scanning a permanent magnet. The signal conditioning unit generates constant-amplitude sine and cosine voltages
that can be used for angle calculation. The resolution can be programmed up to a maximum of 4,096
angular increments per rotation.
The integrated serial interface also enables the position data to be read out to several networked sensors.
And the integrated memory can be written embedded
in the data protocol.
The incremental interface with the pins A, B and Z
supplies quadrature signals with an edge rate of up
to 8 MHz. Interpolation can be carried out with maximum resolution at a speed of 120,000 rpm. The position of the index pulse Z is adjustable.
The commutation interface with the signals U, V and
W provides 120° phase-shifted signals for block commutation. The zero point of the commutation signals
is freely definable in increments of 1.875° over 360°.
The commutation signals are available for EC motors
with 1 and 2 pole pairs.
The RS422-compatible outputs of the incremental
interface and the commutation interface are programmable in the output current and the slew rate.
In conjunction with a rotating permanent magnet, the
iC-MH module forms a one-chip encoder. The entire
configuration can be stored in the internal parameter
ROM with zapping diodes. The integrated programming algorithm assumes writing of the ROM structure.
PACKAGES QFN28 5 x5 mm² to JEDEC MO-220-VHHD-1
PIN CONFIGURATION QFN28 5 x 5mm²
nc
nc
nc
nc
nc
nc
W
28
27
26
25
24
23
22
PIN FUNCTIONS
No. Name Function
PTE
1
21
V
NERR
2
20
U
VPA
3
19
VPD
VNA
4
18
VND
SLI
5
17
Z
MA
6
16
B
SLO
7
15
A
MH
8
9
10
11
nc
nc
nc
nc
13
14
nc
nc
12
VZAP
1
2
3
4
5
6
7
8-11
12
13,14
15
16
17
18
19
20
21
22
23-28
PTE
NERR
VPA
VNA
SLI
MA
SLO
nc
VZAP
nc
A
B
Z
VND
VPD
U
V
W
nc
TP
Test Enable Pin
Error output(active low)
+5 V Supply Voltage (analog)
Ground (analog)
Serial Interface, Data Input
Serial Interface, Clock Input
Serial Interface, Data Output
not connected
Zener Zapping Programming Voltage
not connected
Incremental A (+NU)
Incremental B (+NV)
Index Z (+NW)
Ground (digital)
+5 V Supply Voltage (digital)
Commutation U (+NA)
Commutation V (+NB)
Commutation W (+NZ)
not connected
Thermal-Pad
The Thermal Pad is to be connected to VNA on the PCB. Orientation of the logo (
alteration.
MH CODE ...) is subject to
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 3/23
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Supply voltages at VPA, VPD
-0.3
6
V
G002 V(VZAP)
Zapping voltage
-0.3
8
V
G003 V()
Voltages at A, B, Z, U, V, W, MA, SLO,
SLI, NERR, PTE
-0.3
6
V
G004 I()
Current in VPA
-10
20
mA
G005 I()
Current in VPD
-20
200
mA
G006 I()
Current in A, B, Z, U, V, W
-100
100
mA
G007 I()
Current in MA, SLO, SLI, NERR, PTE
-10
10
mA
G008 Vd()
ESD-voltage, all pins
2
kV
G009 Ts
Storage temperature
-40
150
°C
G010 Tj
Chip temperature
-40
135
°C
HBM 100 pF discharged over 1.5 kΩ
THERMAL DATA
Operating conditions: VPA, VPD = 5 V ±10 %
Item
No.
T01
T02
Symbol
Parameter
Conditions
Unit
Min.
Ta
Rthja
Ambient temperature
Thermal resistance chip/ambient
Typ.
-40
package mounted on PCB, thermal pad at
approx. 2 cm² cooling area
All voltages are referenced to ground unless otherwise stated.
All currents into the device pins are positive; all currents out of the device pins are negative.
Max.
125
40
°C
K/W
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 4/23
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
General
001
V(VPA,
VPD)
Supply Voltage Range
4.5
5.5
V
002
I(VPA)
Supply Current in VPA
003
I(VPD)
Supply Current in VPD
PRM = ’0’, without Load
3
8
mA
5
15
004
I(VPD)
Supply Current in VPD
PRM = ’1’, without Load
mA
2
10
005
Vc(hi)
Clamp Voltage hi at MA, SLI,
SLO, PTE, NERR
mA
Vc()hi = V() − VPD, I() = 1 mA
0.4
1.5
V
006
Vc(lo)
Clamp Voltage lo
I() = -1 mA
-1.5
-0.3
V
20
100
kA/m
2
120 000
kHz
rpm
Hall Sensors and Signal Conditioning
101
Hext
Operating Magnetic Field
Strength
At Chip Surface
102
fmag
Operating Magnetic Field Frequency
Rotating Speed of Magnet
103
dsens
Diameter of HALL Sensor Array
104
xdis
Lateral Displacement of Magnet
to Chip
105
xpac
Displacement Chip to Package
QFN28 package
-0.2
0.2
mm
106
φ pac
Angular alignment of chip vs.
package
QFN28 package
-3
+3
Deg
107
hpac
Distance of chip surface to pack- QFN28 package
age surface
108
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x7F
109
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x3F
110
Vopt
Optimal differential output voltage Vopt = Vpp(PSIN) − Vpp(NSIN), ENAC = ’0’,
see Fig. 6
2
mm
0.2
0.4
mm
mm
-55
55
mV
mV
4
Vpp
Amplitude Control
201
Vampl
Differential Output Amplitude
Vampl = Vpp(PSIN) − Vpp(NSIN), ENAC = ’1’,
see Fig. 6
3.2
202
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS)
1.09
203
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS)
0.91
204
tampl
Settling Time of Amplitude Control
±10%
300
µs
205
Vae()lo
Amplitude Error Threshold for
MINERR
Vpp(PSIN) − Vpp(NSIN)
1.2
2.8
Vpp
206
Vae()hi
Amplitude Error Threshold for
MAXERR
Vpp(PSIN) − Vpp(NSIN)
5.0
5.8
Vpp
4.8
Vpp
Bandgap Reference
401
Vbg
Bandgap Reference Voltage
1.2
1.25
1.3
V
402
403
Vref
Reference Voltage
45
50
55
%VPA
Iibm
Bias Current
-100
CIBM = 0x0
CIBM = 0xF
Bias Current adjusted
-370
-220
-200
-180
µA
µA
µA
404
VPDon
Turn-on Threshold VPD, System V(VPD) − V(VND), increasing voltage
on
3.7
4.0
4.3
V
405
VPDoff
Turn-off Threshold VPD, System V(VPD) − V(VND), decreasing voltage
reset
3
3.5
3.8
V
406
VPDhys
Hysteresis System on/reset
0.35
407
Vosr
Reference voltage offset compensation
480
V
500
520
mV
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 5/23
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Clock Generation
501
f()sys
System Clock
Bias Current adjusted
0.85
1.0
1.15
MHz
502
f()sdc
Sinus/Digital-Converter Clock
Bias Current adjusted
14
16
18
MHz
Sin/Digital Converter
601
RESsdc
Sinus/Digital-Converter Resolution
12
602
AAabs
Absolute Angular Accuracy
Vpp() = 4 V, adjusted
603
AArel
Relative Angular Accuracy
with reference to one output periode at A, B, at
Resolution 1024, see Fig. 17
604
f()ab
Output frequency at A, B
CFGMTB = ’0’
CFGMTB = ’1’
605
REScom
Resolution of Commutation Converter
606
AAabs
Absolute Angular Accuracy of
Commutation Converter
Bit
-0.35
0.35
Deg
-10
10
%
0.5
2.0
MHz
MHz
1.875
Deg
-0.5
0.5
Deg
0.4
V
Serial Interface, Digital Outputs MA, SLO, SLI
701
Vs(SLO)hi Saturation Voltage High
V(SLO) = V(VPD) − V(),
I(SLO) = 4 mA
702
Vs(SLO)lo Saturation Voltage Low
I(SLO) = 4 mA to VND
703
Isc(SLO)hi Short-Circuit Current High
V(SLO) = V(VND), 25°C
704
Isc(SLO)lo Short-Circuit Current Low
V(SLO) = V(VPD), 25°C
80
mA
705
tr(SLO)
Rise Time SLO
CL = 50 pF
60
ns
706
tf(SLO)
Fall Time SLO
CL = 50 pF
60
ns
707
Vt()hi
Threshold Voltage High: MA, SLI
2
V
708
Vt()lo
Threshold Voltage Low: MA, SLI
0.8
709
Vt()hys
Threshold Hysteresis: MA, SLI
150
710
Ipd(SLI)
Pull-up Current: MA, SLI
711
Ipu(MA)
712
f()MA
V() = 0...VPD − 1 V
0.4
-80
-50
50
V
mA
V
250
mV
6
30
60
-60
-30
-6
µA
µA
10
MHz
2
V
Zapping and Test
801
Vt()hi
Threshold Voltage High VZAP,
PTE
with reference to VND
802
Vt()lo
Threshold Voltage Low VZAP,
PTE
with reference to VND
0.8
803
Vt()hys
Hysteresis
Vt()hys = Vt()hi − Vt()lo
150
804
Vt()nozap
Threshold Voltage Nozap VZAP
V() = V(VZAP) − V(VPD), V(VPD) = 5 V ±5 %,
at chip temperature 27 °C
0.8
805
Vt()zap
Threshold Voltage Zap VZAP
V() = V(VZAP) − V(VPD), V(VPD) = 5 V ±5 %,
at chip temperature 27 °C
806
V()zap
Zapping voltage
PROG = ’1’
807
V()zpd
Diode voltage, zapped
808
V()uzpd
Diode voltage, unzapped
809
Rpd()VZAP Pull-Down Resistor at VZAP
6.9
V
250
mV
V
7.0
1.2
V
7.1
V
2
V
55
kΩ
2
V
0.4
V
3
V
30
NERR Output
901
Vt()hi
Input Threshold Voltage High
with reference to VND
902
Vs()lo
Saturation Voltage Low
I() = 4 mA , with reference to VND
903
Vt()lo
Input Threshold Voltage Low
with reference to VND
0.8
904
Vt()hys
Input Hysteresis
Vt()hys = Vt()hi − Vt()lo
150
250
905
Ipu(NERR) Pull-up Current
V(NERR) = 0...VPD − 1 V
-700
-300
-80
µA
906
Isc()lo
Short circuit current NERR
V(NERR) = V(VPD), 25°C
50
80
mA
907
tf(NERR)
Decay time NERR
CL = 50 pF
60
ns
V
mV
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 6/23
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Line Driver Outputs
P01 Vs()hi
Saturation Voltage hi
Typ.
Max.
Vs() = VPD − V();
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
200
700
700
400
mV
mV
mV
mV
200
700
700
400
mV
mV
mV
mV
P02
Vs()lo
Saturation Voltage lo
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
P03
Isc()hi
Short-Circuit Current hi
V() = 0 V;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
-12
-120
-120
-60
-4
-50
-50
-20
mA
mA
mA
mA
V() = VPD;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
4
50
50
20
12
120
120
60
mA
mA
mA
mA
P04
P05
P06
P07
Isc()lo
Short-Circuit Current lo
Ilk()tri
Leakage Current Tristate
TRIHL(1:0) = 11
-100
100
µA
tr()
Rise-Time lo to hi at Q
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
tf()
Fall-Time hi to lo at Q
OPERATING REQUIREMENTS: Serial Interface
Operating conditions: VPA, VPD = 5 V ±10 %, Ta = -40...125 °C, IBM calibrated to 200 µA;
Logic levels referenced to VND: lo = 0...0.45 V, hi = 2.4 V...VPD
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SSI Protocol (ENSSI = 1)
I001 TMAS
Permissible Clock Period
250
2x tout
ns
I002 tMASh
Clock Signal Hi Level Duration
tout determined by CFGTOS
25
tout
ns
I003 tMASl
Clock Signal Lo Level Duration
25
tout
ns
Figure 1: I/O Interface timing with SSI protocol
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 7/23
Registers
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hall Signal Conditioning
0x00
z
GAING(1:0)
GAINF(5:0)
0x01
z
ENAC
GCC(6:0)
0x02
z
-
VOSS(6:0)
0x03
z
PRM
VOSC(6:0)
0x04
z
HCLH
DPU
-
CFGTOB
CIBM(3:0)
RS422 Driver
0x05
z
ENSSI
CFGPROT
CFGO(1:0)
TRIHL(1:0)
CFGDR(1:0)
Sine/Digital Converter
0x06
z
CFGRES(7:0)
0x07
z
0x08
z
0x09
z
0x0A
z
0x0B
z
-
0x0C z
-
0x0D
-
CFGZPOS(7:0)
CFGHYS(1:0)
CFGDIR
CFGMTD
CFGSU
CFGPOLE
CFGAB(1:0)
CfgCOM(7:0)
-
CFGMTD2
Test settings
0x0E p
0x0F
TEST(7:0)
-
res.
res.
res.
-
-
-
PROGZAP
ZAP diodes (read only)
0x10
..
0x1F
ZAP dioden for adresses 0x00..0x0C und 0x7D..0x7F
not used
0x20
..
0x41
’invalid adresses’
Profile identification (read only)
0x42
Profile - 0x2C
0x43
Profile - 0x0
Data length DLEN
not used
0x44
..
0x75
’invalid adress’
Status messages (read only; messages will be set back during reading)
0x76
0x77
GAIN
PROGERR
ERRSDATA
ERRAMIN
ERRAMAX
ERREXT
res.
res.
PROGOK
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 8/23
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Identification (0x78 bis 0x7B read-only)
0x78
Device ID - 0x4D (’M’)
0x79
Device ID - 0x48 (’H’)
0x7A
Revision - 0x5A (’Z’)
0x7B
Revision - 0x00 (”)
0x7C
-
0x7D z
CFGTOS
Manufacturer Revision - 0x00
0x7E
z
Manufacturer ID - 0x00
0x7F
z
Manufacturer ID - 0x00
z: Register value programmable by zapping
p: Register value write protected; can only be changed while V(VZAP)> Vt()hi
Table 5: Register layout
Hall signal processing . . . . . . . . . . . . . . . . . . . . Page 10
Sine/digital converter . . . . . . . . . . . . . . . . . . . . . Page 16
GAING:
GAINF:
CFGRES:
CFGZPOS:
CFGAB:
CFGPOLE:
CFGSU:
CFGMTD:
CFGDIR:
CFGHYS:
CFGCOM:
Resolution of sine digital converter
Zero point for position
Configuration of incremental output
No. of poles for commutation signals
Behavior during start-up
Frequency at AB
Rotating direction reversal
Hysteresis sine/digital converter
Zero point for commutation
Test
TEST:
PROGZAP:
Test mode
Activation of programming routine
GCC:
ENAC:
VOSS:
VOSC:
PRM:
CIBM:
DPU
HCLH
Hall signal amplification range
Hall signal amplification (1–20, log.
scale)
Amplification calibration cosine
Activation of amplitude control
Offset calibration sine
Offset calibration cosine
Energy-saving mode
Calibration of bias current
Deactivation of NERR pull-up
Activation of high Hall clock pulse
RS422 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
CFGDR:
TRIHL:
CFGO:
CFGPROT:
ENSSI:
Driver property
Tristate high-side/low-side driver
Configuration of output mode
Write/read protection memory
Activation of SSI mode
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 9/23
Sensor principle
S
In conjunction with a rotating permanent magnet, the
iC-MH module can be used to create a complete encoder system. A diametrically magnetized, cylindrical permanent magnet made of neodymium iron boron
(NdFeB) or samarium cobalt (SmCo) generates optimum sensor signals. The diameter of the magnet
should be in the range of 3 to 6 mm.
N
z
y
+Bz
B
x
-Bz
C151107-1
Figure 2: Sensor principle
The iC-MH has four Hall sensors adapted for angle
determination and to convert the magnetic field into
a measurable Hall voltage. Only the z-component of
the magnetic field is evaluated, whereby the field lines
pass through two opposing Hall sensors in the opposite direction. Figure 2 shows an example of field vectors. The arrangement of the Hall sensors is selected
so that the mounting of the magnets relative to iC-MH
is extremely tolerant. Two Hall sensors combined provide a differential Hall signal. When the magnet is rotated around the longitudinal axis, sine and cosine output voltages are produced which can be used to determine angles.
Position of the Hall sensors and the analog sensor signal
The Hall sensors are placed in the center of the QFN28
package at 90° to one another and arranged in a circle
with a diameter of 2 mm as shown in Figure 3.
Pin 1 Mark
28
27
26
25
24
23
22
21
1
2
PSIN
PCOS
19
4
18
5
17
NCOS
NSIN
7
(top view)
20
3
6
In order to calculate the angle position of a diametrically polarized magnet placed above the device a difference in signal is formed between opposite pairs of
Hall sensors, resulting in the sine being VSIN = VPSIN VNSIN and the cosine VCOS = VPCOS - VNCOS . The zero
angle position of the magnet is marked by the resulting
cosine voltage value being at a maximum and the sine
voltage value at zero.
This is the case when the south pole of the magnet is
exactly above the PCOS sensor and the north pole is
above sensor NCOS, as shown in Figure 4. Sensors
PSIN and NSIN are placed along the pole boundary so
that neither generate a Hall signal.
16
15
8
9
10
11
12
13
14
C040907-2
Figure 3: Position of the Hall sensors
When a magnetic south pole comes close to the surface of the package the resulting magnetic field has a
positive component in the +z direction (i.e. from the top
of the package) and the individual Hall sensors each
generate their own positive signal voltage.
When the magnet is rotated counterclockwise the
poles then also cover the PSIN and NSIN sensors, resulting in the sine and cosine signals shown in Figure
5 being produced. The signals are internal but can be
made externally available for test purposes (see the
description of iC-MH’s calibration procedure).
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 10/23
28
27
26
25
24
23
22
21
1
18
5
17
6
16
7
8
9
11
12
13
23
28
22
1
2
27
26
25
24
23
(top view)
22
S
21
20
3
19
3
19
4
18
4
18
5
17
5
17
16
6
15
7
6
9
10
11
12
13
14
16
N
8
9
10
11
α>0
15
12
13
14
α=0
0
VSIN= VPSIN- VNSIN VCOS= VPCOS- VNCOS
+2V
15
10
24
N
4
N
19
25
20
8
3
26
21
7
20
S
2
27
1
2
S
28
-90°
90°
180°
270°
360°
α
-2V
14
C041007-3
C040907-1
Figure 4: Zero position of the magnet
Figure 5: Pattern of the analog sensor signals with
the angle of rotation
Hall Signal Processing
The iC-MH module has a signal calibration function
that can compensate for the signal and adjustment
errors. The Hall signals are amplified in two steps.
First, the range of the field strength within which the
Hall sensor is operated must be roughly selected. The
first amplifier stage can be programmed in the following ranges:
GAING(1:0)
Adr 0x00; Bit 7:6
00
01
5-fold
10-fold
01
15-fold
01
20-fold
used. With the amplitude control (ENAC = ’1’) activated, the GAINF register bits have no effect.
GCC(6:0)
1,000
1,0015
...
exp( ln(20)
2048 · GCC)
0x3F
0x40
1,0965
0,9106
...
exp(− ln(20)
2048 · (128 − GCC))
0x7F
0,9985
Table 8: Amplification calibration cosine
Table 6: Range selection for Hall signal amplification
The operating range can be specified in advance in
accordance with the temperature coefficient and the
magnet distance. The integrated amplitude control can
correct the signal amplitude between 1 and 20 via another amplification factor. Should the control reach the
range limits, a different signal amplification must be selected via GAING.
GAINF(5:0)
Adr 0x00; Bit 5:0
0x00
1,000
0x01
...
1,048
exp( ln(20)
64 · GAINF )
0x3F
19,08
Adr 0x01; Bit 6:0
0x00
0x01
The GCC register is used to correct the sensitivity of
the sine channel in relation to the cosine channel. The
cosine amplitude can be corrected within a range of
approximately ±10%.
ENAC
0
1
Adr 0x01; Bit 7
amplitude control deactivated
amplitude control active
Table 9: Activation of amplitude control
Table 7: Hall signal amplification
The second amplifier stage can be varied in an additional range. With the amplitude control (ENAC = ’0’)
deactivated, the amplification in the GAINF register is
The integrated amplitude control can be activated with
the ENAC bit. In this case the differential signal amplitude is adjusted to 4 Vss and the values of GAINF
have no effect here.
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 11/23
PRM
PSIN−NSIN
4Vss
Adr 0x03; Bit 7
0
Energy-saving mode deactivated
1
Energy-saving mode active
PCOS−NCOS
Table 11: Energy-saving mode
Figure 6: Definition of differential amplitude
After switch-on the amplification is increased until the
setpoint amplitude is reached. The amplification is
automatically corrected in case of a change in the
input amplitude by increasing the distance between
the magnet and the sensor, in case of a change in
the supply voltage or a temperature change. The
sine signals are therefore always converted into highresolution quadrature signals at the optimum amplitude.
VOSS(6:0)
Adr 0x02; Bit 6:0
VOSC(6:0)
Adr 0x03; Bit 6:0
0x00
0x01
0 mV
1 mV
...
...
0x3F
63 mV
0x40
0x41
0 mV
-1 mV
...
...
0x7F
-63 mV
Table 10: Offset calibration for sine and cosine
Should there be an offset in the sine or cosine signal
that, among other things, can also be caused by an
inexactly adjusted magnet, then this offset can be corrected by the VOSS and VOSC registers. The output
voltage can be shifted by ±63 mV in each case to compensate for the offset.
In the energy-saving mode the current consumption of
the Hall sensors can be quartered. This also reduces
the maximum rotating frequency by a factor of 4.
CIBM(3:0)
Adr 0x04; Bit 3:0
0x0
-40 %
...
0x8
...
0%
0x9
+5 %
...
0xF
...
+35 %
Table 12: Calibration of bias current
In the test mode (TEST = 0x43) the internal currents
can be calibrated on Pin B. For this purpose, the current must be measured based on VNA and the CIBM
register bits must be changed until the current is calibrated to 200 µA. All internal currents are then calibrated.
HCLH
0
1
Adr 0x04; Bit 7
250 kHz
500 kHz
Table 13: Activation of high Hall clock pulse
The switching-current hall sensors can be operated at
two frequencies. At 500 kHz the sine has twice the
number of support points. This setting is of interest at
high speeds above 30,000 rpm.
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 12/23
Test modes for signal calibration
For signal calibration iC-MH has several test settings
which make internal reference quantities and the amplified Hall voltages of the individual sensors accessible at external pins A, B, Z and U for measurement purposes. This enables the settings of the offset (VOSS,
VOSC), gain (GAING, GAINF) and amplitude ratio of
the cosine to the sine signal (GCC) to be directly observed on the oscilloscope.
iC-MH
PSIN
B
B
A
HPSP
B
HPSN
Z
HNSP
U
HNSN
B
B
VPSIN
VNSIN
NSIN
HALL SENSORS
Test mode can be triggered by connecting pin VZAP
to VPD and programming the TEST register (address
0x0E). The individual test modes are listed in the following table:
Output signals in test mode
Mode
TEST Pin A Pin B
Normal
0x00 A
B
Analog SIN
0x20 HPSP HPSN
Analog COS 0x21 HPCP HPCN
Analog OUT 0x22 PSIN NSIN
Analog REF 0x43 VREF IBM
Digital CLK
0xC0 CLKD
Pin Z
Z
HNSP
HNCP
PCOS
VBG
VNA
C021107-1
Test Mode: Analog SIN
Figure 7: Output signals of the sine Hall sensors in
test mode Analog SIN
Pin U
U
HNSN
HNCN
NCOS
VOSR
iC-MH
PCOS
B
B
A
HPCP
B
HPCN
Z
HNCP
U
HNCN
B
B
VPCOS
VNCOS
NCOS
HALL SENSORS
Table 14: Test modes and available output signals
VNA
C021107-2
The output voltages are provided as differential signals with an average voltage of 2.5 V. The gain is determined by register values GAING and GAINF and
should be set so that output amplitudes from the sine
and cosine signals of about 1 V are visible.
Test modes Analog SIN and Analog COS
In these test modes it is possible to measure the signals from the individual Hall sensors independent of
one another. The name of the signal is derived from
the sensor name and position. HPSP, for example,
is the (amplified) Hall voltage of sensor PSIN at the
positive signal path; similarly, HNCN is the Hall voltage
of sensor NCOS at the negative signal path. The effective Hall voltage is accrued from the differential voltage
between the positive and negative signal paths of the
respective sensor.
Test mode Analog OUT
In this test mode the sensor signals are available at
the outputs as they would be when present internally
for further processing on the interpolator. The interpolation accuracy which can be obtained is determined
by the quality of signals Vsin and Vcos and can be influenced in this particular test mode by the calibration of
the offset, gain and amplitude ratio.
Test Mode: Analog COS
Figure 8: Output signals of the cosine Hall sensors
in test mode Analog COS
iC-MH
PSIN
PCOS
B
B
NCOS
A
PSIN
B
NSIN
Z
PCOS
U
NCOS
B
B
VSIN
VCOS
NSIN
HALL SENSORS
C021107-3
VNA
Test Mode: Analog OUT
Figure 9: Differential sine and cosine signals in test
mode Analog OUT
Test mode Analog REF
In this mode various internal reference voltages are
provided. VREF is equivalent to half the supply voltage
(typically 2.5 V) and is used as a reference voltage for
the Hall sensor signals. VBG is the internal bandgap
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 13/23
reference (1.24 V), with VOSR (0.5 V) used to generate the range of the offset settings. Bias current IBM
determines the internal current setting of the analog
circuitry. In order to compensate for variations in this
current and thus discrepancies in the characteristics
of the individual iC-MH devices (due to fluctuations in
production, for example), this can be set within a range
of -40% to +35% using register parameter CIBM. The
nominal value of 200 µA is measured as a short-circuit
current at pin B to ground.
A
VREF
B
IBM
Z
VBG
~ 1.24 V
U
VOSR
~ 0.5 V
~ 2.5 V
~ 200 µA
C021107-4
Test mode Digital CLK
If, due to external circuitry, it is not possible to measure IBM directly, by way of an alternative clock signal
CLKD at pin A can be calibrated to a nominal 1 MHz
in this test mode via register value CIBM.
Test Mode: Analog REF
iC-MH
VNA
Figure 10: Setting bias current IBM in test mode
Analog REF
Calibration procedure
The calibration procedure described in the following
applies to the optional setting of the internal analog
sine and cosine signals and the mechanical adjustment of the magnet and iC-MH in relation to one another.
BIAS SETTING
The BIAS setting compensates for possible manufacturing tolerances in the iC-MH devices. A magnetic
field does not need to be present for this setting which
can thus be made either prior to or during the assembly of magnet and iC-MH.
If the optional setup process is not used, register CIBM
should be set to an average value of 0x8 (which is
equivalent to a change of 0%). As described in the
previous section, by altering the value in register CIBM
in test mode Analog REF current IBM is set to 200 µA
or, alternatively, in test mode Digital CLK signal CLKD
is set to 1 MHz.
MECHANICAL ADJUSTMENT
iC-MH can be adjusted in relation to the magnet in test
modes Analog SIN and Analog COS, in which the Hall
signals of the individual Hall sensors can be observed
while the magnet rotates.
In test mode Analog SIN the output signals of the sine
Hall sensors which are diagonally opposite one another are visible at pins A, B, Z and U. iC-MH and the
magnet are then adjusted in such a way that differential signals VPSIN and VNSIN have the same amplitude
and a phase shift of 180°. The same applies to test
mode Analog COS, where differential signals VPCOS
and VNCOS are calibrated in the same manner.
Vsin
+2 V
α
-2 V
+2 V
Vcos
-2 V
C141107-1
Figure 11: Ideal Lissajous curve
CALIBRATION USING ANALOG SIGNALS
In test mode Analog OUT as shown in Figure 5 the internal signals which are transmitted to the sine/digital
converter can be tapped with high impedance. With
a rotating magnet it is then possible to portray the differential signals VSIN and VCOS as an x-y graph (Lissajous curve) with the help of an oscilloscope. In an
ideal setup the sine and cosine analog values describe
a perfect circle as a Lissajous curve, as illustrated by
Figure 11.
At room temperature and with the amplitude control
switched off (ENAC = 0) a rough GAING setting is selected so that at an average fine gain of GAINF = 0x20
(a gain factor of ca. 4.5) the Hall signal amplitudes are
as close to 1 V as possible. The amplitude can then
be set more accurately by varying GAINF. Variations in
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 14/23
the gain factor, as shown in Figure 12, have no effect
on the Lissajous curve, enabling the angle information
for the interpolator to be maintained.
Vsin
VOSS
Vsin
α
GAING
GAINF
Vcos
α
C141107-3
Vcos
Figure 13: Effect of the sine offset setting
Vsin
VOSC
C141107-2
Figure 12: Effect of gain settings GAING and
GAINF
α
Deviations of the observed Lissajous curve from the
ideal circle can be corrected by varying the amplitude offset (register VOSS, VOSC) and amplitude ratio
(register GCC). Changes in these parameters are described in the following figures 13 to 15. Each of these
settings has a different effect on the interpolated angle
value. A change in the sine offset thus has a maximum
effect on the angle value at 0° and 180°, with no alterations whatsoever taking place at angles of 90° and
270°. When varying the cosine offset exactly the opposite can be achieved as these angle pairs can be set
independent of one another. Setting the cosine/sine
amplitude ratio does not change these angles (0°, 90°,
180° and 270°); however, in-between values of 45°,
135°, 225° and 315° can still be influenced by this parameter.
Once calibration has been carried out a signal such as
the one illustrated in Figure 11 should be available.
In the final stage of the process the amplitude control
can be switched back on (ENAC =1) to enable deviations in the signal amplitude caused by variations in
the magnetic field due to changes in distance and temperature to be automatically controlled.
Vcos
C141107-4
Figure 14: Effect of the cosine offset setting
Vsin
GCC
α
Vcos
C141107-5
Figure 15: Effect of the amplitude ratio
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 15/23
CALIBRATION USING INCREMENTAL SIGNALS
If test mode cannot be used, signals can also be calibrated using the incremental signals or the values read
out serially. In order to achieve a clear relationship between the calibration parameters which have an effect
on the analog sensor signals and the digital sensor values derived from these, the position of the zero pulse
should be set to ZPOS = 0 so that the digital signal
starting point matches that of the analog signals.
At an incremental resolution of 8 edges per revolution (CFGRES = 0x1) those angle values can be displayed at which calibration parameters VOSS, VOSC
and GCC demonstrate their greatest effect. When rotating the magnet at a constant angular speed the incremental signals shown in Figure 16 are achieved,
with which the individual edges ideally succeed one
another at a temporal distance of an eighth of a cycle (a 45° angle distance). Alternatively, the angle position of the magnet can also be determined using a
reference encoder, rendering an even rotational action
unnecessary and allowing calibration to be performed
using the available set angle values .
The various possible effects of parameters VOSS,
VOSC and GCC on the flank position of incremental
signals A and B are shown in Figure 16. Ideally, the
distance of the rising edge (equivalent to angle positions of 0° and 180°) at signal A should be exactly half
a period (PER). Should the edges deviate from this in
distance, the offset of the sine channel can be adjusted
using VOSS. The same applies to the falling edges of
the A signal which should also have a distance of half
a period; deviations can be calibrated using the offset
of cosine parameter VOSC. With parameter GCC the
distance between the neighboring flanks of signals A
and B can then be adjusted to the exact value of an
eighth of a cycle (a 45° angle distance).
Figure 16: Calibration using incremental signals
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 16/23
Sine/Digital Converter
100%
40%
50%
60%
The iC-MH module integrates two separate sine/digital
converters. A high-resolution 12-bit converter for the
ABZ incremental signals can be programmed in broad
ranges of the resolution and generate quadrature signals even at the highest speed and resolution. The
converter operates for the commutation signals independently of this and can be set in the zero point separately from the quadrature converter. This enables
the commutation at other angles based on the index
track Z.
A
B
Z
Figure 17: ABZ signals and relative accuracy
CFGRES(7:0)
0x0
1
0x1
2
...
0x7e
...
127
0x7f
128
0x80
0x81
256
512
0x82
1024
Adr 0x06; Bit 7:0
The incremental signals can be inverted again independently of the output drivers. As a result, other
phase angles of A and B relative to the index pulse Z
can be generated. The standard is A and B high level
for the zero point, i.e. Z is equal to high.
Table 15: Programming interpolation factor
The resolution of the 12-bit converter can virtually be
set as desired. Any resolution can be set up to an interpolation factor of 128, i.e. 512 edges per rotation. At
higher resolutions, only the binary resolutions can be
set, i.e. 256, 512 and 1024. In the highest resolution
with an interpolation factor of 1024, 4096 edges per
rotation are generated and 4096 angular steps can be
differentiated. Even in the highest resolution, the absolute position can be calculated in real time at the maximum speed. After the resolution is changed, a module
reset is triggered internally and the absolute position is
recalculated.
CFGAB(1:0)
Adr 0x08; Bit 1:0
0x0
A and B not inverted
0x1
0x2
B inverted, A normal
A inverted, B normal
0x3
A and B inverted
Table 16: Inversion of AB signals
Figure 17 shows the position of the incremental signals around the zero point. The relative accuracy of
the edges to each other at a resolution setting of 10
bit is better than 10%. This means that, based on a
period at A or B, the edge occurs in a window between
40% and 60%.
CFGHYS(1:0)
0x0
0x1
0,17°
0,35°
0x2
0,7°
0x3
1,4°
Adr 0x08; Bit 7:6
Table 17: Programming angular hysteresis
With rotating direction reversal, an angular hysteresis
prevents multiple switching of the incremental signals
at the reversing point. The angular hysteresis corresponds to a slip which exists between the two rotating
directions. However, if a switching point is approached
from the same direction, then the edge is always generated at the same position on the output. The following figure shows the generated quadrature signals
for a resolution of 360 edges per rotation (interpolation
factor 90) and a set angular hysteresis of 1.4°.
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 17/23
10°
0°
−10°
A
B
Z
0°
1.4°
0°
Figure 18: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accordance with the hysteresis, the return edge is generated
at A again first. This means that all edges are shifted
by the same value in the rotating direction.
The rotating direction can easily be changed with
the bit CFGDIR. When the setting is CCW (counterclockwise, CFGDIR = ’0’) the resulting angular position
values will increase when rotation of the magnet is performed as shown in figure 5. To obtain increasing angular position values in the CW (clockwise) direction,
CFGDIR then has to be set to ’1’.
The internal analoge sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure
5.
CFGSU
0
1
Adr 0x08; Bit 3
ABZ output "111" during startup
AB instantly counting to actual position
Table 21: Configuration of output startup
CFGZPOS(7:0)
Adr 0x07; Bit 7:0
0x0
0x1
0°
1,4°
0x2
2,8°
...
0xff
360
256 ·CFGZPOS
358,6°
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z-pulse once over 360°.
CFGMTD2
CFGMTD
Minimum edge spacing
0
0
0
1
500 ns
125 ns
max. 500 kHz at A
max. 2 MHz at A
1
0
8 µs
max. 31.25 kHz at A
1
1
2 µs
max. 125 kHz at A
Table 19: Minimum edge spacing
The CFGMTB register defines the time in which two
consecutive position events can be output. The default is a maximum output frequency of 500 kHz on A.
This means that at the highest resolution, speeds of
30,000 rpms can still be correctly shown. In the setting with an edge spacing of 125 ns, the edges can be
generated even at the highest revolution and the maximum speed. However, the counter connected to the
module must be able to correctly process all edges in
this case. The settings with 2 µs, and 8 µs can be used
for slower counters. It should be noted then, however,
that at higher resolutions the maximum rotation speed
is reduced.
CFGDIR
Adr 0x08; Bit 5
0
Rotating direction CCW
1
Rotating direction CW
Table 20: Rotating direction reversal
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, first
the current position is determined. During this phase,
the quadrature outputs are constantly set to "111" in
the setting CFGSU = ’0’. In the setting CFGSU = ’1’,
edges are generated at the output until the absolute
position is reached. This enables a detection of the
absolute position with the incremental interface.
The converter for the generation of the commutation
signals can be configured for two and four-pole motors. Three rectangular signals each with a phase shift
of 120° are generated. With two-pole commutation, the
sequence repeats once per rotation. With a four-pole
setting, the commutation sequence is generated twice
per rotation.
CFGPOLE
Adr 0x8; Bit 1
0
2 pole commutation
1
4 pole commutation
Table 22: Commutation
The zero position of the commutation, i.e. the rising
edge of the track U, can be set as desired over a rotation. Here 192 possible positions are available. Values
above 0xC0 are the mirrored positions from 0x70.
CFGPOLE(7:0)
Adr 0x09; Bit 7:0
0x00
0°
0x01
...
1,875°
360
192 · CFGCOM
0xBF
358,125°
Table 23: Commutation
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 18/23
Output Drivers
Six RS422-compatible output drivers are available,
which can be configured for the incremental signals
and commutation signals. The following table on the
CFGO register bits provides an overview of the possible settings.
PSIN
PCOS
A
iC−MH
B
CFGO(1:0)
Adr 0x07; Bit 7:6
00
01
Incrementral Diff ABZ (U=NA, V=NB, W=NZ)
Incr ABZ + Comm UVW
10
Commutation Diff UVW (A=NU, B=NV, Z=NW)
11
Incr. ABZ + AB4 (U=A4, V=B4, W=0)
Z
U
V
W
Figure 19: ABZ differential incremental signals
PSIN
PCOS
Table 24: Configuration of output drivers
A
In the differential incremental mode (CFGO = ’00’, Figure 19), quadrature signals are available on the Pins
A, B and Z. The respective inverted quadrature signals are available on the pins U, V and W. As a result,
lines can be connected directly to the module. Another
configuration of the incremental signals is specified in
the section "Sine/Digital Converter".
iC−MH
B
Z
U
V
W
Figure 20: ABZ incremental / UVW commutation
signals
PSIN
PCOS
A
B
iC−MH
With CFGO = ’01’ (Figure 20) the ABZ incremental signals and the UVW commutation signals are available
on the six pins. As long as the current angular position is not yet available during the start-up phase, all
commutation signals are at the low level.
Z
U
V
W
With CFGO = ’10’, the third mode (Figure 21) is available for transferring the commutation signals via a differential line. The non-inverted signals are on the pins
U, V and W, the inverted signals on A, B and Z.
Figure 21: UVW differential commutation signals
PSIN
PCOS
A
The ABZ quadrature signals with an adjustable higher
resolution and quadrature signals with one period per
rotation are available in the fourth mode (Figure 22).
Four segments can be differentiated with the pins U
and V. This information can be used for an external
period counter which counts the number of scanned
complete rotations.
iC−MH
B
Z
U
V
W
Figure 22: ABZ incremental signals / period counter
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 19/23
enable a high transmission rate. A lower slew rate is
offered by the setting CFGDR = ’10’, which is excellent for longer lines in an electromagnetically sensitive
environment. Use of the setting CFGDR = ’11’ is advisable at medium transmission rates with a limited driver
capability.
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
CfgDR(1:0)
00
Adr 0x07; Bit 1:0
10 MHz 4 mA (default)
01
10 MHz 60 mA
10
11
300 kHz 60 mA
3 MHz 20 mA
TRIHL
Adr 0x07; Bit 3:2
00
Push Pull Output Stage
Table 25: Driver property
01
10
Lowside Driver
Highside Driver
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital input on the same assembly. With the setting CFGDR
= ’01’ the same transmission speed is available and
the driver power is sufficient for the connection of a
line over a short distance. Steep edges on the output
11
Tristate
Table 26: Tristate Register
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.
Serial Interface
The serial interface is used to read out the absolute
position and to parameterize the module. For a de-
tailed description of the protocol, see separate interface specification.
MA
CDM
SLI
SLO
Ack Start CDS D11 D10
D0
nE
nW CRC5 CRC4
CRC0 Stop
Timeout
Data Range
Figure 23: Serial Interface Protocol
The sensor sends a fixed cycle-start sequence containing the Acknowledge-, Start and Control-Bit followed by the binary 12 bit sensor data. At lower resolution settings the data word contains leading zeros. The
low-active error bit nE a ’0’ indicates an error which
can be further identified by reading the status register
0x77. The following bit nW is always at ’1’ state. Following the 6 CRC bits the data of the next sensors, if
available, are presented. Otherwise, the master stops
generating clock pulse on the MA line an the sensor
runs into a timeout, indicating the end of communication.
Serial Interface
Protocol
Mode C
Cycle start sequence
Ack/Start/CDS
Lenght of sensor data
CRC Polynom
12 Bit + ERR + WARN
0b1000011
CRC Mode
inverted
Multi Cycle Data
max. Data Rate
not available
10 MHz
Table 27: Interface Protocol
ENSSI
Adr 0x05; Bit 7
0
Extended SSI-Mode
1
SSI-Mode
Table 28: Activation of SSI mode
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. However, in the SSI
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 20/23
mode it is not possible to vary the parameter set. The
data is transmitted as reduced Gray code, e.g. after
converting into binary code, the data range is symmetrical to the center of the number string. For example,
with a set resolution of 360 data values between 76
and 435 are transmitted.
Figure 24: SSI protocol, data GRAY-coded
The register range 0x00 to 0x0F is equivalent to the
settings with which the IC can be parameterized. The
settings directly affect the corresponding switching
parts. It is important to note that test register 0x0E can
only be written to when pin VZAP is connected to VPD.
When VPD > 6 V, write access to the test register is ignored. Register 0x0F can be configured at potentials
V(VZAP) > Vt(VZAP)hi.
The range 0x10 to 0x1F is read-only and reflects the
contents of the integrated zapping diodes. Following
programming the data can be verified via these addresses. After the supply voltage is connected, the
contents of the zapping diodes are copied to the RAM
area 0x00 to 0x0F. Then the settings can be overwritten via the serial interface. Overwriting is not possible
if the CFGPROT bit is set.
Errors in the module are signaled via the error message output NERR. This open-drain output signals an
error if the output is pulled against VND. If the error condition no longer exists, then the pin is released
again after a waiting time of approximately 1 ms. If the
integrated pull-up resistor is deactivated with DPU =
’1’, then an external resistor must be provided. With
DPU = ’0’ it brings the pin up to the high level again.
DPU
Adr 0x04; Bit 6
0
Pull-up activated
1
Pull-up deactive
Table 29: Activation of NERR pull-up
With the profile ID, the data format can be requested
for the following sensor data cycles in the module. A
read operation at address 0x42 results in 0x2C, with is
the equivalent to 12-bit single-cycle data. The register
0x43 which follows now contain the data length DLEN
of the transmitted sensor data in accordance with the
set resolution. The sensor data are transmitted right-
justified and filled with preceding zeros if necessary.
The following table shows the data length according to
the resolution.
DLEN
Adr 0x43; Bit 3:0
2
3
CFGRES = ’00000000’, 4
CFGRES = ’00000001’, 8
4
5
CFGRES = ’0000001x’, 12 to 16
CFGRES = ’000001xx’, 20 to 32
6
CFGRES = ’00001xxx’, 36 to 64
7
8
CFGRES = ’0001xxxx’, 68 to 128
CFGRES = ’001xxxxx’, 132 to 256
9
CFGRES = ’01xxxxxx’, 260 to 512
10
11
CFGRES = ’10000000’, 1024
CFGRES = ’10000001’, 2048
12
CFGRES = ’10000010’, 4096
Table 30: Data length
The status register provides information on the status
of the module. There are 5 different errors that can
be signaled. Following unsuccessful programming of
the zapping diodes, the bit PROGERR is set. If an
attempt is made to read the current position via the serial interface during the start-up phase, an error is signaled with ERRSDATA, as the actual position is not yet
known. The ERRAMAX bit is output to signal that the
amplitude is too high, while the ERRAMIN bit signals
an amplitude which is too low, caused, for example, by
too great a distance to the magnet. If the NERR pin
is pulled against VND outside the module, this error is
also signaled via the serial interface. The ERREXT bit
is then equal to ’1’. The error bits are reset again after
the status register is read out at the address 0x77. The
error bit in the data word is then also read in the next
cycle as ’0’.
CFGTOS
0
1
x
CFGTOB
0
Timeout
16 µs
0
2 µs
1
2 µs
Table 31: Timeout for sensor data
The timeout can be programmed to a shorter value
with the CFGTOS bit. However, this setting is reset
to the default value 16 µs again following a reset. The
timeout can be permanently programmed for faster
data transmission with the CFGTOB register via a zapping diode. Resetting to slower data transmission is
then not possible.
The registers 0x7D to 0x7F are reserved for the manufacturer and can be provided with an ID so that the
manufacturer can identify its modules
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 21/23
OTP Programming
CFGPROT
0
1
Adr 0x05; Bit 6
START
no protection
write/read protection
SET CONFIGURATION
Table 32: Write/read protection of configuration
With CFGPROT = ’0’, the registers at the addresses
0x00 to 0x0F and 0x78 to 0x7F are readable and writeable. The addresses 0x10 to 0x1F and 0x77 are readonly. With CFGPROT = ’1’, all registers except the addresses 0x7B and 0x7C are write-protected; the addresses 0x77 to 0x7F are readable, while all others
are read-protected.
100nF
SET CIBM = 0x0
START HW ZAP ALGORITHM
SET ADR 0x0F = 0x01
VPD = VPA = 5.0V
FALSE
100nF
VPA
TRUE
VPD
FALSE
+5V
+7V
VZAP
100nF
iC-MH
+ 10uF
MA
Programming
Board
Serial
Interface
SLI
SLO
VNA
VND
VERIFY
VPD = VPA = 5.5V
CIBM = 0x0
SET CIBM
VERIFY
VPD = VPA = 4.0V
CIBM = 0xF
TRUE
CIBM programmed?
FALSE
TRUE
0V
STOP
Figure 25: Programming within system
Figure 26: Programming algorithm
An internal programming algorithm for the ZAP diodes
is started by setting the bit PROGZAP. This process
can only be successful, if the voltage difference between VZAP and VNA pin is within the specified value
and the test register is set to TEST = 0x00. Following
programming, the PROGZAP bit is reset automatically.
In the process, the bit PROGOK is set in the status register (address 0x77) when programming is successful,
and the bit PROGERR, if it is not.
Once the device has been successfully calibrated the
configuration can be written into the device. To this
end the contents of the RAM bits are transferred to
the ROM zapping structure. CIBM is first set to 0x0
at address 0x04 and the hardware programming algorithm started by bit PROGZAP. Programming should
be monitored with the threshold settings for CIBM and
VPD, VPA voltage by reading out the ZAP structures
via the serial interface. If programming is not successful, the hardware programming algorithm can again be
initiated. In the second stage of the procedure the bias
current is programmed in the CIBM register. Here, all
RAM bits are set to 0x00; register CIBM is configured
with the calculated calibration value and the programming algorithm started. Programming is successful
when all bits have been configured.
A 100 nF ceramic block capacitor must be placed on
board directly between VZAP and VNA pins of the iCMH. Also a 10 µF capacitor must be present at the
end of the programming line as close to the connector as possible (see figure 25). During programming
up to 100 mA flow from pin VZAP to pin VNA, making
it necessary to ensure proper PCB layout to minimize
voltage drops.
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 22/23
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein,
design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data.
Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions
in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of
merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 23/23
ORDERING INFORMATION
Type
Package
Order Designation
iC-MH
QFN28
iC-MH QFN28
iC-MH EVAL MH1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.de/support_distributors.php