ICHAUS MHL200

preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 1/28
FEATURES
APPLICATIONS
♦
♦
♦
♦
♦
♦
♦ Motion control
♦ Linear position encoders
♦ Incremental off-axis rotary
encoders
♦
♦
♦
♦
♦
♦
♦
Realtime system for linear speed up to 8 m/s at full resolution
Absolute position within the magnetic period of 4 mm
12-bit interpolation w. 4096 increments, resolution better 1 µm
Automatic signal offset compensation
Automatic amplitude control for optimum operating point
Programmable features: interpolation factor, hysteresis,
minimum phase distance, zero position and code direction
Electronic index generation with multi-purpose enable input
RS422-compatible A/B/Z outputs for encoder quadrature
signals with up to 8 MHz edge rate
Serial I/O interface for high-speed data output (BiSS/SSI) and
configuration (BiSS)
Zener-Zap ROM for non-volatile setup and OEM data
Signal monitoring: loss of signal, excessive frequency
Single 5 V supply
Extended temperature range of -40 to +125 °C
PACKAGES
TSSOP20
BLOCK DIAGRAM
+ 5V
+ 5V
VPA
GAIN
ENZ
VPD
A
B
B
B
B
B
HALL SENSORS
CONVERSION
LOGIC
Z
SINE-TO-DIG
PTE
RS422
TEST
2
SIN + COS
U
2
NERR
V
AMPLITUDE
CORRECTION
ERROR MONITOR
SINE-TO-COM
W
INCR INTERFACE
iC-MHL200
MA
0x00
0x0F
0x10
S LO
16 Byte ZROM
0x1F
S LI
SERIAL
INTERFACE
Copyright © 2013 iC-Haus
AMPL CONTROL
PHASE
SHIFT
0x77
0x7F
ZAP CONTROL
RAM
BIAS/VREF
VNA
VND
V Z AP
ZAPROM
http://www.ichaus.com
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 2/28
DESCRIPTION
The iC-MHL200 is a magnetic position sensor with
integrated Hall sensors for the scanning of magnetic
tapes and pole wheels featuring a pole pitch of 2 mm.
Moving speeds of up to 8 m/s can be followed even
at highest resolution representing 0.98 µm.
The signal conditioning unit generates constantamplitude sine and cosine voltages that are used
for real-time tracking sine-to-digital angle conversion.
The resolution can be programmed up to a maximum
of 4,096 increments within one magnetic period of
4 mm.
The integrated serial interface enables daisy-chain
operation of multiple devices with a synchronous position capture at all networked sensors. The device’s
memory can also be accessed via the bidirectional
BiSS C protocol without interfering the readout cycles.
The incremental interface with the pins A, B and Z
supplies encoder quadrature signals at an edge rate
of up to 8 MHz. Complementary incremental signals
are available at the U, V, W outputs. The index position at the Z output is adjustable and can be gated
via enable input ENZ.
A/B/Z and U/V/W form RS422-compatible outputs
and are programmable regarding the output’s drive
current and slew rate.
A gain-dependent analog signal is available at the
GAIN output, which can be used to monitor mechanical alignment of the sensor with respect to the magnetic target.
All device parameters can be stored in the internal non-volatile Zener-zapping ROM to allow selfconfiguration after power on. The required writing
algorithm for programming is executed by the IC itself.
Together with the appropriate magnetic scale or pole
wheel, the iC-MHL200 provides a single-chip solution
for linear and rotary encoders.
PACKAGING INFORMATION TSSOP20
PIN CONFIGURATION TSSOP20
PIN FUNCTIONS
No. Name Function
1
20
2
19
3
18
4
17
5
16
SLI
SLO
MA
ENZ
VPA
GAIN
VNA
NERR
7
VZAP
8
A
9
B
10
Z
Orientation of the logo (
MHL200
n.c.
Code...
6
...yyww
n.c.
PTE
15
W
14
V
13
U
12
VPD
11
VND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SLI
MA
VPA
VNA
nc
nc
VZAP
A
B
Z
VND
VPD
U
V
W
PTE
NERR
GAIN
ENZ
SLO
MHL CODE ...) is subject to alteration.
Serial Interface, Data Input
Serial Interface, Clock Input
+5 V Supply Voltage (analog)
Ground (analog)
not connected
not connected
Zener Zapping Programming Voltage
Inkremental A (+ NU)
Inkremental B (+ NV)
Index Z (+ NW)
Ground (digital)
+5 V Supply Voltage (digital)
Commutation U (+NA)
Commutation V (+NB)
Commutation W (+NZ)
Test Enable Pin
Error output (active low)
Gain-Signal
Enable Index Z
Serial Interface, Data Output
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 3/28
CHIP-LAYOUT
Chip size: 4.13 mm x 2.80 mm
GAIN
NERR
PTE
W
U
V
ENZ
VPD
SLO
VND
SLI
Z
MA
B
VPA
A
VZAP
VNA
Figure 1: MHL200 Chip with contact pads shown in grey, Hall sensors shown in black
HALL sensor locations
All dimensions in mm
20
1.0
SP_B
SP_C
1.0
SP_B
SP_C
SP_C
SP_B
1.0
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
1.21
1
Figure 2: Hall sensor array of four sensor pairs spaced 1mm apart.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 4/28
Chip location within TSSOP20 package
hsens
xdis
20
SP_B
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
SP_C
SP_C
SP_B
SP_C
SP_B
ydis
φdis
center of chip
1
Figure 3: Definiton of lateral and rotational displacements
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 5/28
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Supply voltages at VPA, VPD
-0.3
6
V
G002 V(VZAP)
Zapping voltage
-0.3
8
V
G003 V()
Voltages at A, B, Z, U, V, W, MA, SLO,
SLI, NERR, PTE
-0.3
6
V
G004 I()
Current in VPA
-10
20
mA
G005 I()
Current in VPD
-20
200
mA
G006 I()
Current in A, B, Z, U, V, W
-100
100
mA
G007 I()
Current in MA, SLO, SLI, NERR, PTE
-10
10
mA
G008 Vd()
ESD-voltage, all pins
2
kV
G009 Ts
Storage temperature
-40
150
°C
G010 Tj
Chip temperature
-40
135
°C
HBM 100 pF discharged over 1.5 kΩ
THERMAL DATA
Operating conditions: VPA, VPD = 5 V ±10 %
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
T01
Ta
Ambient temperature
T02
Rthja
Thermal resistance chip/ambient
Typ.
-40
package mounted on PCB
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
Max.
125
100
°C
K/W
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 6/28
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
General
001
V(VPA,
VPD)
Supply Voltage Range
4.5
5.5
V
002
I(VPA)
Supply Current in VPA
003
I(VPD)
Supply Current in VPD
PRM = ’0’, without Load
5
8
mA
10
16
004
I(VPD)
Supply Current in VPD
PRM = ’1’, without Load
4
mA
8
005
Vc(hi)
Clamp Voltage hi at MA, SLI,
SLO, PTE, NERR
Vc()hi = V() − VPD, I() = 1 mA
mA
0.4
1.5
V
006
Vc(lo)
Clamp Voltage lo
I() = -1 mA
-1.5
-0.3
V
20
100
kA/m
2
8
kHz
m/s
Hall Sensors and Signal Conditioning
101
Hext
Operating Magnetic Field
Strength
At Chip Surface
102
fmag
Operating Magnetic Field Frequency
Linear Speed
with resolution set to 4096, MTD set to 125 ns
105
xdis, ydis
Displacement Chip to Package
TSSOP package, see Figure 3
-0.2
0.2
mm
106
φpac
Angular alignment of chip vs.
package
TSSOP package, see Figure 3
-3
+3
Deg
107
hsens
Distance of chip surface to top of TSSOP package, see Figure 3
package surface
108
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x7F
109
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x3F
110
Vopt
Optimal differential output voltage Vopt = Vpp(PSIN) − Vpp(NSIN), ENAC = ’0’,
see Fig. 10
0.4
mm
-55
55
mV
mV
4
Vpp
Amplitude Control
201
Vampl
Differential Output Amplitude
Vampl = Vpp(PSIN) − Vpp(NSIN), ENAC = ’1’,
see Fig. 10
3.2
202
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS)
1.09
203
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS)
0.91
204
tampl
Settling Time of Amplitude Control
±10%
300
µs
205
Vae()lo
Amplitude Error Threshold for
MINERR
Vpp(PSIN) − Vpp(NSIN)
1.1
2.8
Vpp
206
Vae()hi
Amplitude Error Threshold for
MAXERR
Vpp(PSIN) − Vpp(NSIN)
4.9
5.8
Vpp
4.8
Vpp
Bandgap Reference
401
Vbg
Bandgap Reference Voltage
402
403
Vref
Reference Voltage
Iibm
Bias Current
CIBM = 0x0
CIBM = 0xF
Bias Current adjusted
1.18
1.25
1.32
V
45
50
55
%VPA
-100
-200
-180
µA
µA
µA
404
VPDon
Turn-on Threshold VPD, System V(VPD) − V(VND), increasing voltage
on
3.7
4.0
4.3
V
405
VPDoff
Turn-off Threshold VPD, System V(VPD) − V(VND), decreasing voltage
reset
3
3.5
3.8
V
406
VPDhys
Hysteresis System on/reset
0.3
407
Vosr
Reference voltage offset compensation
480
500
525
mV
-370
-220
V
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 7/28
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Clock Generation
501
f()sys
System Clock
Bias Current adjusted
0.85
1.0
1.2
MHz
502
f()sdc
Sinus/Digital-Converter Clock
Bias Current adjusted
14
16
18
MHz
-0.35
0.35
Deg
-10
10
%
Sin/Digital Converter
602
AAabs
Absolute Angular Accuracy
Vpp() = 4 V, adjusted
603
AArel
Relative Angular Accuracy
with reference to one output periode at A, B, at
Resolution 1024, see Fig. 21
604
f()ab
Output frequency at A, B
CFGMTB = ’0’
CFGMTB = ’1’
605
REScom
Resolution of Commutation Converter
606
AAabs
Absolute Angular Accuracy of
Commutation Converter
0.5
2.0
MHz
MHz
1.875
Deg
-0.5
0.5
Deg
0.4
V
Serial Interface, Digital Outputs MA, SLO, SLI
701
Vs(SLO)hi Saturation Voltage High
V(SLO) = V(VPD) − V(),
I(SLO) = 4 mA
702
Vs(SLO)lo Saturation Voltage Low
I(SLO) = 4 mA to VND
703
Isc(SLO)hi Short-Circuit Current High
V(SLO) = V(VND), 25°C
704
Isc(SLO)lo Short-Circuit Current Low
V(SLO) = V(VPD), 25°C
705
tr(SLO)
Rise Time SLO
706
tf(SLO)
Fall Time SLO
707
Vt()hi
Threshold Voltage High: MA, SLI
708
Vt()lo
Threshold Voltage Low: MA, SLI
0.8
709
Vt()hys
Threshold Hysteresis: MA, SLI
150
710
Ipd(SLI)
Pull-up Current: MA, SLI
711
Ipu(MA)
712
f()MA
0.4
-90
-50
80
mA
CL = 50 pF
60
ns
CL = 50 pF
60
ns
2
V
V() = 0...VPD − 1 V
50
V
mA
V
250
mV
6
30
60
-60
-30
-6
µA
µA
10
MHz
2
V
Zapping and Test
801
Vt()hi
Threshold Voltage High VZAP,
PTE
with reference to VND
802
Vt()lo
Threshold Voltage Low VZAP,
PTE
with reference to VND
0.8
803
Vt()hys
Hysteresis
Vt()hys = Vt()hi − Vt()lo
100
804
Vt()nozap
Threshold Voltage Nozap VZAP
V() = V(VZAP) − V(VPD), V(VPD) = 5 V ±5 %,
at chip temperature 27 °C
0.8
805
Vt()zap
Threshold Voltage Zap VZAP
V() = V(VZAP) − V(VPD), V(VPD) = 5 V ±5 %,
at chip temperature 27 °C
806
V()zap
Zapping voltage
PROG = ’1’
807
V()zpd
Diode voltage, zapped
???
808
V()uzpd
Diode voltage, unzapped
???
809
Rpd()VZAP Pull-Down Resistor at VZAP
6.9
V
250
mV
V
7.0
1.2
V
7.1
V
2
V
3
V
30
55
kΩ
2
V
0.4
V
NERR Output
901
Vt()hi
Input Threshold Voltage High
with reference to VND
902
Vs()lo
Saturation Voltage Low
I() = 4 mA , with reference to VND
903
Vt()lo
Input Threshold Voltage Low
with reference to VND
0.8
904
Vt()hys
Input Hysteresis
Vt()hys = Vt()hi − Vt()lo
150
250
905
Ipu(NERR) Pull-up Current
V(NERR) = 0...VPD − 1 V
-750
-300
-80
µA
906
Isc()lo
Short circuit current NERR
V(NERR) = V(VPD), 25°C
50
80
mA
907
tf(NERR)
Decay time NERR
CL = 50 pF
60
ns
V
mV
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 8/28
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, Tj = -40...125 °C, IBM adjusted to 200 µA , unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Line Driver Outputs
P01 Vs()hi
Saturation Voltage hi
Typ.
Max.
Vs() = VPD − V();
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
200
700
700
400
mV
mV
mV
mV
200
700
700
400
mV
mV
mV
mV
P02
Vs()lo
Saturation Voltage lo
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
P03
Isc()hi
Short-Circuit Current hi
V() = 0 V;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
-12
-125
-125
-60
-4
-50
-50
-20
mA
mA
mA
mA
V() = VPD;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
4
50
50
20
12
125
125
60
mA
mA
mA
mA
P04
P05
P06
P07
Isc()lo
Short-Circuit Current lo
Ilk()tri
Leakage Current Tristate
TRIHL(1:0) = 11
-100
100
µA
tr()
Rise-Time lo to hi at Q
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
tf()
Fall-Time hi to lo at Q
D/A Converter And Ratiometric Output LAO
Q01 RES()
D/A Converter Resolution
Q02 Iload()
Q03 dV0()hi
Q04 dV0()lo
MODE(1:0) = 00 (range 360°)
MODE(1:0) = 01 (range 270°)
MODE(1:0) = 10 (range 180°)
MODE(1:0) = 11 (range 90°)
Permissible Output Current
Output Voltage hi, Rail-To-Rail
Output Voltage lo, Rail-To-Rail
8
-1
bit
1
mA
dV0()hi = V(VDD) - V(LAO), MODE(3) = 0;
I() = -1 mA
I() = 0 mA
170
85
mV
mV
MODE(3) = 0;
I() = 1 mA
I() = 0 mA
170
85
mV
mV
Q05 Ilk()
Leakage Current
V(LAO) = 0...VDD, PSMI = hi
-5
Q06 SR()hi
Slew Rate hi
V(LAO): 20% → 80% of range
2
5
V/µs
µA
Q07 SR()lo
Slew Rate lo
V(LAO): 80% → 20% of range
2
V/µs
Activation Index Z: ENZ
R01 Vt()hi
Threshold Voltage High ENZ
R02 Vt()lo
Threshold Voltage Low ENZ
0.8
2
R03 Vt()hys
Threshold Hysteresis ENZ
100
250
R04 Ipd(SLI)
Pull-Down Current 30 µA ENZ
6
30
V() = 1 V...V(VPD)
V
V
mV
60
µA
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 9/28
OPERATING REQUIREMENTS: Serial Interface
Operating conditions: VPA, VPD = 5 V ±10 %, Ta = -40...125 °C, IBM calibrated to 200 µA;
Logic levels referenced to VND: lo = 0...0.45 V, hi = 2.4 V...VPD
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SSI Protocol (ENSSI = 1)
I001 TMAS
Permissible Clock Period
250
2x tout
ns
I002 tMASh
Clock Signal Hi Level Duration
tout determined by CFGTOS
25
tout
ns
I003 tMASl
Clock Signal Lo Level Duration
25
tout
ns
Figure 4: I/O Interface timing with SSI protocol
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 10/28
Registers
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hall Signal Conditioning
0x00
z
0x01
z
GAING(1:0)
GAINF(5:0)
0x02
z
-
VOSS(6:0)
0x03
z
PRM
VOSC(6:0)
0x04
z
HCLH
ENAC
GCC(6:0)
DPU
-
CFGTOB
CIBM(3:0)
RS422 Driver
0x05
z
ENSSI
CFGPROT
CFGO(1:0)
TRIHL(1:0)
CFGDR(1:0)
Sine/Digital Converter
0x06
z
CFGRES(7:0)
0x07
z
CFGZPOS(7:0)
0x08
z
0x09
z
0x0A
z
0x0B
CFGHYS(1:0)
CFGDIR
CFGMTD
CFGSU
CFGPOLE
CFGAB(1:0)
CfgCOM(7:0)
-
CFGTRIG
z
-
0x0C z
-
0x0D
-
CFGZ180
CFGENZ
CFGMTD2
-
-
PROGZAP
Test settings
0x0E p
0x0F
TEST(7:0)
-
res.
res.
res.
-
ZAP diodes (read only)
0x10
..
0x1F
ZAP dioden for adresses 0x00..0x0C und 0x7D..0x7F
not used
0x20
..
0x41
’invalid adresses’
Profile identification (read only)
0x42
Profile - 0x2C
0x43
Profile - 0x0
Data length DLEN
not used
0x44
..
0x75
’invalid adress’
Status messages (read only; messages will be set back during reading)
0x76
0x77
GAIN
PROGERR
ERRSDATA
ERRAMIN
ERRAMAX
ERREXT
res.
res.
PROGOK
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 11/28
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Identification (0x78 bis 0x7B read-only)
0x78
Device ID - 0x4D (’M’)
0x79
Device ID - 0x48 (’H’)
0x7A
Revision - 0x5A (’L’)
0x7B
Revision - 0x<rev>
0x7C
-
0x7D z
CFGTOS
Manufacturer Revision - 0x00
0x7E
z
Manufacturer ID - 0x00
0x7F
z
Manufacturer ID - 0x00
y: <rev>: 00 → ’MHL200_0’/’MHL200_1’, 32 → ’MHL200_2’
z: Register value programmable by zapping
p: Register value write protected; can only be changed while V(VZAP)> Vt()hi
Table 5: Register layout
Hall signal processing . . . . . . . . . . . . . . . . . . . . Page 14
Sine/digital converter . . . . . . . . . . . . . . . . . . . . . Page 20
GAING:
GAINF:
CFGRES:
CFGZPOS:
CFGAB:
CFGPOLE:
CFGSU:
CFGMTD:
CFGDIR:
CFGHYS:
CFGCOM:
CFGENZ:
CFGZ180:
RS422 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 23
CFGTRIG:
Resolution of sine digital converter
Zero point for position
Configuration of incremental output
No. of poles for commutation signals
Behavior during start-up
Frequency at AB
Rotating direction reversal
Hysteresis sine/digital converter
Zero point for commutation
Inverting Enable Z
90° → 180° zero signal (synchronous
with B)
Tristate GAIN DAC and output
CFGDR:
TRIHL:
CFGO:
CFGPROT:
ENSSI:
Test
TEST:
PROGZAP:
Test mode
Activation of programming routine
GCC:
ENAC:
VOSS:
VOSC:
PRM:
CIBM:
DPU
HCLH
Hall signal amplification range
Hall signal amplification (1–20, log.
scale)
Amplification calibration cosine
Activation of amplitude control
Offset calibration sine
Offset calibration cosine
Energy-saving mode
Calibration of bias current
Deactivation of NERR pull-up
Activation of high Hall clock pulse
Driver property
Tristate high-side/low-side driver
Configuration of output mode
Write/read protection memory
Activation of SSI mode
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 12/28
Basic operation
The iC-MHL200 uses an array of hall sensors to detect
the local variation of the magnetic field emerging from
a magentic target. The target could be a magnetic tape
with periodic varying polarity and a pitch (NS spacing)
of 2 mm to match the iC-MHL200 sensor periode P of
4 mm. An example for linear position sensing is shown
in Figure 5.
moving magnetic target
N
B
S
N
S
4 mm
x
MH
L200
P = 4 mm
Vcos(ϕ)
Figure 5: Typical arrangement of a magnetic tape to
iC-MHL200
Vsin(ϕ)
interpolaton
A
B
From the periodic magnetic field delivered by the target, the hall sensor array generates internal sensor
signals which are then further processed and passed
to the interpolator to generate incremental position
data, as shown in Figure 6.
Figure 6: Signal generation and position data output
Position of the Hall sensors and related analog sensor signal
The magnetic sensor array is placed in a line at the
upper edge of the chip as shown in Figure 7. Each
of the four sensor location (NCOS, PSIN, PCOS and
NSIN) are equally spaced apart and are based on a
pair of Hall sensors. Each Hall sensor pair provides a
Hall output signal from the mean value of the two single sensors a pair consists of, thus representing the
magnetic field strength at the center of each pair.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 13/28
Since the field distribution repeats periodically every
4 mm, an absolute position value can be defined only
within a range of one magnetic period. Electrically, the
sensor signals are repeating every 360° for every target movement of 4 mm.
20
NCOS PSIN PCOS NSIN
SP_B
SP_C
SP_B
SP_C
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
By definition, the electrical zero position (within one period) is given by the corresponding angular zero value
φ = 0 where Vsin is zero and Vcos is at its maximum
value. The mechanical zero-position location of the
tape with respect to the iC-MHL200 is shown in Figure 8.
1
Figure 7: Position of the Hall sensors
When a magnetic target is placed on top of the iCMHL200 package, the resulting magnetic field generates corresponding HALL voltages. If a magnetic south
pole is on top of a HALL sensor pair, the resulting Hall
voltage is positive, whereas a magnetic north pole provides a negative one.
20
NCOS PSIN PCOS NSIN
SP_B
To provide accurate sensor signals, the magnetic target must consist of a periodic arrangement of north
and south poles with a pitch (spacing NS) of 2 mm.
The magnetic field distribution thus has a periodic variation of 4 mm, matching the Hall sensor array periode exactly. Usually, a magnetic tape with magnetized north-south pattern is used together with the iCMHL200.
The field distribution can be approximately described
as a sinusoidal variation of the magnetic field strength
B along the target. As mentioned before, the iCMHL200 provides analog sensor signals VSIN and
VCOS which represents the linear position of the tape
with respect to the chip. The signals are internal but
can be made externally available for test purposes
(see the description of calibration procedure).
These signals are derived from the output signal difference of the complementary sensor pairs (PSIN/NSIN
for the sine signal, PCOS/NCOS for the cosine signal)
resulting in
VSIN = VPSIN - VNSIN
and
VCOS = VPCOS - VNCOS .
SP_C
SP_B
SP_C
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
N S N
0°
1
Figure 8: Zero angular position of the magnetic target. Center of south pole is aligned to the
PCOS sensor pair
The definition of a specific moving direction can be
made by comparing the mechanical position with the
corresponding electrical angular value. To obtain increasing angular position values, the magnetic tape
has to be moved to the left (when looking on top of the
chip/package) as shown in Figure 9 where the tape has
been shifted 1 mm to the left, as compared to Figure 8.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 14/28
20
NCOS PSIN PCOS NSIN
SP_B
SP_C
SP_B
SP_C
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
SP_C
SP_B
N S N
90°
0°
1
Figure 9: Position of the magnetic target at 90° electrical position. Center of south pole is
aligned to the PSIN sensor pair
Hall Signal Processing
The iC-MH module has a signal calibration function
that can compensate for the signal and adjustment
errors. The Hall signals are amplified in two steps.
First, the range of the field strength within which the
Hall sensor is operated must be roughly selected. The
first amplifier stage can be programmed in the following ranges:
GAING(1:0)
Addr. 0x00; bit 7:6
00
5-fold
01
01
01
10-fold
15-fold
20-fold
Table 6: Range selection for Hall signal amplification
The operating range can be specified in advance in
accordance with the temperature coefficient and the
magnet distance. The integrated amplitude control can
correct the signal amplitude between 1 and 20 via another amplification factor. Should the control reach the
range limits, a different signal amplification must be selected via GAING.
GAINF(5:0)
Addr. 0x00; bit 5:0
0x00
1,000
0x01
...
0x3F
1,048
exp( ln(20)
· GAINF )
64
19,08
Table 7: Hall signal amplification
The second amplifier stage can be varied in an additional range. With the amplitude control (ENAC = ’0’)
deactivated, the amplification in the GAINF register is
used. With the amplitude control (ENAC = ’1’) activated, the GAINF register bits have no effect.
GCC(6:0)
0x00
0x01
...
Addr. 0x01; bit 6:0
1,000
1,0015
exp( ln(20)
· GCC)
2048
0x3F
0x40
...
0x7F
1,0965
0,9106
exp(− ln(20)
· (128 − GCC))
2048
0,9985
Table 8: Amplification calibration cosine
The GCC register is used to correct the sensitivity of
the sine channel in relation to the cosine channel. The
cosine amplitude can be corrected within a range of
approximately ±10%.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 15/28
ENAC
0
1
inexactly adjusted magnet, then this offset can be corrected by the VOSS and VOSC registers. The output
voltage can be shifted by ±63 mV in each case to compensate for the offset.
Addr. 0x01; bit 7
amplitude control deactivated
amplitude control active
Table 9: Activation of amplitude control
The integrated amplitude control can be activated with
the ENAC bit. In this case the differential signal amplitude is adjusted to 4 Vss and the values of GAINF
have no effect here.
PSIN−NSIN
4Vss
PCOS−NCOS
Figure 10: Definition of differential amplitude
After switch-on the amplification is increased until the
setpoint amplitude is reached. The amplification is
automatically corrected in case of a change in the
input amplitude by increasing the distance between
the magnet and the sensor, in case of a change in
the supply voltage or a temperature change. The
sine signals are therefore always converted into highresolution quadrature signals at the optimum amplitude.
VOSS(6:0)
VOSC(6:0)
Addr. 0x02; bit 6:0
Addr. 0x03; bit 6:0
0x00
0x01
...
0x3F
0x40
0x41
0 mV
1 mV
...
63 mV
0 mV
-1 mV
...
0x7F
...
-63 mV
Table 10: Offset calibration for sine and cosine
Should there be an offset in the sine or cosine signal
that, among other things, can also be caused by an
PRM
0
1
Addr. 0x03; bit 7
Energy-saving mode deactivated
Energy-saving mode active
Table 11: Energy-saving mode
In the energy-saving mode the current consumption of
the Hall sensors can be quartered. This also reduces
the maximum rotating frequency by a factor of 4.
CIBM(3:0)
0x0
...
0x8
0x9
...
0xF
Addr. 0x04; bit 3:0
-40 %
...
0%
+5 %
...
+35 %
Table 12: Calibration of bias current
In the test mode (TEST = 0x43) the internal currents
can be calibrated on Pin B. For this purpose, the current must be measured based on VNA and the CIBM
register bits must be changed until the current is calibrated to 200 µA. All internal currents are then calibrated.
HCLH
0
1
Addr. 0x04; bit 7
250 kHz
500 kHz
Table 13: Activation of high Hall clock pulse
The switching-current hall sensors can be operated at
two frequencies. At 500 kHz the sine has twice the
number of support points. This setting is of interest at
high speeds above 30,000 rpm.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 16/28
Test modes for signal calibration
For signal calibration iC-MH has several test settings
which make internal reference quantities and the amplified Hall voltages of the individual sensors accessible at external pins A, B, Z and U for measurement purposes. This enables the settings of the offset (VOSS,
VOSC), gain (GAING, GAINF) and amplitude ratio of
the cosine to the sine signal (GCC) to be directly observed on the oscilloscope.
iC-MH
PSIN
B
B
A
HPSP
B
HPSN
Z
HNSP
U
HNSN
B
B
VPSIN
VNSIN
NSIN
HALL SENSORS
Test mode can be triggered by connecting pin VZAP
to VPD and programming the TEST register (address
0x0E). The individual test modes are listed in the following table:
Output signals in test mode
Mode
TEST Pin A Pin B
Normal
0x00 A
B
Analog SIN
0x20 HPSP HPSN
Analog COS 0x21 HPCP HPCN
Analog OUT 0x22 PSIN NSIN
Analog REF 0x43 VREF IBM
Digital CLK
0xC0 CLKD
VNA
C021107-1
Test Mode: Analog SIN
Figure 11: Output signals of the sine Hall sensors in
test mode Analog SIN
Pin Z
Z
HNSP
HNCP
PCOS
VBG
Pin U
U
HNSN
HNCN
NCOS
VOSR
iC-MH
PCOS
B
B
A
HPCP
B
HPCN
Z
HNCP
U
HNCN
B
B
VPCOS
VNCOS
NCOS
Table 14: Test modes and available output signals
HALL SENSORS
VNA
C021107-2
The output voltages are provided as differential signals with an average voltage of 2.5 V. The gain is determined by register values GAING and GAINF and
should be set so that output amplitudes from the sine
and cosine signals of about 1 V are visible.
Test modes Analog SIN and Analog COS
In these test modes it is possible to measure the signals from the individual Hall sensors independent of
one another. The name of the signal is derived from
the sensor name and position. HPSP, for example,
is the (amplified) Hall voltage of sensor PSIN at the
positive signal path; similarly, HNCN is the Hall voltage
of sensor NCOS at the negative signal path. The effective Hall voltage is accrued from the differential voltage
between the positive and negative signal paths of the
respective sensor.
Test mode Analog OUT
In this test mode the sensor signals are available at
the outputs as they would be when present internally
for further processing on the interpolator. The interpolation accuracy which can be obtained is determined
by the quality of signals Vsin and Vcos and can be influenced in this particular test mode by the calibration of
the offset, gain and amplitude ratio.
Test Mode: Analog COS
Figure 12: Output signals of the cosine Hall sensors
in test mode Analog COS
iC-MH
PSIN
PCOS
B
B
NCOS
A
PSIN
B
NSIN
Z
PCOS
U
NCOS
B
B
VSIN
VCOS
NSIN
HALL SENSORS
C021107-3
VNA
Test Mode: Analog OUT
Figure 13: Differential sine and cosine signals in
test mode Analog OUT
Test mode Analog REF
In this mode various internal reference voltages are
provided. VREF is equivalent to half the supply voltage
(typically 2.5 V) and is used as a reference voltage for
iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 17/28
the Hall sensor signals. VBG is the internal bandgap
reference (1.24 V), with VOSR (0.5 V) used to generate the range of the offset settings. Bias current IBM
determines the internal current setting of the analog
circuitry. In order to compensate for variations in this
current and thus discrepancies in the characteristics
of the individual iC-MH devices (due to fluctuations in
production, for example), this can be set within a range
of -40% to +35% using register parameter CIBM. The
nominal value of 200 µA is measured as a short-circuit
current at pin B to ground.
Test mode Digital CLK
If, due to external circuitry, it is not possible to measure IBM directly, by way of an alternative clock signal
CLKD at pin A can be calibrated to a nominal 1 MHz
in this test mode via register value CIBM.
Test Mode: Analog REF
iC-MH
A
VREF
B
IBM
Z
VBG
~ 1.24 V
U
VOSR
~ 0.5 V
~ 2.5 V
~ 200 µA
C021107-4
VNA
Figure 14: Setting bias current IBM in test mode
Analog REF
Calibration procedure
The calibration procedure described in the following
applies to the optional setting of the internal analog
sine and cosine signals and the mechanical adjustment of the magnet and iC-MH in relation to one another.
BIAS SETTING
The BIAS setting compensates for possible manufacturing tolerances in the iC-MH devices. A magnetic
field does not need to be present for this setting which
can thus be made either prior to or during the assembly of magnet and iC-MH.
If the optional setup process is not used, register CIBM
should be set to an average value of 0x8 (which is
equivalent to a change of 0%). As described in the
previous section, by altering the value in register CIBM
in test mode Analog REF current IBM is set to 200 µA
or, alternatively, in test mode Digital CLK signal CLKD
is set to 1 MHz.
MECHANICAL ADJUSTMENT
iC-MH can be adjusted in relation to the magnet in test
modes Analog SIN and Analog COS, in which the Hall
signals of the individual Hall sensors can be observed
while the magnet rotates.
In test mode Analog SIN the output signals of the sine
Hall sensors which are diagonally opposite one another are visible at pins A, B, Z and U. iC-MH and the
magnet are then adjusted in such a way that differential signals VPSIN and VNSIN have the same amplitude
and a phase shift of 180°. The same applies to test
mode Analog COS, where differential signals VPCOS
and VNCOS are calibrated in the same manner.
Vsin
+2 V
α
-2 V
+2 V
Vcos
-2 V
C141107-1
Figure 15: Ideal Lissajous curve
CALIBRATION USING ANALOG SIGNALS
In test mode Analog OUT as shown in Figure ?? the
internal signals which are transmitted to the sine/digital
converter can be tapped with high impedance. With a
rotating magnet it is then possible to portray the differential signals VSIN and VCOS as an x-y graph (Lissajous curve) with the help of an oscilloscope. In an
ideal setup the sine and cosine analog values describe
a perfect circle as a Lissajous curve, as illustrated by
Figure 15.
At room temperature and with the amplitude control
switched off (ENAC = 0) a rough GAING setting is selected so that at an average fine gain of GAINF = 0x20
(a gain factor of ca. 4.5) the Hall signal amplitudes are
as close to 1 V as possible. The amplitude can then
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 18/28
be set more accurately by varying GAINF. Variations in
the gain factor, as shown in Figure 16, have no effect
on the Lissajous curve, enabling the angle information
for the interpolator to be maintained.
Vsin
VOSS
α
Vsin
GAING
GAINF
Vcos
α
C141107-3
Vcos
Figure 17: Effect of the sine offset setting
Vsin
VOSC
C141107-2
Figure 16: Effect of gain settings GAING and
GAINF
α
Deviations of the observed Lissajous curve from the
ideal circle can be corrected by varying the amplitude offset (register VOSS, VOSC) and amplitude ratio
(register GCC). Changes in these parameters are described in the following figures 17 to 19. Each of these
settings has a different effect on the interpolated angle
value. A change in the sine offset thus has a maximum
effect on the angle value at 0° and 180°, with no alterations whatsoever taking place at angles of 90° and
270°. When varying the cosine offset exactly the opposite can be achieved as these angle pairs can be set
independent of one another. Setting the cosine/sine
amplitude ratio does not change these angles (0°, 90°,
180° and 270°); however, in-between values of 45°,
135°, 225° and 315° can still be influenced by this parameter.
Vcos
C141107-4
Figure 18: Effect of the cosine offset setting
Vsin
GCC
α
Once calibration has been carried out a signal such as
the one illustrated in Figure 15 should be available.
In the final stage of the process the amplitude control
can be switched back on (ENAC =1) to enable deviations in the signal amplitude caused by variations in
the magnetic field due to changes in distance and temperature to be automatically controlled.
Vcos
C141107-5
Figure 19: Effect of the amplitude ratio
iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 19/28
CALIBRATION USING INCREMENTAL SIGNALS
If test mode cannot be used, signals can also be calibrated using the incremental signals or the values read
out serially. In order to achieve a clear relationship between the calibration parameters which have an effect
on the analog sensor signals and the digital sensor values derived from these, the position of the zero pulse
should be set to ZPOS = 0 so that the digital signal
starting point matches that of the analog signals.
At an incremental resolution of 8 edges per revolution (CFGRES = 0x1) those angle values can be displayed at which calibration parameters VOSS, VOSC
and GCC demonstrate their greatest effect. When rotating the magnet at a constant angular speed the incremental signals shown in Figure 20 are achieved,
with which the individual edges ideally succeed one
another at a temporal distance of an eighth of a cycle (a 45° angle distance). Alternatively, the angle position of the magnet can also be determined using a
reference encoder, rendering an even rotational action
unnecessary and allowing calibration to be performed
using the available set angle values .
The various possible effects of parameters VOSS,
VOSC and GCC on the flank position of incremental
signals A and B are shown in Figure 20. Ideally, the
distance of the rising edge (equivalent to angle positions of 0° and 180°) at signal A should be exactly half
a period (PER). Should the edges deviate from this in
distance, the offset of the sine channel can be adjusted
using VOSS. The same applies to the falling edges of
the A signal which should also have a distance of half
a period; deviations can be calibrated using the offset
of cosine parameter VOSC. With parameter GCC the
distance between the neighboring flanks of signals A
and B can then be adjusted to the exact value of an
eighth of a cycle (a 45° angle distance).
Figure 20: Calibration using incremental signals
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 20/28
Sine/Digital Converter
100%
40%
50%
60%
The iC-MH module integrates two separate sine/digital
converters. A high-resolution 12-bit converter for the
ABZ incremental signals can be programmed in broad
ranges of the resolution and generate quadrature signals even at the highest speed and resolution. The
converter operates for the commutation signals independently of this and can be set in the zero point separately from the quadrature converter. This enables
the commutation at other angles based on the index
track Z.
A
B
Z
Figure 21: ABZ signals and relative accuracy
CFGRES(7:0)
0x0
1
0x1
2
...
...
0x7e
127
0x7f
128
0x80
0x81
0x82
Addr. 0x06; bit 7:0
256
512
1024
Table 15: Programming interpolation factor
The resolution of the 12-bit converter can virtually be
set as desired. Any resolution can be set up to an interpolation factor of 128, i.e. 512 edges per rotation. At
higher resolutions, only the binary resolutions can be
set, i.e. 256, 512 and 1024. In the highest resolution
with an interpolation factor of 1024, 4096 edges per
rotation are generated and 4096 angular steps can be
differentiated. Even in the highest resolution, the absolute position can be calculated in real time at the maximum speed. After the resolution is changed, a module
reset is triggered internally and the absolute position is
recalculated.
CFGAB(1:0)
Addr. 0x08; bit 1:0
0x0
A and B not inverted
0x1
B inverted, A normal
0x2
A inverted, B normal
0x3
A and B inverted
Table 16: Inversion of AB signals
The incremental signals can be inverted again independently of the output drivers. As a result, other
phase angles of A and B relative to the index pulse Z
can be generated. The standard is A and B high level
for the zero point, i.e. Z is equal to high.
Figure 21 shows the position of the incremental signals around the zero point. The relative accuracy of
the edges to each other at a resolution setting of 10
bit is better than 10%. This means that, based on a
period at A or B, the edge occurs in a window between
40% and 60%.
CFGHYS(1:0)
Addr. 0x08; bit 7:6
0x0
0,17°
0x1
0,35°
0x2
0,7°
0x3
1,4°
Table 17: Programming angular hysteresis
With rotating direction reversal, an angular hysteresis
prevents multiple switching of the incremental signals
at the reversing point. The angular hysteresis corresponds to a slip which exists between the two rotating
directions. However, if a switching point is approached
from the same direction, then the edge is always generated at the same position on the output. The following figure shows the generated quadrature signals
for a resolution of 360 edges per rotation (interpolation
factor 90) and a set angular hysteresis of 1.4°.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 21/28
CFGDIR
0
1
10°
0°
Addr. 0x08; bit 5
Rotating direction CCW
Rotating direction CW
−10°
A
B
Z
Table 20: Rotating direction reversal
0°
1.4°
0°
Figure 22: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accordance with the hysteresis, the return edge is generated
at A again first. This means that all edges are shifted
by the same value in the rotating direction.
CFGZPOS(7:0)
0x0
0°
0x1
0x2
...
0xff
Addr. 0x07; bit 7:0
The rotating direction can easily be changed with
the bit CFGDIR. When the setting is CCW (counterclockwise, CFGDIR = ’0’) the resulting angular position
values will increase when rotation of the magnet is performed as shown in figure ??. To obtain increasing angular position values in the CW (clockwise) direction,
CFGDIR then has to be set to ’1’.
The internal analoge sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure
??.
CFGSU
0
1
1,4°
2,8°
360
·CFGZPOS
256
358,6°
Addr. 0x08; bit 3
ABZ output "111" during startup
AB instantly counting to actual position
Table 21: Configuration of output startup
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z-pulse once over 360°.
CFGMTD2
0
CFGMTD
0
Minimum edge spacing
500 ns
max. 500 kHz at A
0
1
1
1
0
1
125 ns
8 µs
2 µs
max. 2 MHz at A
max. 31.25 kHz at A
max. 125 kHz at A
Table 19: Minimum edge spacing
The CFGMTB register defines the time in which two
consecutive position events can be output. The default is a maximum output frequency of 500 kHz on A.
This means that at the highest resolution, speeds of
30,000 rpms can still be correctly shown. In the setting with an edge spacing of 125 ns, the edges can be
generated even at the highest revolution and the maximum speed. However, the counter connected to the
module must be able to correctly process all edges in
this case. The settings with 2 µs, and 8 µs can be used
for slower counters. It should be noted then, however,
that at higher resolutions the maximum rotation speed
is reduced.
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, first
the current position is determined. During this phase,
the quadrature outputs are constantly set to "111" in
the setting CFGSU = ’0’. In the setting CFGSU = ’1’,
edges are generated at the output until the absolute
position is reached. This enables a detection of the
absolute position with the incremental interface.
The converter for the generation of the commutation
signals can be configured for two and four-pole motors. Three rectangular signals each with a phase shift
of 120° are generated. With two-pole commutation, the
sequence repeats once per rotation. With a four-pole
setting, the commutation sequence is generated twice
per rotation.
CFGPOLE
0
1
Addr. 0x8; bit 1
2 pole commutation
4 pole commutation
Table 22: Commutation
The zero position of the commutation, i.e. the rising
edge of the track U, can be set as desired over a rotation. Here 192 possible positions are available. Values
above 0xC0 are the mirrored positions from 0x70.
iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 22/28
CFGPOLE(7:0)
Addr. 0x09; bit 7:0
0x00
0°
0x01
1,875°
...
0xBF
360
· CFGCOM
192
358,125°
Table 23: Commutation
iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 23/28
Output Drivers
Six RS422-compatible output drivers are available,
which can be configured for the incremental signals
and commutation signals. The following table on the
CFGO register bits provides an overview of the possible settings.
PSIN
PCOS
A
iC−MH
B
CFGO(1:0)
00
01
10
11
Addr. 0x07; bit 7:6
Incrementral Diff ABZ (U=NA, V=NB, W=NZ)
Incr ABZ + Comm UVW
Commutation Diff UVW (A=NU, B=NV, Z=NW)
Incr. ABZ + AB4 (U=A4, V=B4, W=0)
Z
U
V
W
Figure 23: ABZ differential incremental signals
PSIN
Table 24: Configuration of output drivers
PCOS
A
In the differential incremental mode (CFGO = ’00’, Figure 23), quadrature signals are available on the Pins
A, B and Z. The respective inverted quadrature signals are available on the pins U, V and W. As a result,
lines can be connected directly to the module. Another
configuration of the incremental signals is specified in
the section "Sine/Digital Converter".
iC−MH
B
Z
U
V
W
Figure 24: ABZ incremental / UVW commutation
signals
PSIN
PCOS
A
B
iC−MH
With CFGO = ’01’ (Figure 24) the ABZ incremental signals and the UVW commutation signals are available
on the six pins. As long as the current angular position is not yet available during the start-up phase, all
commutation signals are at the low level.
Z
U
V
W
With CFGO = ’10’, the third mode (Figure 25) is available for transferring the commutation signals via a differential line. The non-inverted signals are on the pins
U, V and W, the inverted signals on A, B and Z.
The ABZ quadrature signals with an adjustable higher
resolution and quadrature signals with one period per
rotation are available in the fourth mode (Figure 26).
Four segments can be differentiated with the pins U
and V. This information can be used for an external
period counter which counts the number of scanned
complete rotations.
Figure 25: UVW differential commutation signals
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 24/28
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital input on the same assembly. With the setting CFGDR =
’01’ the same transmission speed is available and the
driver power is sufficient for the connection of a line
over a short distance. Steep edges on the output enable a high transmission rate. A lower slew rate is offered by the setting CFGDR = ’10’, which is excellent
for longer lines in an electromagnetically sensitive environment. Use of the setting CFGDR = ’11’ is advisable at medium transmission rates with a limited driver
capability.
PSIN
PCOS
A
iC−MH
B
Z
U
V
W
Figure 26: ABZ incremental signals / period counter
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
CfgDR(1:0)
00
01
10
11
Addr. 0x07; bit 1:0
10 MHz 4 mA (default)
10 MHz 60 mA
300 kHz 60 mA
3 MHz 20 mA
TRIHL
00
01
Addr. 0x07; bit 3:2
Push Pull Output Stage
Lowside Driver
10
11
Highside Driver
Tristate
Table 26: Tristate Register
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.
Table 25: Driver property
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
Serial Interface
The serial interface is used to read out the absolute
position and to parameterize the module. For a de-
tailed description of the protocol, see separate interface specification.
MA
CDM
SLI
SLO
Ack Start CDS D11 D10
D0
nE
nW CRC5 CRC4
CRC0 Stop
Timeout
Data Range
Figure 27: Serial Interface Protocol
The sensor sends a fixed cycle-start sequence containing the Acknowledge-, Start and Control-Bit followed by the binary 12 bit sensor data. At lower resolution settings the data word contains leading zeros. The
low-active error bit nE a ’0’ indicates an error which
can be further identified by reading the status register
0x77. The following bit nW is always at ’1’ state. Following the 6 CRC bits the data of the next sensors, if
available, are presented. Otherwise, the master stops
generating clock pulse on the MA line an the sensor
runs into a timeout, indicating the end of communication.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 25/28
Serial Interface
Protocol
Cycle start sequence
Lenght of sensor data
CRC Polynom
CRC Mode
Multi Cycle Data
Mode C
max. Data Rate
10 MHz
Ack/Start/CDS
12 Bit + ERR + WARN
0b1000011
inverted
not available
again after a waiting time of approximately 1 ms. If the
integrated pull-up resistor is deactivated with DPU =
’1’, then an external resistor must be provided. With
DPU = ’0’ it brings the pin up to the high level again.
DPU
0
1
Addr. 0x04; bit 6
Pull-up activated
Pull-up deactive
Table 27: Interface Protocol
Table 29: Activation of NERR pull-up
ENSSI
0
1
Addr. 0x05; bit 7
Extended SSI-Mode
SSI-Mode
Table 28: Activation of SSI mode
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. However, in the SSI
mode it is not possible to vary the parameter set. The
data is transmitted as reduced Gray code, e.g. after
converting into binary code, the data range is symmetrical to the center of the number string. For example,
with a set resolution of 360 data values between 76
and 435 are transmitted.
Figure 28: SSI protocol, data GRAY-coded
The register range 0x00 to 0x0F is equivalent to the
settings with which the IC can be parameterized. The
settings directly affect the corresponding switching
parts. It is important to note that test register 0x0E can
only be written to when pin VZAP is connected to VPD.
When VPD > 6 V, write access to the test register is ignored. Register 0x0F can be configured at potentials
V(VZAP) > Vt(VZAP)hi.
The range 0x10 to 0x1F is read-only and reflects the
contents of the integrated zapping diodes. Following
programming the data can be verified via these addresses. After the supply voltage is connected, the
contents of the zapping diodes are copied to the RAM
area 0x00 to 0x0F. Then the settings can be overwritten via the serial interface. Overwriting is not possible
if the CFGPROT bit is set.
Errors in the module are signaled via the error message output NERR. This open-drain output signals an
error if the output is pulled against VND. If the error condition no longer exists, then the pin is released
With the profile ID, the data format can be requested
for the following sensor data cycles in the module. A
read operation at address 0x42 results in 0x2C, with is
the equivalent to 12-bit single-cycle data. The register
0x43 which follows now contain the data length DLEN
of the transmitted sensor data in accordance with the
set resolution. The sensor data are transmitted rightjustified and filled with preceding zeros if necessary.
The following table shows the data length according to
the resolution.
DLEN
2
3
Addr. 0x43; bit 3:0
CFGRES = ’00000000’, 4
CFGRES = ’00000001’, 8
4
5
6
7
8
9
CFGRES = ’0000001x’, 12 to 16
CFGRES = ’000001xx’, 20 to 32
CFGRES = ’00001xxx’, 36 to 64
CFGRES = ’0001xxxx’, 68 to 128
CFGRES = ’001xxxxx’, 132 to 256
CFGRES = ’01xxxxxx’, 260 to 512
10
11
12
CFGRES = ’10000000’, 1024
CFGRES = ’10000001’, 2048
CFGRES = ’10000010’, 4096
Table 30: Data length
The status register provides information on the status
of the module. There are 5 different errors that can
be signaled. Following unsuccessful programming of
the zapping diodes, the bit PROGERR is set. If an
attempt is made to read the current position via the serial interface during the start-up phase, an error is signaled with ERRSDATA, as the actual position is not yet
known. The ERRAMAX bit is output to signal that the
amplitude is too high, while the ERRAMIN bit signals
an amplitude which is too low, caused, for example, by
too great a distance to the magnet. If the NERR pin
is pulled against VND outside the module, this error is
also signaled via the serial interface. The ERREXT bit
is then equal to ’1’. The error bits are reset again after
the status register is read out at the address 0x77. The
error bit in the data word is then also read in the next
cycle as ’0’.
preliminary
iC-MHL200
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 26/28
CFGTOS
0
1
CFGTOB
0
0
Timeout
16 µs
2 µs
x
1
2 µs
to the default value 16 µs again following a reset. The
timeout can be permanently programmed for faster
data transmission with the CFGTOB register via a zapping diode. Resetting to slower data transmission is
then not possible.
Table 31: Timeout for sensor data
The timeout can be programmed to a shorter value
with the CFGTOS bit. However, this setting is reset
The registers 0x7D to 0x7F are reserved for the manufacturer and can be provided with an ID so that the
manufacturer can identify its modules
OTP Programming
CFGPROT
0
1
Addr. 0x05; bit 6
no protection
write/read protection
Table 32: Write/read protection of configuration
end of the programming line as close to the connector as possible (see figure 29). During programming
up to 100 mA flow from pin VZAP to pin VNA, making
it necessary to ensure proper PCB layout to minimize
voltage drops.
With CFGPROT = ’0’, the registers at the addresses
0x00 to 0x0F and 0x78 to 0x7F are readable and writeable. The addresses 0x10 to 0x1F and 0x77 are readonly. With CFGPROT = ’1’, all registers except the addresses 0x7B and 0x7C are write-protected; the addresses 0x77 to 0x7F are readable, while all others
are read-protected.
100 nF
100 nF
SET CONFIGURATION
SET CIBM = 0x0
START HW ZAP ALGORITHM
SET ADR 0x0F = 0x01
VPD = VPA = 5.0V
Programming
Board
+ 5V
VPD VPA
iC-MHL200
START
VZAP
MA
SLI
SLO
+ 7V
Serial
Interface
100 nF
VND VNA
FALSE
10 µF
0V
VERIFY
VPD = VPA = 5.5V
CIBM = 0x0
TRUE
FALSE
SET CIBM
VERIFY
VPD = VPA = 4.0V
CIBM = 0xF
TRUE
Figure 29: Programming within system
CIBM programmed?
FALSE
TRUE
An internal programming algorithm for the ZAP diodes
is started by setting the bit PROGZAP. This process
can only be successful, if the voltage difference between VZAP and VNA pin is within the specified value
and the test register is set to TEST = 0x00. Following
programming, the PROGZAP bit is reset automatically.
In the process, the bit PROGOK is set in the status register (address 0x77) when programming is successful,
and the bit PROGERR, if it is not.
A 100 nF ceramic block capacitor must be placed on
board directly between VZAP and VNA pins of the iCMH. Also a 10 µF capacitor must be present at the
STOP
Figure 30: Programming algorithm
Once the device has been successfully calibrated the
configuration can be written into the device. To this
end the contents of the RAM bits are transferred to
the ROM zapping structure. CIBM is first set to 0x0
at address 0x04 and the hardware programming algorithm started by bit PROGZAP. Programming should
be monitored with the threshold settings for CIBM and
iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 27/28
VPD, VPA voltage by reading out the ZAP structures
via the serial interface. If programming is not successful, the hardware programming algorithm can again be
initiated. In the second stage of the procedure the bias
current is programmed in the CIBM register. Here, all
RAM bits are set to 0x00; register CIBM is configured
with the calculated calibration value and the programming algorithm started. Programming is successful
when all bits have been configured.
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relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
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iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
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iC-MHL200
preliminary
12-BIT LINEAR / ROTARY POSITION HALL ENCODER
Rev A1, Page 28/28
ORDERING INFORMATION
Type
Package
Order Designation
iC-MHL200
TSSOP20
iC-MHL200 TSSOP20
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners