ICHAUS IC

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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 1/25
FEATURES
APPLICATIONS
♦
♦
♦
♦
♦
♦ Digital angular sensor
technology, 0–360°
♦ Incremental angular encoder
♦ Absolute angular encoder
♦ Brushless motors
♦ Motor feedback
♦ Rotational speed control
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Real-time system for rotation speed up to 120,000 rpm
Integrated Hall sensors with automatic offset compensation
4x sensor arrangement for fault-tolerant adjustment
Amplitude control for optimum operating point
Interpolator with 4096 angular increments/resolution better
than 0.1°
Programmable resolution, hysteresis, edge spacing, zero
position and rotating direction
Incremental output of sensor position up to 8 MHz edge rate
RS422-compatible AB encoder signals with index Z
UVW commutation signals for eight pole EC motor applications
Serial interface for data output and configuration
SSI-compatible output mode
Integrated ZAP diodes for module setup and OEM data,
programmable via serial interface
Signal error (e.g. magnet loss) can also be read out via serial
interface
Analogue sine and cosine differential signals
Extended temperature range from -40 to +125 °C
PACKAGES
QFN28 5 x 5 mm²
BLOCK DIAGRAM
Sine / cosine outputs
+ 5V
+ 5V
PCOUT NCOUT
VPA
B
Test
S
PSOUT NSOUT
TEST
A
A
B
B
Z
Z
B
PTE
B
Binary interpolation factors
1, 2, 4, ... 256, 512, 1024
VPD
N
B
HALL SENSOR
CONVERSION
LOGIC
SINE-TO-DIG
RS422
2
SIN + COS
Loss of magnet,
frequency error
Two, four and eight pole
commutating signals
0°
U
2
U
120°
V
NERR
AMPLITUDE
CORRECTION
ERROR MONITOR
AMPL CONTROL
PHASE
SHIFT
SINE-TO-COM
V
240°
W
W
INCR INTERFACE
Analog output signals
0x00
MA
SLO
Data,
Programming
iC-MH8
0x0F
0x10
PSOUT
NSOUT
16 Byte ZROM
0.5 Vpp
0x1F
SLI
SERIAL
INTERFACE
0x77
0x7F
RAM
VNA1
ZAP CONTROL
BIAS/VREF
VND
VZAP
Programming
Voltage
PCOUT
NCOUT
ZAPROM
0°
VNA2
180°
360°
C061010-2
Angular position a
Copyright © 2011 iC-Haus
http://www.ichaus.com
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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 2/25
DESCRIPTION
The iC-MH8 12-bit angular encoder is a position sensor with integrated Hall sensors for scanning a permanent magnet. The signal conditioning unit generates constant-amplitude sine and cosine voltages
that can be used for angle calculation. The resolution can be programmed up to a maximum of 4,096
angular increments per rotation.
The integrated serial interface also enables the position data to be read out to several networked sensors.
And the integrated memory can be written embedded
in the data protocol.
The incremental interface with the pins A, B and Z
supplies quadrature signals with an edge rate of up
to 8 MHz. Interpolation can be carried out with maximum resolution at a speed of 120,000 rpm. The position of the index pulse Z is adjustable.
The commutation interface with the signals U, V and
W provides 120° phase-shifted signals for block commutation of eight pole EC motors. The zero point of
the commutation signals is freely definable in increments of 5.625° over 360°.
Sine and cosine signals are externally availabe to facilitate adjustement.
The RS422-compatible outputs of the incremental
interface and the commutation interface are programmable in the output current and the slew rate.
In conjunction with a rotating permanent magnet, the
iC-MH8 module forms a one-chip encoder. The entire configuration can be stored in the internal parameter ROM with zapping diodes. The integrated
programming algorithm assumes writing of the ROM
structure.
PACKAGES QFN28 5 x5 mm² to JEDEC MO-220-VHHD-1
PIN CONFIGURATION QFN28 5 x 5mm²
PSOUT NSOUT
nc
nc
28
27
26
25
nc
nc
W
24
23
22
PTE
1
21
V
NERR
2
20
U
VPA
3
19
VPD
MH8
VNA1
4
18
VND
SLI
5
17
Z
MA
6
16
B
SLO
7
15
A
8
9
nc
nc
10
11
12
13
14
C061010-1
nc
PCOUT VZAP
VNA2
NCOUT
PIN FUNCTIONS
No. Name Function
1 PTE Test Enable Pin
2 NERR Error output(active low)
PIN FUNCTIONS
No. Name Function
3 VPA
+5 V Supply Voltage (analog)
4 VNA1
Ground (analog)
5 SLI
Serial Interface, Data Input
6 MA
Serial Interface, Clock Input
7 SLO
Serial Interface, Data Output
8,9 nc
not connected
10 PCOUT Positive Cosine Output
11 NCOUT Negative Cosine Output
12 VZAP
Zener Zapping Programming Voltage
13 VNA2
Ground (analog)
14 nc
not connected
15 A
Incremental A (+NU)
16 B
Incremental B (+NV)
17 Z
Index Z (+NW)
18 VND
Ground (digital)
19 VPD
+5 V Supply Voltage (digital)
20 U
Commutation U (+NA)
21 V
Commutation V (+NB)
22 W
Commutation W (+NZ)
23,24 nc
not connected
25 NSOUT Negative Sine Output
26 PSOUT Positive Sine Output
27,28 nc
not connected
TP
Thermal-Pad
The Thermal Pad is to be connected to common ground (VNA1, VNA2, VND) on the PCB. Orientation of the
logo ( MH8 CODE ...) is subject to alteration.
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 3/25
PACKAGE DIMENSIONS
RECOMMENDED PCB-FOOTPRINT
4.70
3.15
15
R0.
0.50
0.30
BOTTOM
5
3.15
0.50
0.25
0.55
5
3.15
TOP
0.90
0.90
3.15
4.70
SIDE
drb_qfn28-2_pack_1, 10:1
All dimensions given in mm.
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 4/25
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Supply voltages at VPA, VPD
-0.3
6
V
G002 V(VZAP)
Zapping voltage
-0.3
8
V
G003 V()
Voltages at A, B, Z, U, V, W, MA, SLO,
SLI, NERR, PTE
-0.3
6
V
G004 I()
Current in VPA
-10
20
mA
G005 I()
Current in VPD
-20
200
mA
G006 I()
Current in A, B, Z, U, V, W
-100
100
mA
G007 I()
Current in MA, SLO, SLI, NERR, PTE
-10
10
mA
G008 Vd()
ESD-voltage, all pins
2
kV
G009 Ts
Storage temperature
-40
150
°C
G010 Tj
Chip temperature
-40
135
°C
HBM 100 pF discharged over 1.5 kΩ
THERMAL DATA
Operating conditions: VPA, VPD = 5 V ±10 %
Item
No.
T01
T02
Symbol
Parameter
Conditions
Unit
Min.
Ta
Rthja
Operating Ambient Temperature Range
Thermal Resistance Chip to Ambient
Typ.
-40
surface mounted to PCB, thermal pad linked
to cooling area of approx. 2 cm²
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
Max.
125
40
°C
K/W
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 5/25
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
General
001
V(VPA),
V(VPD)
Permissible Supply Voltage
4.5
5.5
V
002
I(VPA)
Supply Current in VPA
003
I(VPD)
Supply Current in VPD
PRM = ’0’, without Load
3
12
mA
5
27
004
I(VPD)
Supply Current in VPD
PRM = ’1’, without Load
mA
2
20
005
Vc()hi
Clamp Voltage hi at MA, SLI,
SLO, PTE, NERR
mA
Vc()hi = V() − VPD, I() = 1 mA
0.4
1.5
V
006
Vc()lo
Clamp Voltage lo at MA, SLI,
SLO, PTE, NERR
I() = -1 mA
-1.5
-0.3
V
20
100
kA/m
2
120 000
kHz
rpm
Hall Sensors and Signal Conditioning
101
Hext
Operating Magnetic Field
Strength
at surface of chip
102
fmag
Operating Magnetic Field
Frequency
Rotating Speed of Magnet
103
dsens
Diameter of Hall Sensor Array
104
xdis
Max. Magnet Axis Displacement
vs. Center of Hall Sensor Array
105
xpac
Chip Placement Error vs. Package
with QFN28
-0.2
106
φpac
Chip Tilt Error vs. Package
with QFN28
-3
107
hpac
Sensor-to-Package-Surface Dis- with QFN28
tance
108
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x7F
109
Vos
Trimming range of output offset
voltage
VOSS or VOSC = 0x3F
110
Vopt
Optimal differential output voltage Vopt = Vpp(PSIN) − Vpp(NSIN), ENAC = ’0’,
see Fig. 6
111
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x3F
112
Vratio
Amplitude Ratio
Vratio = Vpp(PSIN) / Vpp(PCOS), GCC = 0x40
2
mm
0.2
mm
0.2
mm
+3
Deg
0.4
mm
-55
55
mV
mV
4
Vpp
1.09
0.92
Signal Level Control
201
Vpp
Differential Peak-to-Peak Output Vpp = Vpk(Px) − Vpk(Nx), ENAC = ’1’, see Fig.
Amplitude
6
202
ton
Controller Settling Time
300
µs
203
Vt()lo
MINERR Amplitude Error Thresh- see 201
old
1.0
2.8
Vpp
204
Vt()hi
MAXERR Amplitude Error
Threshold
4.8
5.8
Vpp
3.2
4.8
to ±10% of final amplitude
see 201
Vpp
Bandgap Reference
401
Vbg
Bandgap Reference Voltage
402
403
Vref
Reference Voltage
Iibm
Bias Current
CIBM = 0x0
CIBM = 0xF
Bias Current adjusted
1.18
1.25
1.32
V
45
50
55
%VPA
-100
-200
-180
µA
µA
µA
404
VPDon
Turn-on Threshold VPD, System V(VPD) − V(VND), increasing voltage
on
3.65
4.0
4.3
V
405
VPDoff
Turn-off Threshold VPD, System V(VPD) − V(VND), decreasing voltage
reset
3
3.5
3.8
V
406
VPDhys
Hysteresis System on/reset
-370
-220
0.3
V
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 6/25
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
407
Symbol
Vosr
Parameter
Conditions
Reference voltage offset compensation
Unit
Min.
Typ.
Max.
475
500
525
mV
Clock Generation
501
f()sys
System Clock
Bias Current adjusted
0.85
1.0
1.2
MHz
502
f()sdc
Sinus/Digital-Converter Clock
Bias Current adjusted
13.5
16
18
MHz
Sin/Digital Converter
601
RESsdc
Sinus/Digital-Converter Resolution
12
602
603
AAabs
Absolute Angular Accuracy
Vpp() = 4 V, adjusted
AArel
Relative Angular Accuracy
with reference to an output periode at A, B.
CFGRES=0x2, ENF=1, PRM=0, HCLH=1,
GAING=0x0, Vpp(SIN/COS) = 4 Vpp.
see Fig. 17
± 10
%
604
f()ab
Output frequency at A, B
CFGMTD = 0x0, CFGRES=0x0
CFGMTD = 0x7, CFGRES=0x0
2.0
0.25
MHz
MHz
-0.35
Bit
0.35
Deg
Serial Interface, Digital Outputs MA, SLO, SLI
701
Vs(SLO)hi Saturation Voltage High
V(SLO) = V(VPD) − V(),
I(SLO) = 4 mA
702
Vs(SLO)lo Saturation Voltage Low
I(SLO) = 4 mA to VND
703
Isc(SLO)hi Short-Circuit Current High
V(SLO) = V(VND), 25°C
704
Isc(SLO)lo Short-Circuit Current Low
V(SLO) = V(VPD), 25°C
80
mA
705
tr(SLO)
Rise Time SLO
CL = 50 pF
60
ns
706
tf(SLO)
Fall Time SLO
CL = 50 pF
60
ns
707
Vt()hi
Threshold Voltage High: MA, SLI
2
V
708
Vt()lo
Threshold Voltage Low: MA, SLI
0.8
709
Vt()hys
Threshold Hysteresis: MA, SLI
140
710
Ipd()
Pull-Down Current: MA, SLI
711
Ipu(MA)
712
f(MA)
V() = 0...VPD − 1 V
0.4
0.4
-90
-50
50
V
V
mA
V
250
mV
6
30
60
-60
-30
-6
µA
µA
10
MHz
2
V
Zapping and Test
801
Vt()hi
Threshold Voltage High VZAP,
PTE
with reference to VND
802
Vt()lo
Threshold Voltage Low VZAP,
PTE
with reference to VND
0.8
803
Vt()hys
Hysteresis
Vt()hys = Vt()hi − Vt()lo
140
804
Vt()nozap
Threshold Voltage Nozap VZAP
V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,
at chip temperature 27 °C
0.7
805
Vt()zap
Threshold Voltage Zap VZAP
V() = V(VZAP) − V(VPA), V(VPA) = 5 V ±5 %,
at chip temperature 27 °C
806
V()zap
Zapping voltage
PROG = ’1’
807
V()zpd
Diode voltage, zapped
808
V()uzpd
Diode voltage, unzapped
809
Rpd()VZAP Pull-Down Resistor at VZAP
6.9
V
250
mV
V
7.0
1.2
V
7.1
V
2
V
55
kΩ
2
V
0.4
V
3
V
30
NERR Output
901
Vt()hi
Input Threshold Voltage High
with reference to VND
902
Vs()lo
Saturation Voltage Low
I() = 4 mA , with reference to VND
903
Vt()lo
Input Threshold Voltage Low
with reference to VND
904
Vt()hys
Input Hysteresis
Vt()hys = Vt()hi − Vt()lo
140
250
905
Ipu()
Pull-up Current Source
V(NERR) = 0...VPD − 1 V
-800
-300
-80
µA
906
Isc()lo
Short circuit current Lo
V(NERR) = V(VPD), Tj = 25°C
50
80
mA
907
tf()hilo
Decay time
CL = 50 pF
60
ns
0.8
V
mV
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 7/25
ELECTRICAL CHARACTERISTICS
Operating conditions:
VPA, VPD = 5 V ±10 %, VNA=VND, Tj = -40...125 °C, IBM adjusted to 200 µA , 4 mm NdFeB magnet, unless otherwise noted
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Digital Line Driver Outputs
P01 Vs()hi
Saturation Voltage hi
Typ.
Max.
Vs() = VPD − V();
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
200
700
700
400
mV
mV
mV
mV
200
700
700
400
mV
mV
mV
mV
P02
Vs()lo
Saturation Voltage lo
CfgDR(1:0) = 00, I() = -4 mA
CfgDR(1:0) = 01, I() = -50 mA
CfgDR(1:0) = 10, I() = -50 mA
CfgDR(1:0) = 11, I() = -20 mA
P03
Isc()hi
Short-Circuit Current hi
V() = 0 V;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
-12
-125
-125
-60
-4
-50
-50
-20
mA
mA
mA
mA
V() = VPD;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
4
50
50
20
12
125
125
60
mA
mA
mA
mA
P04
P05
P06
P07
Isc()lo
Short-Circuit Current lo
Ilk()tri
Leakage Current Tristate
TRIHL(1:0) = 11
-100
100
µA
tr()
Rise-Time lo to hi at Q
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
RL = 100 Ω to VND;
CfgDR(1:0) = 00
CfgDR(1:0) = 01
CfgDR(1:0) = 10
CfgDR(1:0) = 11
5
5
50
5
20
20
350
40
ns
ns
ns
ns
Rl = 50 Ω vs. VPD / 2, see Fig.
200
300
mV
tf()
Fall-Time hi to lo at Q
Analog Outputs PSOUT, NSOUT, PCOUT, NCOUT
Q01 Vpk()
Max. Output Signal Amplitude
Q02 Vos()
Output Offset Voltage
Q03 fc()
Output Cut-off Frequency
Cl = 250 pF
10
Q04 Isc()hi,lo
Output Short-circuit Current
pin shorten to VPD or VND
10
±200
µV
kHz
50
mA
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 8/25
OPERATING REQUIREMENTS: Serial Interface
Operating conditions: VPA, VPD = 5 V ±10 %, Ta = -40...125 °C, IBM calibrated to 200 µA;
Logic levels referenced to VND: lo = 0...0.45 V, hi = 2.4 V...VPD
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SSI Protocol (ENSSI = 1)
I001 TMAS
Permissible Clock Period
250
2x tout
ns
I002 tMASh
Clock Signal Hi Level Duration
tout determined by CFGTOS
25
tout
ns
I003 tMASl
Clock Signal Lo Level Duration
25
tout
ns
Figure 1: I/O Interface timing with SSI protocol
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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 9/25
Registers
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hall Signal Conditioning
0x00
z
0x01
z
GAING(1:0)
GAINF(5:0)
0x02
z
1
VOSS(6:0)
0x03
z
PRM
VOSC(6:0)
0x04
z
HCLH
ENAC
GCC(6:0)
DPU
DAO
CFGTOB
CIBM(3:0)
RS422 Driver
0x05
z
ENSSI
CFGPROT
CFGO(1:0)
TRIHL(1:0)
CFGDR(1:0)
Sine/Digital Converter
0x06
z
0x07
z
ENF
CFGMTD(2:0)
CFGRES(3:0)
0x08
z
0x09
z
CfgCOM(7:0)
0x0A
z
-
0x0B
CFGZPOS(7:0)
CFGHYS(1:0)
CFGDIR
CFGSU
CFGPOLE(1:0)
z
-
0x0C z
-
0x0D
-
CFGAB(1:0)
Test settings
0x0E p
0x0F
TEST(7:0)
ENHC
res.
res.
res.
res.
res.
res.
PROGZAP
ZAP diodes (read only)
0x10
..
0x1F
ZAP diodes for addresses 0x00..0x0C and 0x7D..0x7F
not used
0x20
..
0x41
’invalid adresses’
Profile identification (read only)
0x42
Profile - 0x2C
0x43
Profile - 0x0
Data length DLEN
not used
0x44
..
0x75
’invalid adress’
Status messages (read only; messages will be set back during reading)
0x76
0x77
GAIN
PROGERR
ERRSDATA
ERRAMIN
ERRAMAX
ERREXT
res.
res.
PROGOK
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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 10/25
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Identification (0x78 bis 0x7B read-only)
0x78
Device ID - 0x4D (’M’)
0x79
Device ID - 0x48 (’H’)
0x7A
Revision - 0x38 (’8’)
0x7B
Revision - 0x00 (”)
0x7C
-
0x7D z
CFGTOS
Manufacturer Revision - 0x00
0x7E
z
Manufacturer ID - 0x00
0x7F
z
Manufacturer ID - 0x00
z: Register value programmable by zapping
p: Register value write protected; can only be changed while V(VZAP)> Vt()hi
Table 5: Register layout
Hall signal processing . . . . . . . . . . . . . . . . . . . . Page 12
Sine/digital converter . . . . . . . . . . . . . . . . . . . . . Page 18
GAING:
GAINF:
CFGRES:
CFGZPOS:
CFGAB:
CFGPOLE:
CFGSU:
CFGMTD:
CFGDIR:
CFGHYS:
CFGCOM:
GCC:
ENAC:
VOSS:
VOSC:
PRM:
CIBM:
DPU
HCLH
ENF
DAO:
Hall signal amplification range
Hall signal amplification (1–20, log.
scale)
Amplification calibration cosine
Activation of amplitude control
Offset calibration sine
Offset calibration cosine
Energy-saving mode
Calibration of bias current
Deactivation of NERR pull-up
Activation of high Hall clock pulse
Activation of noise filter
Disable Analog Outputs
RS422 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21
CFGDR:
TRIHL:
CFGO:
CFGPROT:
ENSSI:
Driver property
Tristate high-side/low-side driver
Configuration of output mode
Write/read protection memory
Activation of SSI mode
Test
TEST:
ENHC:
PROGZAP:
Resolution of sine digital converter
Zero point for position
Configuration of incremental output
No. of poles for commutation signals
Behavior during start-up
Frequency at AB
Rotating direction reversal
Hysteresis sine/digital converter
Zero point for commutation
Test mode
Enable High Current during ZAPDiode Read (iC-MH82 and later)
Activation of programming routine
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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 11/25
Sensor principle
S
In conjunction with a rotating permanent magnet, the
iC-MH8 module can be used to create a complete encoder system. A diametrically magnetized, cylindrical permanent magnet made of neodymium iron boron
(NdFeB) or samarium cobalt (SmCo) generates optimum sensor signals. The diameter of the magnet
should be in the range of 3 to 6 mm.
N
z
y
+Bz
B
x
-Bz
C151107-1
Figure 2: Sensor principle
The iC-MH8 has four Hall sensors adapted for angle
determination and to convert the magnetic field into
a measurable Hall voltage. Only the z-component of
the magnetic field is evaluated, whereby the field lines
pass through two opposing Hall sensors in the opposite direction. Figure 2 shows an example of field vectors. The arrangement of the Hall sensors is selected
so that the mounting of the magnets relative to iC-MH8
is extremely tolerant. Two Hall sensors combined provide a differential Hall signal. When the magnet is rotated around the longitudinal axis, sine and cosine output voltages are produced which can be used to determine angles.
Position of the Hall sensors and the analog sensor signal
The Hall sensors are placed in the center of the QFN28
package at 90° to one another and arranged in a circle
with a diameter of 2 mm as shown in Figure 3.
Pin 1 Mark
28
27
26
25
24
23
22
21
1
2
PSIN
PCOS
19
4
18
5
17
NCOS
NSIN
7
(top view)
20
3
6
In order to calculate the angle position of a diametrically polarized magnet placed above the device a difference in signal is formed between opposite pairs of
Hall sensors, resulting in the sine being VSIN = VPSIN VNSIN and the cosine VCOS = VPCOS - VNCOS . The zero
angle position of the magnet is marked by the resulting
cosine voltage value being at a maximum and the sine
voltage value at zero.
This is the case when the south pole of the magnet is
exactly above the PCOS sensor and the north pole is
above sensor NCOS, as shown in Figure 4. Sensors
PSIN and NSIN are placed along the pole boundary so
that neither generate a Hall signal.
16
15
8
9
10
11
12
13
14
C040907-2
Figure 3: Position of the Hall sensors
When a magnetic south pole comes close to the surface of the package the resulting magnetic field has a
positive component in the +z direction (i.e. from the top
of the package) and the individual Hall sensors each
generate their own positive signal voltage.
When the magnet is rotated counterclockwise the
poles then also cover the PSIN and NSIN sensors, resulting in the sine and cosine signals shown in Figure
5 being produced.
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iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 12/25
28
27
26
25
24
23
22
21
1
5
17
6
16
7
8
9
11
12
13
28
22
2
20
2
27
26
25
24
23
(top view)
22
S
21
20
3
19
3
19
4
18
4
18
5
17
5
17
16
6
15
7
6
9
10
11
12
13
14
16
N
8
9
10
11
α>0
15
12
13
14
α=0
0
VSIN= VPSIN- VNSIN VCOS= VPCOS- VNCOS
+2V
15
10
23
N
18
N
19
4
24
1
8
3
25
21
7
20
S
2
26
S
28
27
1
-90°
90°
180°
270°
360°
α
-2V
14
C041007-3
C040907-1
Figure 4: Zero position of the magnet
Figure 5: Pattern of the analog sensor signals with
the angle of rotation
Hall Signal Processing
The iC-MH8 module has a signal calibration function
that can compensate for the signal and adjustment errors. The Hall signals are amplified in two steps. First,
the range of the field strength within which the Hall sensor is operated must be roughly selected. The first
amplifier stage can be programmed in the following
ranges:
GAING(1:0)
00
01
10
11
Addr. 0x00; bit 7:6
5-fold
10-fold
15-fold
20-fold
The second amplifier stage can be varied in an additional range. With the amplitude control (ENAC = ’0’)
deactivated, the amplification in the GAINF register is
used. With the amplitude control (ENAC = ’1’) activated, the GAINF register bits have no effect.
GCC(6:0)
0x00
0x01
1,000
1,0015
Addr. 0x01; bit 6:0
...
0x3F
0x40
...
0x7F
exp( ln(20)
· GCC)
2048
1,0965
0,9106
exp(− ln(20)
· (128 − GCC))
2048
0,9985
Table 6: Range selection for Hall signal amplification
Table 8: Amplification calibration cosine
The operating range can be specified in advance in
accordance with the temperature coefficient and the
magnet distance. The integrated amplitude control can
correct the signal amplitude between 1 and 20 via another amplification factor. Should the control reach the
range limits, a different signal amplification must be selected via GAING.
GAINF(5:0)
Addr. 0x00; bit 5:0
0x00
...
1,000
0x02
0x03
1,048
...
exp( ln(20)
· GAINF − 2)
64
0x3F
17,38
Table 7: Hall signal amplification
The GCC register is used to correct the sensitivity of
the sine channel in relation to the cosine channel. The
cosine amplitude can be corrected within a range of
approximately ±10%.
ENAC
0
Addr. 0x01; bit 7
amplitude control deactivated
1
amplitude control active
Table 9: Activation of amplitude control
The integrated amplitude control can be activated with
the ENAC bit. In this case the differential signal amplitude is adjusted to 4 Vss and the values of GAINF
have no effect here.
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 13/25
PSIN−NSIN
4Vss
PRM
0
1
Addr. 0x03; bit 7
Energy-saving mode deactivated
Energy-saving mode active
PCOS−NCOS
Table 11: Energy-saving mode
Figure 6: Definition of differential amplitude
After switch-on the amplification is increased until the
setpoint amplitude is reached. The amplification is
automatically corrected in case of a change in the
input amplitude by increasing the distance between
the magnet and the sensor, in case of a change in
the supply voltage or a temperature change. The
sine signals are therefore always converted into highresolution quadrature signals at the optimum amplitude.
VOSS(6:0)
VOSC(6:0)
0x00
0x01
...
0x3F
Addr. 0x02; bit 6:0
Addr. 0x03; bit 6:0
0 mV
1 mV
...
63 mV
0x40
0x41
...
0x7F
0 mV
-1 mV
...
-63 mV
Table 10: Offset calibration for sine and cosine
In the energy-saving mode the current consumption of
the Hall sensors can be quartered. This also reduces
the maximum rotating frequency by a factor of 4.
CIBM(3:0)
0x0
...
0x8
0x9
...
-40 %
...
0%
+5 %
...
Addr. 0x04; bit 3:0
0xF
+35 %
Table 12: Calibration of bias current
The bias current is factory calibrated to 200 µA. The
calibration can be verified in test mode (TEST = 0x43)
by measuring the current from Pin B to Pin VNA.
HCLH
0
1
Addr. 0x04; bit 7
250 kHz
500 kHz
Table 13: Activation of high Hall clock pulse
Should there be an offset in the sine or cosine signal
that, among other things, can also be caused by an
inexactly adjusted magnet, then this offset can be corrected by the VOSS and VOSC registers. The output
voltage can be shifted by ±63 mV in each case to compensate for the offset.
The switching-current hall sensors can be operated at
two frequencies. At 500 kHz the sine has twice the
number of support points. This setting is of interest at
high speeds above 30,000 rpm.
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 14/25
Test modes for signal calibration
For signal calibration iC-MH8 has several test settings
which make internal reference quantities and the amplified Hall voltages of the individual sensors accessible at external pins A, B, Z and U for measurement purposes. This enables the settings of the offset (VOSS,
VOSC), gain (GAING, GAINF) and amplitude ratio of
the cosine to the sine signal (GCC) to be directly observed on the oscilloscope.
iC-MH8
PSIN
B
B
A
HPSP
B
HPSN
Z
HNSP
U
HNSN
B
B
VPSIN
VNSIN
NSIN
HALL SENSORS
Test mode can be triggered by connecting pin VZAP
to VPD and programming the TEST register (address
0x0E). The individual test modes are listed in the following table:
Output signals in test mode
Mode
TEST Pin A Pin B
Normal
0x00 A
B
Analog SIN
0x20 HPSP HPSN
Analog COS 0x21 HPCP HPCN
Analog OUT 0x22 PSIN NSIN
Analog REF 0x43 VREF IBM
Digital CLK
0xC0 CLKD
VNA
C021107-1acr
Test Mode: Analog SIN
Figure 7: Output signals of the sine Hall sensors in
test mode Analog SIN
Pin Z
Z
HNSP
HNCP
PCOS
VBG
Pin U
U
HNSN
HNCN
NCOS
VOSR
iC-MH8
PCOS
B
B
A
HPCP
B
HPCN
Z
HNCP
U
HNCN
B
B
VPCOS
VNCOS
NCOS
Table 14: Test modes and available output signals
HALL SENSORS
VNA
C021107-2acr
The output voltages are provided as differential signals with an average voltage of 2.5 V. The gain is determined by register values GAING and GAINF and
should be set so that output amplitudes from the sine
and cosine signals of about 1 V are visible.
Test modes Analog SIN and Analog COS
In these test modes it is possible to measure the signals from the individual Hall sensors independent of
one another. The name of the signal is derived from
the sensor name and position. HPSP, for example,
is the (amplified) Hall voltage of sensor PSIN at the
positive signal path; similarly, HNCN is the Hall voltage
of sensor NCOS at the negative signal path. The effective Hall voltage is accrued from the differential voltage
between the positive and negative signal paths of the
respective sensor.
Test mode Analog OUT
In this test mode the sensor signals are available at
the outputs as they would be when present internally
for further processing on the interpolator. The interpolation accuracy which can be obtained is determined
by the quality of signals Vsin and Vcos and can be influenced in this particular test mode by the calibration of
the offset, gain and amplitude ratio.
Test Mode: Analog COS
Figure 8: Output signals of the cosine Hall sensors
in test mode Analog COS
iC-MH8
PSIN
PCOS
B
B
NCOS
A
PSIN
B
NSIN
Z
PCOS
U
NCOS
B
B
VSIN
VCOS
NSIN
HALL SENSORS
C021107-3acr
VNA
Test Mode: Analog OUT
Figure 9: Differential sine and cosine signals in test
mode Analog OUT
Test mode Analog REF
In this mode various internal reference voltages are
provided. VREF is equivalent to half the supply voltage
(typically 2.5 V) and is used as a reference voltage for
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12 BIT ANGULAR HALL ENCODER
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the Hall sensor signals. VBG is the internal bandgap
reference (1.24 V), with VOSR (0.5 V) used to generate the range of the offset settings. Bias current IBM
determines the internal current setting of the analog
circuitry. In order to compensate for variations in this
current and thus discrepancies in the characteristics
of the individual iC-MH8 devices (due to fluctuations in
production, for example), this can be set within a range
of -40% to +35% using register parameter CIBM. The
nominal value of 200 µA is measured as a short-circuit
current at pin B to ground.
Test mode Digital CLK
If, due to external circuitry, it is not possible to measure IBM directly, by way of an alternative clock signal
CLKD at pin A can be calibrated to a nominal 1 MHz
in this test mode via register value CIBM.
Test Mode: Analog REF
iC-MH8
A
VREF
B
IBM
Z
VBG
~ 1.24 V
U
VOSR
~ 0.5 V
~ 2.5 V
~ 200 µA
C021107-4acr
VNA
Figure 10: Setting bias current IBM in test mode
Analog REF
Calibration procedure
The calibration procedure described in the following
applies to the optional setting of the internal analog
sine and cosine signals and the mechanical adjustment of the magnet and iC-MH8 in relation to one another.
BIAS SETTING
The BIAS setting compensates for possible manufacturing tolerances in the iC-MH8 devices. A magnetic
field does not need to be present for this setting which
can thus be made either prior to or during the assembly of magnet and iC-MH8.
If the optional setup process is not used, register CIBM
should be set to an average value of 0x8 (which is
equivalent to a change of 0%). As described in the
previous section, by altering the value in register CIBM
in test mode Analog REF current IBM is set to 200 µA
or, alternatively, in test mode Digital CLK signal CLKD
is set to 1 MHz.
MECHANICAL ADJUSTMENT
iC-MH8 can be adjusted in relation to the magnet in
test modes Analog SIN and Analog COS, in which the
Hall signals of the individual Hall sensors can be observed while the magnet rotates.
In test mode Analog SIN the output signals of the sine
Hall sensors which are diagonally opposite one another are visible at pins A, B, Z and U. iC-MH8 and
the magnet are then adjusted in such a way that differential signals VPSIN and VNSIN have the same amplitude and a phase shift of 180°. The same applies
to test mode Analog COS, where differential signals
VPCOS and VNCOS are calibrated in the same manner.
Vsin
+2 V
α
-2 V
+2 V
Vcos
-2 V
C141107-1
Figure 11: Ideal Lissajous curve
CALIBRATION USING ANALOG SIGNALS
In test mode Analog OUT as shown in Figure 5 the internal signals which are transmitted to the sine/digital
converter can be tapped with high impedance. With
a rotating magnet it is then possible to portray the differential signals VSIN and VCOS as an x-y graph (Lissajous curve) with the help of an oscilloscope. In an
ideal setup the sine and cosine analog values describe
a perfect circle as a Lissajous curve, as illustrated by
Figure 11.
At room temperature and with the amplitude control
switched off (ENAC = 0) a rough GAING setting is selected so that at an average fine gain of GAINF = 0x20
(a gain factor of ca. 4.5) the Hall signal amplitudes are
as close to 1 V as possible. The amplitude can then
iC-MH8
12 BIT ANGULAR HALL ENCODER
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be set more accurately by varying GAINF. Variations in
the gain factor, as shown in Figure 12, have no effect
on the Lissajous curve, enabling the angle information
for the interpolator to be maintained.
Vsin
VOSS
α
Vsin
GAING
GAINF
Vcos
α
C141107-3
Vcos
Figure 13: Effect of the sine offset setting
Vsin
VOSC
C141107-2
Figure 12: Effect of gain settings GAING and
GAINF
α
Deviations of the observed Lissajous curve from the
ideal circle can be corrected by varying the amplitude offset (register VOSS, VOSC) and amplitude ratio
(register GCC). Changes in these parameters are described in the following figures 13 to 15. Each of these
settings has a different effect on the interpolated angle
value. A change in the sine offset thus has a maximum
effect on the angle value at 0° and 180°, with no alterations whatsoever taking place at angles of 90° and
270°. When varying the cosine offset exactly the opposite can be achieved as these angle pairs can be set
independent of one another. Setting the cosine/sine
amplitude ratio does not change these angles (0°, 90°,
180° and 270°); however, in-between values of 45°,
135°, 225° and 315° can still be influenced by this parameter.
Vcos
C141107-4
Figure 14: Effect of the cosine offset setting
Vsin
GCC
α
Once calibration has been carried out a signal such as
the one illustrated in Figure 11 should be available.
In the final stage of the process the amplitude control
can be switched back on (ENAC =1) to enable deviations in the signal amplitude caused by variations in
the magnetic field due to changes in distance and temperature to be automatically controlled.
Vcos
C141107-5
Figure 15: Effect of the amplitude ratio
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 17/25
CALIBRATION USING INCREMENTAL SIGNALS
If test mode cannot be used, signals can also be calibrated using the incremental signals or the values read
out serially. In order to achieve a clear relationship between the calibration parameters which have an effect
on the analog sensor signals and the digital sensor values derived from these, the position of the zero pulse
should be set to ZPOS = 0x0 and the rotating direction
should be set to CFGDIR=0, so that the digital signal
starting point matches that of the analog signals.
At an incremental resolution of 8 edges per revolution (CFGRES = 0x1) those angle values can be displayed at which calibration parameters VOSS, VOSC
and GCC demonstrate their greatest effect. When rotating the magnet at a constant angular speed the incremental signals shown in Figure 16 are achieved,
with which the individual edges ideally succeed one
another at a temporal distance of an eighth of a cycle (a 45° angle distance). Alternatively, the angle position of the magnet can also be determined using a
reference encoder, rendering an even rotational action
unnecessary and allowing calibration to be performed
using the available set angle values .
The various possible effects of parameters VOSS,
VOSC and GCC on the flank position of incremental
signals A and B are shown in Figure 16. Ideally, the
distance of the rising edge (equivalent to angle positions of 0° and 180°) at signal A should be exactly half
a period (PER). Should the edges deviate from this in
distance, the offset of the sine channel can be adjusted
using VOSS. The same applies to the falling edges of
the A signal which should also have a distance of half
a period; deviations can be calibrated using the offset
of cosine parameter VOSC. With parameter GCC the
distance between the neighboring flanks of signals A
and B can then be adjusted to the exact value of an
eighth of a cycle (a 45° angle distance).
A
B
Z
VOSS
VOSC
GCC
PER
Figure 16: Calibration using incremental signals
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 18/25
Sine/Digital Converter
This absolute position is used to generate quadrature
signals (ABZ) and commutation signals (UVW). The
zero point of the quadrature signals and the commutation signals can be set seperately. This enables the
commutation at other angles based on the index track
Z.
The resolution of the incremental output signals is programmed with CFGRES.
The value of the 12-bit sine-digital converter is available in full resolution in the ’Extended SSI-Mode’ and
in a resolution according to CFGRES in the ’SSIMode’.
CFGRES(2:0)
0x0
1024
0x1
512
0x2
256
0x3
128
0x4
64
0x5
0x6
0x7
0x8
0x9
0xA
Addr. 0x06; bit 3:0
32
16
8
4
2
1
Table 15: Programming interpolation factor
After the resolution is changed, a module reset is triggered internally and the absolute position is recalculated.
CFGAB(1:0)
Addr. 0x08; bit 1:0
0x0
A and B not inverted
0x1
B inverted, A normal
0x2
A inverted, B normal
0x3
A and B inverted
Table 16: Inversion of AB signals
100%
40%
50%
60%
The iC-MH8 module integrates a high-resolution
sine/digital converter. In the highest output resolution
with an interpolation factor of 1024, 4096 edges per
rotation are generated and 4096 angular steps can be
differentiated. Even in the highest resolution, the absolute position can be calculated in real time at the maximum speed.
A
B
Z
Figure 17: ABZ signals and relative accuracy
The incremental signals can be inverted again independently of the output drivers. As a result, other
phase angles of A and B relative to the index pulse Z
can be generated. The standard is A and B high level
for the zero point, i.e. Z is equal to high.
Figure 17 shows the position of the incremental signals around the zero point. The relative accuracy of
the edges to each other at a resolution setting of 10
bit is better than 10%. This means that, based on a
period at A or B, the edge occurs in a window between
40% and 60%.
CFGHYS(1:0)
Addr. 0x08; bit 7:6
0x0
0,17°
0x1
0,35°
0x2
0,7°
0x3
1,4°
Table 17: Programming angular hysteresis
With rotating direction reversal, an angular hysteresis
prevents multiple switching of the incremental signals
at the reversing point. The angular hysteresis corresponds to a slip which exists between the two rotating
directions. However, if a switching point is approached
from the same direction, then the edge is always generated at the same position on the output. The following figure shows the generated quadrature signals
for a resolution of 360 edges per rotation (interpolation
factor 90) and a set angular hysteresis of 1.4°.
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 19/25
It should be noted then, however, that the maximum
rotation speed is reduced.
10°
0°
−10°
A
B
Z
0°
1.4°
CFGDIR
0
Addr. 0x08; bit 5
Rotating direction CCW
1
Rotating direction CW
0°
Figure 18: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accordance with the hysteresis, the return edge is generated
at A again first. This means that all edges are shifted
by the same value in the rotating direction.
CFGZPOS(7:0)
0x0
0x1
0x2
...
0xFF
Addr. 0x07; bit 7:0
0°
1,4°
2,8°
360
·CFGZPOS
256
358,6°
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z-pulse once over 360°.
CFGMTD(2:0)
Addr. 0x06; bit 6:4
0
Minimum edge spacing 125 ns at IPO 1024 (max.
2 MHz at A)
1
2
3
Minimum edge spacing 250 ns at IPO 1024
Minimum edge spacing 500 ns at IPO 1024 (max.
500 kHz at A)
Minimum edge spacing 1 µs at IPO 1024
4
5
6
7
Minimum edge spacing 2 µs at IPO 1024
Minimum edge spacing 4 µs at IPO 1024
Minimum edge spacing 8 µs at IPO 1024
Minimum edge spacing 16 µs at IPO 1024
Table 19: Minimum edge spacing
The CFGMTD register defines the time in which two
consecutive position events can be output at the highest resolution. The default is a maximum output frequency of 500 kHz on A. This means that at the highest resolution, speeds of 30,000 rpms can still be correctly shown. In the setting with an edge spacing of
125 ns, the edges can be generated even at the highest revolution and the maximum speed. However, the
counter connected to the module must be able to correctly process all edges in this case. The settings
with 2 µs, and 8 µs can be used for slower counters.
Table 20: Rotating direction reversal
The rotating direction can easily be changed with
the bit CFGDIR. When the setting is CCW (counterclockwise, CFGDIR = ’0’) the resulting angular position
values will increase when rotation of the magnet is performed as shown in figure 5. To obtain increasing angular position values in the CW (clockwise) direction,
CFGDIR then has to be set to ’1’.
The internal analoge sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure
5.
CFGSU
0
Addr. 0x08; bit 4
ABZ output "111" during startup
1
AB instantly counting to actual position
Table 21: Configuration of output startup
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, first
the current position is determined. During this phase,
the quadrature outputs are constantly set to "111". In
the setting CFGSU = ’1’, edges are generated at the
output until the absolute position is reached. This enables a detection of the absolute position with the incremental interface.
The converter for the generation of the commutation
signals can be configured for two, four and eight-pole
motors. Three rectangular signals each with a phase
shift of 120° are generated. With two-pole commutation, the sequence repeats once per rotation. With a
four-pole setting, the commutation sequence is generated twice per rotation. With a eight-pole setting, the
commutation sequence is generated four times per rotation.
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 20/25
PSIN
CFGPOLE=00
iC−MH8
CFGPOLE=01
iC−MH8
iC−MH8
U
U
CFGPOLE=10
PCOS
U
CFGPOLE(1:0)
Addr. 0x8; bit 3,2
00
2 pole commutation
01
4 pole commutation
1-
8 pole commutation
V
W
V
W
V
W
Figure 19: UVW signals for different settings of
CFGPOLE
Table 22: Commutation
The zero position of the commutation, i.e. the rising
edge of the track U, can be set as desired over a rotation. Here 256 possible positions are available.
CFGCOM(7:0)
0x00
0x01
...
Addr. 0x09; bit 7:0
0°
-1,4°
- 360
· CFGCOM
256
Table 23: Commutation
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 21/25
Output Drivers
CFGO(1:0)
00
01
10
11
Addr. 0x05; bit 5:4
Incrementral Diff ABZ (U=NA, V=NB, W=NZ)
Incr ABZ + Comm UVW
Commutation Diff UVW (A=NU, B=NV, Z=NW)
Incr. ABZ + AB4 (U=A4, V=B4, W=0)
PSIN
PCOS
A
B
iC−MH8
Six RS422-compatible output drivers are available,
which can be configured for the incremental signals
and commutation signals. The following table on the
CFGO register bits provides an overview of the possible settings.
Z
U
V
W
Figure 20: ABZ differential incremental signals
PSIN
Table 24: Configuration of output drivers
PCOS
A
In the differential incremental mode (CFGO = ’00’, Figure 20), quadrature signals are available on the Pins
A, B and Z. The respective inverted quadrature signals are available on the pins U, V and W. As a result,
lines can be connected directly to the module. Another
configuration of the incremental signals is specified in
the section "Sine/Digital Converter".
iC−MH8
B
Z
U
V
W
Figure 21: ABZ and UVW single ended signals
PSIN
PCOS
A
B
iC−MH8
With CFGO = ’01’ (Figure 21) the ABZ incremental signals and the UVW commutation signals are available
on the six pins. As long as the current angular position is not yet available during the start-up phase, all
commutation signals are at the low level.
Z
U
V
W
With CFGO = ’10’, the third mode (Figure 22) is available for transferring the commutation signals via a differential line. The non-inverted signals are on the pins
U, V and W, the inverted signals on A, B and Z.
Figure 22: UVW differential commutation signals
PSIN
PCOS
A
The ABZ quadrature signals with an adjustable higher
resolution and quadrature signals with one period per
rotation are available in the fourth mode (Figure 23).
Four segments can be differentiated with the pins U
and V. This information can be used for an external
period counter which counts the number of scanned
complete rotations.
iC−MH8
B
Z
U
V
W
Figure 23: ABZ incremental signals / period counter
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 22/25
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
able a high transmission rate. A lower slew rate is offered by the setting CFGDR = ’10’, which is excellent
for longer lines in an electromagnetically sensitive environment. Use of the setting CFGDR = ’11’ is advisable at medium transmission rates with a limited driver
capability.
CFGDR(1:0)
Addr. 0x05; bit 1:0
00
10 MHz 4 mA (default)
01
10 MHz 60 mA
10
300 kHz 60 mA
11
3 MHz 20 mA
Table 25: Driver property
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital input on the same assembly. With the setting CFGDR =
’01’ the same transmission speed is available and the
driver power is sufficient for the connection of a line
over a short distance. Steep edges on the output en-
TRIHL
00
01
10
Addr. 0x05; bit 3:2
Push Pull Output Stage
Highside Driver
Lowside Driver
11
Tristate
Table 26: Tristate Register
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.
Serial Interface
The serial interface is used to read out the absolute
position and to parameterize the module. For a de-
tailed description of the protocol, see separate interface specification.
MA
CDM
SLI
SLO
Ack Start CDS D11 D10
D0
nE
nW CRC5 CRC4
CRC0 Stop
Timeout
Data Range
Figure 24: Serial Interface Protocol
The sensor sends a fixed cycle-start sequence containing the Acknowledge-, Start and Control-Bit followed by the binary 12 bit sensor data. The low-active
error bit nE a ’0’ indicates an error which can be further identified by reading the status register 0x77. The
following bit nW is always at ’1’ state. Following the
6 CRC bits the data of the next sensors, if available,
are presented. Otherwise, the master stops generating clock pulse on the MA line an the sensor runs into
a timeout, indicating the end of communication.
Serial Interface
Protocol
Cycle start sequence
Lenght of sensor data
CRC Polynom
CRC Mode
Multi Cycle Data
Mode C
max. Data Rate
10 MHz
Ack/Start/CDS
12 Bit + ERR + WARN
0b1000011
inverted
not available
Table 27: Interface Protocol
ENSSI
0
1
Addr. 0x05; bit 7
Extended SSI-Mode
SSI-Mode
Table 28: Activation of SSI mode
The extended SSI-Mode is active if V(VZAP) = V()ZAP
or Bit ENSSI is 0. The extended SSI-Mode must be
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 23/25
forced by applying V(VZAP) = V()ZAP before changing the value of Bit ENSSI to avoid an aborted register
communication.
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. (The data is transmitted as Gray code with trailing zeros.)
Figure 25: SSI protocol, data GRAY-coded
The register range 0x00 to 0x0F is equivalent to the
settings with which the IC can be parameterized. The
settings directly affect the corresponding switching
parts. The range 0x10 to 0x1F is read-only and reflects
the contents of the integrated zapping diodes. Following programming the data can be verified via these addresses. After the supply voltage is connected, the
contents of the zapping diodes are copied to the RAM
area 0x00 to 0x0F. Then the settings can be overwritten via the serial interface. Overwriting is not possible
if the CFGPROT bit is set.
Errors in the module are signaled via the error message output NERR. This open-drain output signals an
error if the output is pulled against VND. If the error condition no longer exists, then the pin is released
again after a waiting time of approximately 1 ms. If the
integrated pull-up resistor is deactivated with DPU =
’1’, then an external resistor must be provided. With
DPU = ’0’ it brings the pin up to the high level again.
DPU
Addr. 0x04; bit 6
0
1
Pull-up activated
Pull-up deactive
Table 29: Activation of NERR pull-up
With the profile ID, the data format can be requested
for the following sensor data cycles in the module. A
read operation at address 0x42 results in 0x2C, with is
the equivalent to 12-bit single-cycle data.
The status register provides information on the status
of the module. There are 5 different errors that can
be signaled. Following unsuccessful programming of
the zapping diodes, the bit PROGERR is set. If an
attempt is made to read the current position via the serial interface during the start-up phase, an error is signaled with ERRSDATA, as the actual position is not yet
known. The ERRAMAX bit is output to signal that the
amplitude is too high, while the ERRAMIN bit signals
an amplitude which is too low, caused, for example, by
too great a distance to the magnet. If the NERR pin
is pulled against VND outside the module, this error is
also signaled via the serial interface. The ERREXT bit
is then equal to ’1’. The error bits are reset again after
the status register is read out at the address 0x77. The
error bit in the data word is then also read in the next
cycle as ’0’.
CFGTOS
0
1
x
CFGTOB
0
0
1
Timeout
16 µs
2 µs
2 µs
Table 30: Timeout for sensor data
The timeout can be programmed to a shorter value
with the CFGTOS bit. However, this setting is reset
to the default value 16 µs again following a reset. The
timeout can be permanently programmed for faster
data transmission with the CFGTOB register via a zapping diode. Resetting to slower data transmission is
then not possible.
The registers 0x7D to 0x7F are reserved for the manufacturer and can be provided with an ID so that the
manufacturer can identify its modules
OTP Programming
CFGPROT
0
Addr. 0x05; bit 6
no protection
ENHC
0
Addr. 0x0f; bit 7
Default setting
1
write/read protection
1
ZAP diode testing: Use a higher current for reading
the ZAP diodes memory (0x10-0x1f)
Table 31: Write/read protection of configuration
Table 32: Enable High Current
With CFGPROT = ’0’, the registers at the addresses
0x00 to 0x0F and 0x78 to 0x7F are readable and write-
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12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 24/25
able. The addresses 0x10 to 0x1F and 0x77 are readonly. With CFGPROT = ’1’, all registers except the addresses 0x7B and 0x7C are write-protected; the addresses 0x77 to 0x7F are readable, while all others
are read-protected.
100 nF
100 nF
+ 5V
VPD VPA
iC-MH8
An internal programming algorithm for the ZAP diodes
is started by setting the bit PROGZAP. This process
can only be successful if the voltage at VZAP is greater
than 6.5 V and the test register TEST (2:0) is not set.
Following programming, the register is reset internally
again. In the process, the bit PROGOK is set in the
status register (address 0x77) when programming is
successful, and the bit PROGERR if it is not.
Programming
Board
VZAP
MA
SLI
SLO
+ 7V
Serial
Interface
100 nF
VND VNA1 VNA2
10 µF
0V
Figure 26: Recommended setup for external programming. A short low impedance path (shown in
light red) must be provided directly from pin
VZAP to pins VNA1, VNA2.
The ZAP memory can be tested by reading the register range 0x10-0x1f. This test can be done with with a
higher readout current (Bit ENHC=1) to simulate deteriorated working conditions.
For reliable ROM writing, a low impedance connection
path as shown in Figure 26 must be established for the
VZAP blocking capacitor (about 100 nF) between pin
VZAP and pins VNA1, VNA2 to ensure stable VZAP
voltage during programming. A further capacitor of
10 µF which may be located externally (e.g. on the programming board) is recommended for additional blocking purpose.
Figure 27: Example PCB layout showing low impedance
A typical PCB layout may look like the one shown in
Figure 27.
connection of capacitors to supply voltages
(VPA, VPD, VZAP) and common ground
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MH8
12 BIT ANGULAR HALL ENCODER
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Rev A0.9, Page 25/25
ORDERING INFORMATION
Type
Package
Order Designation
iC-MH8
QFN28
iC-MH8 QFN28-5x5
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners